HFA3861 Intersil Corporation, HFA3861 Datasheet
HFA3861
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HFA3861 Summary of contents
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... The HFA3861 has on-board A/D’s for analog I and Q inputs and outputs, for which the HFA3783 IF QMODEM is recommended. Differential phase shift keying modulation schemes DBPSK and DQPSK, with data scrambling capability, are available along with Complementary Code Keying to provide a variety of data rates. Built-in fl ...
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... Data Demodulation in the CCK Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Demodulator Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overall Eb/N0 Versus BER Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Offset Tracking Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Carrier Offset Frequency Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A Default Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thin Plastic Quad Flatpack Packages (TQFP HFA3861 PAGE ...
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... I ADC Q ADC REFOUT I/O LO PLL DAC Q DAC HFA3783 QUAD IF REF IN REF IN TYPICAL TRANSCEIVER APPLICATION CIRCUIT USING THE HFA3861 The four-digit file numbers are shown in the Typical Application Diagram, and correspond to the appropriate circuit DAC 1 RF AGC ADC 7 CTL WEP ...
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... TXD is an input, used to transfer MAC Payload Data Unit (MPDU) data from the MAC or network processor to the HFA3861. The data is received serially with the LSB first. The data is clocked in the HFA3861 at the rising edge of TXCLK. TXCLK is a clock output used to receive the data on the TXD from the MAC or network processor to the HFA3861, synchronously ...
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... Serial Data Input in 3 wire mode described in Tech Brief TBD. This pin is not used in the 4 wire interface described in this data sheet. It should not be left floating. R input to the HFA3861 used to change the direction of the SD bus when reading or writing data on the SD bus. R/W must be set up prior to the rising edge of SCLK. A high level indicates read while a low level is a write Chip select for the device to activate the serial control port. The CS doesn’ ...
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... SCLK 7 SD MSB R/W CS NOTES: 1. The HFA3861 always uses the rising edge of SCLK to sample address and data and to generate read data. 2. These figures show the controller using the falling edge of SCLK to generate address and data and to sample read data. 7 SCLK SD 7 MSB ...
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... Figure 4. Assertion of TX_PE will initialize the generation of the preamble and header. TX_RDY, which is an output from the HFA3861, is used (if needed) to indicate to the external processor that the preamble has been generated and the device is ready to receive the data packet (MPDU transmitted from the external processor ...
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... RXCLK is an output from the HFA3861 and is the clock for the serial demodulated data on RXD. MD_RDY is an output from the HFA3861 and it may be set to go active after the SFD or CRC fields. Note that RXCLK becomes active after the Start Frame Delimiter (SFD) to clock out the Signal, Service, and Length fields, then goes inactive during the header CRC field ...
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... DACs to the HFA3783. These are DC coupled and digitally filtered. Test Port The HFA3861 provides the capability to access a number of internal signals and/or data through the Test port, pins TEST 7:0. The test port is programmable through configuration register (CR 34). Any signal on the test port can also be read from configuration register (CR50) via the serial control port ...
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... Header/Packet Description The HFA3861 is designed to handle packetized Direct Sequence Spread Spectrum (DSSS) data transmissions. The HFA3861 generates its own preamble and header information. It uses two packet preamble and header configurations. The first is backwards compatible with the existing IEEE 802.11-1997 1 and 2Mbps modes and the ...
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... See IEEE STD 802.11 for definition of the other bits. These bits are not used by the HFA3861. Length Field (16 Bits) - This field indicates the number of microseconds it will take to transmit the payload data (PSDU). The external controller (MAC) will check the length fi ...
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... CR32 bit NOTE: Be advised that the IEEE 802.11 compliant scrambler in the HFA3861 has the property that it can lock up (stop scrambling) on random data followed by repetitive bit patterns. The probability of this happening is 1/128. The patterns that have been identified are all ze- ros, all ones, repeated 10s, repeated 1100s, and repeated 111000s ...
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... PHASE CHANGE (+j ) networking scheme. The Clear Channel Assessment (CCA) monitors the environment to determine when it is feasible to transmit. The CCA circuit in the HFA3861 can be programmed / function of RSSI (energy detected on the channel), 0 CS1, CS2, or both. The CCA output can be ignored, allowing transmissions independent of any channel conditions ...
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... The PRISM baseband processor, HFA3861 uses differential demodulation for the initial acquisition portion of the message processing and then switches to coherent demodulation for the MPDU demodulation. The HFA3861 is designed to achieve rapid settling of the carrier tracking loop during acquisition. Rapid phase fluctuations are handled with a relatively wide loop bandwidth ...
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... SYMBOLS AGC SETTLE AND LOCK AND INITIAL DETECTION 15 HFA3861 case time line example assumes that the signal arrives part way into the first dwell such as to just barely catch detection. The signal and the scanning process are asynchronous and the signal could start anywhere. In this timeline assumed that the signal is present in the fi ...
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... ANTSEL (40) (62) TX_PE FIGURE 11. DSSS BASEBAND PROCESSOR, TRANSMIT SECTION PN Correlators Description There are two types of correlators in the HFA3861 baseband processor. The first is a parallel matched correlator that correlates for the Barker sequence used in preamble, header, and PSK data modes. This PN correlator is designed to handle BPSK spreading with carrier offsets up to 50ppm and 11 chips per symbol ...
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... RATE CORRELATION TIME T0 CORRELATOR OUTPUT IS THE RESULT OF CORRELATING THE PN SEQUENCE WITH THE RECEIVED SIGNAL 17 HFA3861 TABLE 8. DQPSK DATA DECODER PHASE SHIFT +90 +180 -90 The data scrambler and de-scrambler are self synchronizing circuits. They consist of a 7-bit shift register with feedback of some of the taps of the register. The scrambler is designed to insure smearing of the discrete spectrum lines produced by the PN code ...
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... RX-RF-AGC (38) DAC 6-BIT RXI (10, 11) A/D 6 6-BIT RXQ (13, 14) A/D 6 ANTENNA SWITCH ANTSEL (40) CONTROL GENERATOR (63) RESET FIGURE 13. DSSS BASEBAND PROCESSOR, RECEIVE SECTION 18 HFA3861 GND (ANALOG) V (DIGITAL) DD (9, 15, 20, 25, 28) (2, 8, 37, 41, 57) AGC CLEAR CHANNEL CONTROL ASSESSMENT/ SIGNAL QUALITY 8 COMPLEX 8 MULTIPLY SIN/COS ROM FAST ...
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... The symbol clock is tracked by a sample interpolator that can adjust the sample timing forwards and backwards by 72 increments of 1/8th chip. This approach means that the HFA3861 can only track an offset in timing for a finite interval before the limits of the interpolator are reached. Thus, continuous demodulation is not possible. ...
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... The PRISM baseband processor is designed to accept data clock offsets 25ppm for each end of the link (TX and RX). This effects both the acquisition and the tracking performance of the demodulator. The budget for clock offset error is 0.75dB at 50ppm. No appreciable degradation was seen for operation in AWGN at 50ppm. 20 HFA3861 11 12 1.E+00 1.E+00 1.E-01 1.E-01 1 ...
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... A Default Register Configuration The registers in the HFA3861 are addressed with 7-bit numbers where the lower 1 bit of an 8-bit hexadecimal address is left as unused. This results in the addresses being in increments shown in the table below. Table 9 shows the register values for a default 802.11 configuration with various rate configurations ...
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... This register is written, then the data is loaded into register 23 as per the following table. AGC REGISTER SETTINGS CR22 DECIMAL HFA3861 TABLE 9. CONTROL REGISTER VALUES (Continued) NAME CR23 HEX ...
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... Control Registers The following tables describe the function of each control register along with the associated bits in each control register. CONFIGURATION REGISTER 0 ADDRESS (0h) R PART/VERSION CODE Bit 7:4 Part Code 1 = HFA3861 series Bit 3:0 Version Code 0 = 3861 base Version CONFIGURATION REGISTER 1 ADDRESS (02h) R/W I/O POLARITY This register is used to define the phase of clocks and other interface signals ...
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... R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Bit 1 antenna choice for Receive 0 = Antenna select pin low 1 = Antenna select pin high Bit 0 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. 24 HFA3861 ...
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... Bit 2 RF A/D clock 0 = enable 1 = disable Bit 1 I A/D clock 0 = enable 1 = disable bit 0 Q A/D clock 0 = enable 1 = disable CONFIGURATION REGISTER 13 ADDRESS (1Ah) R/W A/D TEST MODES 2 Bit 7 Standby 1 = enable 0 = disable Bit 6 SLEEPTX 1 = enable 0 = disable Bit 5 SLEEP enable 0 = disable Bit 4 SLEEP enable 0 = disable 25 HFA3861 ...
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... AGC mid Sat counts (0-15 range) Bits 3:0 AGC low Sat Count (0-15 range) CONFIGURATION REGISTER 17 ADDRESS (22h) R/W AGC CONTROL 4 Bits 7:6 Unused, set to 0 Bit 5:0 AGC timer count (number of clocks in AGC cycle, 0-63 range) CONFIGURATION REGISTER 18 ADDRESS (24h) R/W AGC CONTROL 5 Bits 7:4 AGC high sat attenuation (0-60) Bits 3:0 AGC (0-15 range) 26 HFA3861 ...
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... AGC override Enable, if set, CR25 controls receiver gain in both RF and normal 1 = enabled Bit 1 AGC random I/Q allows random data on AGC 6 bit I/Q inputs enabled 0 = normal 1 = enabled Bit 0 AGC test math- always accumulates in gain adjust, always outputs mean power from log table normal 1 = enabled 27 HFA3861 ...
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... Bit 3 Disable spread sequence for 1 and 2Mbps 0 = Normal 1 = disabled Bit 2 Disable scrambler 0 = normal scrambler operation 1 = scrambler disabled (taps set to 0) Bit 1 PN generator enable (RX 44MHz clock not enabled 1 = enabled Bit 0 PN generator enable (RX 22MHz clock not enabled 1 = enabled 28 HFA3861 ...
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... CONFIGURATION REGISTER ADDRESS 50 (66h) R TEST BUS READ Bit 7:0 reads value on test bus CONFIGURATION REGISTER ADDRESS 51 (68h) R SIGNAL QUALITY MEASURE Bit 7:0 measures signal quality based on the SNR in the carrier tracking loop CONFIGURATION REGISTER ADDRESS 52 (6Ah) R RECEIVED SIGNAL FIELD Bit 7:0 8-bit value of received signal field 29 HFA3861 ...
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... CONFIGURATION REGISTER ADDRESS 63 (80h) R CALCULATED CRC ON RECEIVED HEADER, HIGH Bit 7:6 signal field value 5 Bit 5 SFD found Bit 4 Short preamble detected Bit 3 valid signal field found Bit 2 valid CRC 16 Bit 1 Antenna used on last good packet NA Bit 0 not used 30 HFA3861 ...
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... Hold TXD to TX_CLK Hi TX_CLK to TX_PE Inactive (1Mbps) TX_CLK to TX_PE Inactive (2Mbps) TX_CLK to TX_PE Inactive (5.5Mbps) TX_CLK to TX_PE Inactive (11Mbps) TX_RDY Inactive to Last Chip of MPDU Out 31 HFA3861 Thermal Information Thermal Resistance (Typical, Note 4) +0.5V TQFP Package Maximum Storage Temperature Range . . . . . . . . . . -65 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 Maximum Lead Temperature (Soldering 10s) ...
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... Minimum time to insure Reset. RESET must be followed by an RX_PE pulse to insure proper operation. This pulse should not be used for first receive or acquisition. 19. Delay from TXCLK to inactive edge of TXPE to prevent next TXCLK. Because TXPE asynchronously stops TXCLK, TXPE going inactive within 40ns of TXCLK will cause TXCLK minimum hi time to be less than 40ns. 32 HFA3861 o = 3.0V to 3. ...
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... Not tested, but characterized at initial design and at major process/design changes. Test Circuit NOTES: 21. Includes Stray and JIG Capacitance. 22. Switch S Open for I and I 1 CCSB CCOP Waveforms SCLK SDI, R/W, SD (AS OUTPUT) R HFA3861 (Note 20) MIN 0. (NOTE 22) S DUT (NOTE 21) IOH EQUIVALENT CIRCUIT ...
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... RLP RX_PE MD_RDY RX_CLK RXD CCA, RSSI NOTE: RXD, MD_RDY is output two MCLK after RXCLK rising to provide hold time. RSSI Output on TEST (5:0). TEST 0-7, CCA, ANTSEL, TEST_CK 34 HFA3861 t PEH t t TCD TCD TDH t TDS FIGURE 18. TX PORT SIGNAL TIMING ...
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... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 35 HFA3861 Q64.10x10 64 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE SYMBOL -B- e SEATING PLANE A NOTES: 1 ...