MC92500ZQ Freescale Semiconductor, Inc, MC92500ZQ Datasheet
MC92500ZQ
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MC92500ZQ Summary of contents
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... Internal SCAN (ISCAN) Egress Cell Processor (EPU) Figure 1. Representative Block Diagram Order this document by MC92500/D MC92500 ATM Cell Processor ZQ SUFFIX GTBGA CASE 5203 Ordering Information Device Package MC92500ZQ 256 GTBGA Utopia Ingress Switch I/F I/F (ISWI) Memory JTAG Boundary Test Scan Port (FMC) Utopia ...
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ATM NETWORK 1.1 ATM Network Description ................................... 3 1.2 ATM Network Applications ................................. 4 2. FUNCTIONAL DESCRIPTION 2.1 System Functional Description .......................... 5 2.2 MC92500 Functional Description ....................... 5 2.2.1 Ingress Cell Flow ......................................... 6 2.2.2 Egress Cell Flow ...
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ATM Network Description A typical ATM network consists of user end stations that transmit and receive 53-byte data cells on virtual connections (see Figure 1). The virtual connections are implemented using physical links and switching sys- tems that interconnect ...
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ATM Network Applications The MC92500, an Asynchronous Transfer Mode cell- processing device, is ideally suited for use in the inter- face between a PHY-layer device and an ATM switch fabric. The primary application of the MC92500 is ATM- layer ...
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System Functional Description A serial transmission link operating 155.52Mbit/ sec (PHY) is coupled to the MC92500 via a byte-based interface. The transmission link timing is adapted to the MC92500 and switch timing by means of internal ...
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Ingress Cell Flow In the Ingress direction, the MC92500 extracts cells from the FIFO in the PHY. Cell discrimination based on pre-defined header field values is performed to recog- nize unassigned and invalid cells. Cell rate decoupling is accomplished ...
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Egress Features The Egress section (Egress refers to cells being trans- ferred from the switch to the physical interface): • Receives ATM cells and associated switch context parameters (including congestion notification) from the switch using a UTOPIA- style interface • ...
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Ingress PHY Interface (IPHI) The Ingress PHY Interface (IPHI) block receives cells on a byte basis from the ATM PHY layer using the UTOPIA standard interface. It assembles the cells and synchronizes their arrival to the MC92500 cell process- ...
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Egress PHY Interface (EPHI) The Egress PHY Interface (EPHI) block takes the pro- cessed cells from the EPU, disassembles them into bytes and transfers them to the physical layer using the UTOPIA standard interface. Unassigned cells may be inserted ...
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External Address Compression Device - this memory space may be used by the processor to access the ex- ternal address compression device. The External Address Compression Device may be accessed when the MC92500 is in Setup Mode or during maintenance ...
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EXTERNAL MEMORY DESCRIPTION 4.1 MC92500 External Memory The MC92500 uses external memory to store the data- base (context information) relating to the processing of cells on a per-connection basis. The MC92500 can ac- cess External Memory with 16- or ...
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Ingress Billing Counters Table pointer Egress Billing Counters Table pointer Flags Table pointer Context Parameters Table pointer Ingress Policing Counters Table pointer VC Table pointer Multicast Table pointer OAM Table pointer VP Table pointer Dump Vector Table pointer Egress Link ...
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Functional Signal Groups This section contains brief descriptions of the input and output signals in their functional groups, as shown in Figure 7. Each signal is explained briefly. ARST CONTROL ENID AMODE(0-1) MCLK MADD(2-25) MWR MSEL MDS MWSH PROCESSOR ...
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Receive Data Bus (RXDATA0 - RXDATA7) This input data bus receives octets from the PHY chip. When RXENB is active, RXDATA is sampled into the MC92500. Receive Data Bus Parity (RXPRTY) This input is the odd parity over RXDATA. This ...
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Receive Start Of Cell (SRXSOC) This 3-state output, when high, indicates that the current data on SRXDATA is the first byte of a cell structure (including the overhead bytes output on the rising edge of SRXCLK. Receive Switch ...
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Control Signals These signals are used to control the MC92500. ATMC Power-Up Reset (ARST) This input signal is used for power-up reset of the entire chip. It must be asserted for at least the time re- quired by the ...
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MP Cell Out Request (MCOREQ) This output signal may be used by an external DMA device as a control line indicating when to start a new cell extraction cycle from the MC92500. This out- put is asserted whenever the Cell ...
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P CELL CNTXT INSR LKUP from PHY layer ADDR IPHI CMPR Ingress Cell Processing Unit (IPU) Microprocessor Interface (MPIF) 6.2 Interface to Physical Layer - Cell Assembly The Ingress Physical-Layer Interface (IPHI) block re- ceives cell data from the ...
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Address Compression The purpose of the ingress address compression is to map the address field(s) in the header of the received cell into a pointer to the entry in the Context Table that relates to the cell’s virtual connection. ...
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A “don’t touch” option is provided to apply the UPC/ NPC algorithm for statistical purposes without tagging or discarding the violating cells. A UPC/NPC mechanism can be used to enforce the sum of several connections. This method is likely to ...
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Transfer from Switch The Egress Switch Interface (ESWI) block contains a cell FIFO. Data is received from the switch at the rate of one byte per clock cycle. The data structure received from the switch includes overhead routing information ...
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Multicast Identifier Translation Multicasting involves copying a cell that arrived at the switch and transmitting it on multiple physical links. In the general case the ECI of the connection to which the cell belongs will be different on each ...
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MC92500 Modes of Operation The MC92500 has two basic modes of operation, Set- up and Operate. After reset, the MC92500 is in Setup Mode. Switching to Operate Mode is accomplished by writing to a pseudo-register. 8.1.1 Setup Mode The ...
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Electrical Specifications 9.1.1 Clocks Num C1 ACLK Cycle Time C2 ACLK Pulse Width Low C3 ACLK Pulse Width High C4 ACLK Rise/Fall Time C5 MCLK Cycle Time C6 MCLK Pulse Width Low C7 MCLK Pulse Width High C8 MCLK ...
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Microprocessor Interface Timing The timing diagrams in this section are intended to con- vey setup and hold values for input signals and propa- Num 1 MSEL setup time before MCLK falling edge 2 MSEL hold time after MCLK falling ...
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MCLK MSEL MADD [25:2] MWR MDATA [31:0] MDTACK Figure 12. Cell Extraction Register Read Access Timing MOTOROLA Data Valid MC92500 ...
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MCLK MSEL MADD [25:2] MWR MDATA [31:0] MDTACK Figure 13. Maintenance Read Access Timing MC92500 Data Valid MOTOROLA 27 ...
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MCLK MSEL MADD [25:2] MWR MDATA [31:0] MDTACK Figure 14. General Register Read Access Timing MOTOROLA Data Valid MC92500 ...
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MCLK MSEL MADD [25:2] MWR MWSH/L MDS MDATA [31:0] MDTACK Figure 15. Cell Insertion Register Write Access / Maintenance Write Access Timing MC92500 Data Valid ...
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MCLK MSEL MADD [25:2] MWR MWSH/L MDS MDATA [31:0] MDTACK Figure 16. General Register Write Access Timing MOTOROLA Data Valid 28 MC92500 ...
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MCLK MCIREQ, MCOREQ, EMMREQ MC92500 26 Figure 17. DMA Request Signals Timing 26 MOTOROLA 31 ...
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PHY Interface Timing Num 51 setup time before ACLK rising edge 52 hold time after ACLK rising edge 53 propagation delay from rising edge of ACLK ACLK RXEMPTY, RXSOC, RXDATA, RXPRTY, RXPHYID 53 RXENB ACLK TXFULL, TXCCLR 53 TXDATA, ...
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Switch Interface Timing Num 61 setup time before SRXCLK/STXCLK rising edge 62 hold time after SRXCLK/STXCLK rising edge 63 propagation delay from rising edge of SRXCLK/STXCLK 64 SRXCLK rising edge to outputs active 65 SRXCLK rising edge to outputs ...
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External Memory Interface Timing This section represents External Memory timing pa- rameters for the default definition. These values are for 9.1.6 Write Cycle Timing Num 81 Write Pulse Width . a 82 EMWR assertion time. EMWR low to end ...
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Read Cycle Timing Num EMBSH0-3, EMBSL0-3, EACEN 90 Enable Pulse Width. EMBSH0-3, EMBSL0-3, EACEN 92 Address Setup Time. 93 Address Hold Time. EMADD Invalid to EMBSH0-3, EMBSL0-3, EACEN Low 94 Data Driving Start Point. 95 Data Setup Time. EMDATA ...
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DC Electrical Characteristics Table 3. Preliminary Electrical Characteristics Symbol Parameter V DC Supply Voltage Input Voltage (5V Tolerant) in 4,5 Vout DC Output Voltage I DC Current Drain per Pin, Any Single Input or Output ...
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Table 4. Preliminary DC Electrical Characteristics (T Parameter V TTL Inputs (5V Tolerant TTL Inputs (5V Tolerant Input Leakage Current Pull Resistor with Pullup Resistor * with Pulldown Resistor * † I Output High ...
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Pin Assignment Pack- Pack- Signal Signal age age Name Name Pin Pin C3 TESTOUT A8 MSEL A2 ACLK D9 MCIREQ B2 TESTSEL C9 MCOREQ D5 MADD:17 B9 MDTACK A3 MADD:16 A9 MINT B4 MADD:15 D10 EMMREQ C5 MADD:14 C10 ...
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PBGA Pin Diagram/Power Pin Assignment (Bottom View) VDD - D6, D11, D15, F4, F17, K4, L17, R4, R17, U6, U10, U15, B19, B18, C4, D3, W2, Y2, V19, W19, P18, V14 VSS - A1, D4, D8, D13, D17, H4, ...
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PBGA Case Outline GTPAC - (used for Prototype and Production) ZQ Package Dimensions for OMPAC MILLIMETERS INCHES DIM MIN MAX MIN MAX A 26.90 27.10 1.0590 1.0669 B 26.90 ...
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Notes: MC92500 MOTOROLA 41 ...
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of ...