MCM63F733ATQ11 Freescale Semiconductor, Inc, MCM63F733ATQ11 Datasheet

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MCM63F733ATQ11

Manufacturer Part Number
MCM63F733ATQ11
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
128K x 32 Bit Flow–Through
BurstRAM Synchronous
Fast Static RAM
vide a burstable, high performance, secondary cache for the PowerPC
other high performance microprocessors. It is organized as 128K words of 32
bits each, fabricated with high performance silicon gate CMOS technology.
This device integrates input registers, a 2–bit address counter, and high speed
SRAM onto a single monolithic circuit for reduced parts count in cache data
RAM applications. Synchronous design allows precise cycle control with the
use of an external clock (K). CMOS circuitry reduces the overall power con-
sumption of the integrated functions for greater reliability.
enable (G) and Linear Burst Order (LBO) are clock (K) controlled through
positive–edge–triggered noninverting registers.
addresses can be generated internally by the MCM63F733A (burst sequence
operates in linear or interleaved mode dependent upon state of LBO) and con-
trolled by the burst address advance (ADV) input pin.
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte
writes SBx are asserted with SW. All bytes are written if either SGW is asserted
or if all SBx and SW are asserted.
from the memory array.
operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC
Standard JESD8–5 compatible.
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MOTOROLA FAST SRAM
REV 2
3/20/98
Motorola, Inc. 1998
The MCM63F733A is a 4M–bit synchronous fast static RAM designed to pro-
Addresses (SA), data inputs (DQx), and all control signals except output
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
Write cycles are internally self–timed and are initiated by the rising edge of the
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
For read cycles, a flow–through SRAM allows output data to simply flow freely
The MCM63F733A operates from a 3.3 V core power supply and all outputs
MCM63F733A–10 = 10 ns Access/13 ns Cycle (75 MHz)
MCM63F733A–11 = 11 ns Access/15 ns Cycle (66 MHz)
3.3 V + 10% / – 5% Core, Power Supply, 2.5 V or 3.3 V I/O Supply
ADSP, ADSC, and ADV Burst Control Pins
Selectable Burst Sequencing Order (Linear/Interleaved)
Internally Self–Timed Write Cycle
Byte Write and Global Write Control
Single–Cycle Deselect
Sleep Mode (ZZ)
100–Pin TQFP Package
and
MCM63F733A
Order this document
by MCM63F733A/D
CASE 983A–01
TQ PACKAGE
MCM63F733A
TQFP
1

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MCM63F733ATQ11 Summary of contents

Page 1

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Advance Information 128K x 32 Bit Flow–Through BurstRAM Synchronous Fast Static RAM The MCM63F733A is a 4M–bit synchronous fast static RAM designed to pro- vide a burstable, high performance, secondary cache for the PowerPC other high ...

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LBO ADV K ADSC ADSP SA SA1 SA0 SGW SW SBa SBb SBc SBd SE1 SE2 SE3 G MCM63F733A 2 FUNCTIONAL BLOCK DIAGRAM BURST COUNTER K2 CLR 2 17 ADDRESS REGISTER WRITE REGISTER a WRITE REGISTER b WRITE REGISTER c ...

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NC DQc DQc V DDQ V SS DQc DQc DQc DQc DDQ DQc DQc DQd DQd V DDQ V SS DQd DQd DQd DQd DDQ DQd DQd NC ...

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PIN DESCRIPTIONS Pin Locations (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79 12, 13 (d) 18, 19, ...

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TRUTH TABLE (See Notes 1 through 5) Address Next Cycle Used SE1 Deselect None 1 Deselect None 0 Deselect None 0 Deselect None X Deselect None X Begin Read External 0 Begin Read External 0 Continue Read Next X Continue ...

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INTERLEAVED BURST ADDRESS TABLE 1st Address (External) 2nd Address (Internal X00 X01 X10 X11 WRITE TRUTH TABLE Cycle Type Read Read Write Byte a ...

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DC OPERATING CONDITIONS AND CHARACTERISTICS ( 3 10%, – 5 Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS: 2.5 V I/O Supply Parameter Supply Voltage I/O Supply Voltage Input Low Voltage ...

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SUPPLY CURRENTS Parameter Input Leakage Current ( Output Leakage Current ( DDQ ) AC Supply Current (Device Selected, All Outputs Open, Freq = Max) Includes V DD Only CMOS Standby ...

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AC OPERATING CONDITIONS AND CHARACTERISTICS ( 3 10%, – 5 Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . ...

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OUTPUT Figure 3. Lumped Capacitive Load and Typical Derating Curve MCM63F733A 10 OUTPUT Ω Ω 1.25 V Figure 2. AC Test Load 2400 2200 2000 1800 1600 1400 1200 C L 1000 ...

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PULL–UP VOLTAGE (V) I (mA) MIN I (mA) MAX – 0.5 – – 38 0.8 – 38 1.25 – 30 1.5 – 27 2.3 0 2.7 0 2.9 0 PULL–UP VOLTAGE (V) I (mA) MIN I (mA) MAX ...

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MCM63F733A 12 MOTOROLA FAST SRAM ...

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É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É ...

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... D E Q(C) Q(D) D(E) ORDERING INFORMATION (Order by Full Part Number) MCM 63F733A Blank = Trays Tape and Reel Speed ( ns ns) Package (TQ = TQFP) MCM63F733ATQ11 MCM63F733ATQ10R MCM63F733ATQ11R ( ADSC ADV SE1 SE2 LBO ...

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H A– –A– 100 1 D1 TIPS 0.20 (0.008) C A–B A –H– –C– SEATING PLANE 0.05 (0.002 VIEW AB MOTOROLA FAST SRAM PACKAGE DIMENSIONS TQ ...

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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of ...

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