MCM63P733ATQ133 Freescale Semiconductor, Inc, MCM63P733ATQ133 Datasheet

MCM63P733ATQ133

Manufacturer Part Number

MCM63P733ATQ133

Description

Manufacturer

Freescale Semiconductor, Inc

Datasheet

1.MCM63P733ATQ133.pdf (16 pages)

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

128K x 32 Bit Pipelined

BurstRAM Synchronous

Fast Static RAM

vide a burstable, high performance, secondary cache for the PowerPC

other high performance microprocessors. It is organized as 128K words of 32

bits each, fabricated with high performance silicon gate CMOS technology.

This device integrates input registers, an output register, a 2–bit address

counter, and high speed SRAM onto a single monolithic circuit for reduced

parts count in cache data RAM applications. Synchronous design allows pre-

cise cycle control with the use of an external clock (K). CMOS circuitry reduces

the overall power consumption of the integrated functions for greater reliability.

enable (G) and Linear Burst Order (LBO) are clock (K) controlled through

positive–edge–triggered noninverting registers.

addresses can be generated internally by the MCM63P733A (burst sequence

operates in linear or interleaved mode dependent upon state of LBO) and con-

trolled by the burst address advance (ADV) input pin.

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

nous write enable (SW) are provided to allow writes to either individual bytes or

to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls

DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte

writes SBx are asserted with SW. All bytes are written if either SGW is asserted

or if all SBx and SW are asserted.

edge–triggered output register and then released to the output buffers at the next

rising edge of clock (K).

operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC

standard JESD8–5 compatible.

PowerPC is a trademark of IBM Corp.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 1

3/24/98

MOTOROLA FAST SRAM

Motorola, Inc. 1998

The MCM63P733A is a 4M–bit synchronous fast static RAM designed to pro-

Addresses (SA), data inputs (DQx), and all control signals except output

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

Write cycles are internally self–timed and are initiated by the rising edge of the

Synchronous byte write (SBx), synchronous global write (SGW), and synchro-

For read cycles, pipelined SRAMs output data is temporarily stored by an

The MCM63P733A operates from a 3.3 V core power supply and all outputs

MCM63P733A–133 = 4 ns Access/7.5 ns Cycle (133 MHz)

MCM63P733A–117 = 4.2 ns Access/8.5 ns Cycle (117 MHz)

MCM63P733A–100 = 4.5 ns Access/10 ns Cycle (100 MHz)

MCM63P733A–90 = 5 ns Access/11 ns Cycle (90 MHz)

3.3 V + 10% / – 5% Core, Power Supply, 2.5 V or 3.3 V I/O Supply

ADSP, ADSC, and ADV Burst Control Pins

Selectable Burst Sequencing Order (Linear/Interleaved)

Internally Self–Timed Write Cycle

Byte Write and Global Write Control

Single–Cycle Deselect

Sleep Mode (ZZ)

100–Pin TQFP Package

and

MCM63P733A

Order this document

by MCM63P733A/D

CASE 983A–01

TQ PACKAGE

MCM63P733A

TQFP

Related parts for MCM63P733ATQ133

MCM63P733ATQ133 Summary of contents

Page 1

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Advance Information 128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM63P733A is a 4M–bit synchronous fast static RAM designed to pro- vide a burstable, high performance, secondary cache for the PowerPC other high ...

Page 2

LBO ADV K ADSC ADSP SA SA1 SA0 SGW SW SBa SBb SBc SBd SE1 SE2 SE3 G MCM63P733A 2 FUNCTIONAL BLOCK DIAGRAM BURST COUNTER K2 CLR 2 17 ADDRESS REGISTER WRITE REGISTER a WRITE REGISTER b WRITE REGISTER c ...

Page 3

NC 1 DQc 2 DQc 3 V DDQ DQc 6 DQc 7 DQc 8 DQc DDQ DQc DQc DQd DQd V DDQ V SS DQd DQd ...

Page 4

PIN DESCRIPTIONS Pin Locations (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79 12, 13 (d) 18, 19, ...

Page 5

TRUTH TABLE (See Notes 1 through 5) Address Next Cycle Used SE1 Deselect None 1 Deselect None 0 Deselect None 0 Deselect None X Deselect None X Begin Read External 0 Begin Read External 0 Continue Read Next X Continue ...

Page 6

INTERLEAVED BURST ADDRESS TABLE 1st Address (External) 2nd Address (Internal X00 X01 X10 X11 WRITE TRUTH TABLE Cycle Type Read Read Write Byte a ...

Page 7

DC OPERATING CONDITIONS AND CHARACTERISTICS ( 3 10%, – 5 Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS: 2.5 V I/O Supply Parameter Supply Voltage I/O Supply Voltage Input Low Voltage ...

Page 8

SUPPLY CURRENTS Parameter Input Leakage Current ( Output Leakage Current ( DDQ ) AC Supply Current (Device Selected, MCM63P733A–133 All Outputs Open, Freq = Max) MCM63P733A–117 Includes V DD Only ...

Page 9

AC OPERATING CONDITIONS AND CHARACTERISTICS ( 3 10%, – 5 Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . ...

Page 10

OUTPUT Figure 3. Lumped Capacitive Load and Typical Derating Curve MCM63P733A 10 OUTPUT Ω Ω 1.25 V Figure 2. AC Test Load 2400 2200 2000 1800 1600 1400 1200 C L 1000 ...

Page 11

PULL–UP VOLTAGE (V) I (mA) MIN I (mA) MAX – 0.5 – – 38 0.8 – 38 1.25 – 30 1.5 – 27 2.3 0 2.7 0 2.9 0 PULL–UP VOLTAGE (V) I (mA) MIN I (mA) MAX ...

Page 12

MCM63P733A 12 MOTOROLA FAST SRAM ...

Page 13

É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É ...

Page 14

... DQ Q(A) READS Figure 5. Example Configuration as Non–Burst Synchronous SRAM Motorola Memory Prefix Part Number Full Part Numbers — MCM63P733ATQ133 MCM63P733ATQ133R MCM63P733A 14 APPLICATION INFORMATION may continue to run without impacting the RAMs sleep cur- rent ( All inputs are allowed to toggle — the RAM will not be selected and perform any reads or writes ...

Page 15

H A– –A– 100 1 D1 TIPS 0.20 (0.008) C A–B A –H– –C– SEATING PLANE 0.05 (0.002 VIEW AB MOTOROLA FAST SRAM PACKAGE DIMENSIONS TQ ...

Page 16

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of ...

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