MCM69P536CTQ5 Freescale Semiconductor, Inc, MCM69P536CTQ5 Datasheet

MCM69P536CTQ5

Manufacturer Part Number

MCM69P536CTQ5

Description

Manufacturer

Freescale Semiconductor, Inc

Datasheet

1.MCM69P536CTQ5.pdf (12 pages)

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

32K x 36 Bit Pipelined BurstRAM

Synchronous Fast Static RAM

vide a burstable, high performance, secondary cache for the 68K Family,

PowerPC , 486, i960 , and Pentium microprocessors. It is organized as 32K

words of 36 bits each. This device integrates input registers, an output register,

a 2–bit address counter, and high speed SRAM onto a single monolithic circuit

for reduced parts count in cache data RAM applications. Synchronous design

allows precise cycle control with the use of an external clock (K). BiCMOS cir-

cuitry reduces the overall power consumption of the integrated functions for

greater reliability.

enable (G) and Linear Burst Order (LBO) are clock (K) controlled through

positive–edge–triggered noninverting registers.

addresses can be generated internally by the MCM69P536C (burst sequence

operates in linear or interleaved mode dependent upon the state of LBO) and

controlled by the burst address advance (ADV) input pin.

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

synchronous write enable SW are provided to allow writes to either individual

bytes or to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa

controls DQa, SBb controls DQb, etc. Individual bytes are written if the selected

byte writes SBx are asserted with SW. All bytes are written if either SGW is

asserted or if all SBx and SW are asserted.

edge–triggered output register and then released to the output buffers at the next

rising edge of clock (K).

outputs are LVTTL compatible.

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

i960 and Pentium are trademarks of Intel Corp.

REV 3

2/9/98

MOTOROLA FAST SRAM

Motorola, Inc. 1998

The MCM69P536C is a 1M–bit synchronous fast static RAM designed to pro-

Addresses (SA), data inputs (DQx), and all control signals except output

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

Write cycles are internally self–timed and are initiated by the rising edge of the

Synchronous byte write (SBx), synchronous global write (SGW), and

For read cycles, pipelined SRAMs output data is temporarily stored by an

The MCM69P536C operates from a 3.3 V power supply and all inputs and

MCM69P536C–4 = 4 ns Access / 7.5 ns Cycle

MCM69P536C–4.5 = 4.5 ns Access / 8 ns Cycle

MCM69P536C–5 = 5 ns Access / 10 ns Cycle

MCM69P536C–6 = 6 ns Access / 12 ns Cycle

MCM69P536C–7 = 7 ns Access / 13.3 ns Cycle

Single 3.3 V + 10%, – 5% Power Supply

ADSP, ADSC, and ADV Burst Control Pins

Selectable Burst Sequencing Order (Linear/Interleaved)

Internally Self–Timed Write Cycle

Byte Write and Global Write Control

5 V Tolerant on all Pins (Inputs and I/Os)

100–Pin TQFP Package

MCM69P536C

Order this document

by MCM69P536C/D

CASE 983A–01

TQ PACKAGE

MCM69P536C

TQFP

Related parts for MCM69P536CTQ5

MCM69P536CTQ5 Summary of contents

Page 1

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM69P536C is a 1M–bit synchronous fast static RAM designed to pro- vide a burstable, high performance, secondary cache for the 68K Family, PowerPC , 486, ...

Page 2

LBO ADV K ADSC ADSP SA SA1 SA0 SGW SW SBa SBb SBc SBd SE1 SE2 SE3 G MCM69P536C 2 FUNCTIONAL BLOCK DIAGRAM BURST COUNTER K2 CLR 2 15 ADDRESS REGISTER WRITE REGISTER a WRITE REGISTER b WRITE REGISTER c ...

Page 3

DQc 1 DQc 2 DQc DQc 6 DQc 7 DQc 8 DQc DQc 12 DQc ...

Page 4

PIN DESCRIPTIONS Pin Locations (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79 12, 13 (d) 18, 19, ...

Page 5

TRUTH TABLE (See Notes 1 through 4) Address Next Cycle Used Deselect None Deselect None Deselect None Deselect None Deselect None Begin Read External Begin Read External Continue Read Next Continue Read Next Continue Read Next Continue Read Next Suspend ...

Page 6

ABSOLUTE MAXIMUM RATINGS (See Note 1) Rating Power Supply Voltage Voltage Relative for Any Pin Except V DD Output Current (per I/O) Package Power Dissipation (See Note 2) Temperature Under Bias Storage Temperature NOTES: 1. Permanent device ...

Page 7

DC OPERATING CONDITIONS AND CHARACTERISTICS ( 3 10%, – 5 Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Input Low Voltage Input High Voltage * V IL – ...

Page 8

AC OPERATING CONDITIONS AND CHARACTERISTICS ( 3 10%, – 5 Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . ...

Page 9

MOTOROLA FAST SRAM MCM69P536C 9 ...

Page 10

The MCM69P536C BurstRAM is a high speed synchro- nous SRAM that is intended for use primarily in secondary or level two (L2) cache memory applications. L2 caches are found in a variety of classes of computers — from the desk- ...

Page 11

... ORDERING INFORMATION (Order by Full Part Number) MCM 69P536C Blank = Trays Tape and Reel Speed ( ns, 4.5 = 4 ns) Package (TQ = TQFP) MCM69P536CTQ4R MCM69P536CTQ4.5 MCM69P536CTQ4.5R MCM69P536CTQ5 MCM69P536CTQ5R MCM69P536CTQ6 MCM69P536CTQ6R MCM69P536CTQ7 MCM69P536CTQ7R are registered trademarks of Motorola, Inc. Motorola, Inc Equal MCM69P536C 11 ...

Page 12

H A– –A– 100 1 D1 TIPS 0.20 (0.008) C A–B A –H– –C– SEATING PLANE 0.05 (0.002 VIEW AB How to reach us: USA / ...

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