DSP56852VF120 Freescale Semiconductor, Inc, DSP56852VF120 Datasheet
DSP56852VF120
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DSP56852VF120 Summary of contents
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Data Sheet Technical Data 56800E 16-bit Digital Signal Controllers DSP56852 Rev. 8 01/2007 freescale.com ...
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DSP56852 General Description • 120 MIPS at 120MHz • 16-bit Program SRAM • 16-bit Data SRAM • 16-bit Boot ROM • 21 External Memory Address lines, 16 data lines and four chip selects • ...
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Part 1 Overview 1.1 56852 Features 1.1.1 Core • Efficient 16-bit engine with dual Harvard architecture • 120 Million Instructions Per Second (MIPS) at 120MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) • • Four (4) 36-bit accumulators ...
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Energy Information • Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs • Wait and Stop modes available 1.2 56852 Description The 56852 is a member of the 56800E core-based family of controllers. It combines single chip, ...
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Product Documentation The four documents listed in Table 1-1 the 56852. Documentation is available from local Freescale distributors, Freescale semiconductor sales offices, Freescale Literature Distribution Centers, or online at www.freescale.com. Table 1-1 DSP56852 Chip Documentation Topic DSP56800E Detailed description ...
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Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56852 are organized into functional groups, as shown in as illustrated in Figure 2-1. In signals present. Table 2-1 Functional Group Pin Allocations Power ( ...
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Logic Power VDDIO I/O VSSIO Power Analog VDDA 1 Power VSSA A0–16 A17(TI/O) A18(TI/O) Address Bus A19(CS3) CLKO(A20) GPIOA0(CS0) GPIOA1(CS1) Chip Select GPIOA2(CS2) D0-D12 Data D13-D15/MODEA-C Bus Bus Control Figure 2-1 56852 Signals Identified by Functional Group 8 1 VDD ...
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Part 3 Signals and Package Information All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are enabled by default. Exceptions: 1. When a pin has GPIO functionality, the pull-up may be disabled under software ...
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Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued) Pin No. Signal Name A10 H4 A11 ...
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Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued) Pin No. Signal Name D3 CS1 GPIOA1 Input/Output C3 CS2 GPIOA2 Input/Output G7 D0 Input/Output ...
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Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued) Pin No. Signal Name RXD GPIOE0 Input/Output D4 TXD GPIOE1 Input/Output B2 GPIOC0 Input/Output STXD A2 GPIOC1 Input/Output SRXD A3 SCLK Input/Output GPIOC2 Input/Output STCK ...
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Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued) Pin No. Signal Name C4 MISO Input/Output GPIOC4 Input/Output SRCK Input/Output C5 MOSI GPIOC5 Input/Output SRFS Input/Output A1 IRQA C2 IRQB A6 EXTAL A7 XTAL Input/Output Freescale Semiconductor ...
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Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued) Pin No. Signal Name D5 RESET C6 TCK B7 TDI A8 TDO C7 TMS D6 TRST B8 DE Input/Output 14 Type Input Reset (RESET)—This input is a direct ...
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Part 4 Specifications 4.1 General Characteristics The 56852 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to withstand ...
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Table 4-1 Absolute Maximum Ratings Characteristic Supply voltage, core Supply voltage, IO Supply voltage, analog Digital input voltages Analog input voltages (XTAL, EXTAL) Current drain per pin excluding SSA, DDIO SSIO Junction temperature Storage temperature ...
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Characteristic Thermal resistance junction-to-ambient (estimated) I/O pin power dissipation Power dissipation Maximum allowed See Section 6.1 for more detail Junction Temperature TA = Ambient Temperature 4.2 DC Electrical Characteristics Table 4-4 DC Electrical Characteristics ...
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Table 4-4 DC Electrical Characteristics (Continued) Operating Conditions SSIO SSA Characteristic V supply current (Core logic, memories, peripherals Run 2 Deep Stop 3 Light Stop V supply current (I/O circuity) DDIO 5 ...
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Figure 4-1 Maximum Run I 4.3 Supply Voltage Sequencing and Separation Cautions Figure 4-2 shows two situations to avoid in sequencing the V 3.3V 1. Note rising before V , ...
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V should not be allowed to rise early (1). This is usually avoided by running the regulator for the V DD supply (1.8V) from the voltage generated by the 3.3V V rising faster than V . DDIO V should not ...
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Figure 4-5 shows the definitions of the following signal states: • Active state, when a bus or signal is driven, and enters a low impedance state • Tri-stated, when a bus or signal is placed in a high impedance state ...
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High Speed External Clock Source (> 4MHz) The recommended method of connecting an external clock is given in source is connected to XTAL and the EXTAL pin is held at ground (recommended), V The TOD_SEL bit in CGM must ...
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External 90% 50% Clock 10 Note: The midpoint Operating Conditions SSIO SSA Characteristic External reference crystal frequency for the PLL PLL output frequency 2 PLL stabilization time ...
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Some of the parameters contain two sets of numbers. These parameters have two different paths and clock edges that must be considered. Check both sets of numbers and use the smaller result. The appropriate entry may change if the operating ...
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Table 4-7 External Memory Interface Timing Operating Conditions SSIO SSA Characteristic Address Valid to WR Asserted WR Width Asserted to WR Deasserted Data Out Valid to WR Asserted Valid Data Out Hold Time after ...
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Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 4-8 Reset, Stop, Wait, Mode Select, and Interrupt Timing Operating Conditions SSIO SSA Characteristic RESET Assertion to Address, Data and Control Signals High Impedance ...
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RESET t RAZ A0–A20, D0–D15 CS, RD, WR Figure 4-11 Asynchronous Reset Timing IRQA IRQB Figure 4-12 External Interrupt Timing (Negative-Edge-Sensitive) A0–A20, CS IDM IRQA, IRQB Purpose I/O Pin t IG IRQA, IRQB Figure 4-13 External ...
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IRQA, IRQB A0–A20, CS, RD, WR Figure 4-14 Interrupt from Wait State Timing t IW IRQA A0–A20, CS, RD, WR Figure 4-15 Recovery from Stop State Using Asynchronous Interrupt Timing RESET 28 t IRI RSTO Figure 4-16 ...
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Serial Peripheral Interface (SPI) Timing Operating Conditions SSIO SSA Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCLK) high time Master Slave Clock (SCLK) low ...
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SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output MISO (Input) MOSI (Output) Figure 4-17 SPI Master Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) ...
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SS (Input) SCLK (CPOL = 0) (Input) t SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 4-19 SPI Slave Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) t ...
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Quad Timer Timing Operating Conditions SSIO SSA Characteristic Timer input period Timer input high/low period Timer output period Timer output high/low period 1. In the formulas listed clock cycle. For f ...
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Synchronous Serial Interface (SSI) Timing Table 4-11 SSI Master Mode Operating Conditions SSIO SSA Parameter STCK frequency 3 STCK period STCK high time STCK low time Output clock rise/fall time Delay from STCK ...
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Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part. 3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR) and a ...
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Table 4-12 SSI Slave Mode Operating Conditions SSIO SSA Parameter STCK frequency 3 STCK period STCK high time STCK low time Output clock rise/fall time Delay from STCK high to STFS (bl) high - ...
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Table 4-12 SSI Slave Mode Operating Conditions SSIO SSA Parameter SRXD Hold time after SRCK low - Slave Synchronous Operation (in addition to standard external clock parameters) SRXD Setup time before STCK low - ...
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Serial Communication Interface (SCI) Timing Operating Conditions SSIO SSA Characteristic 1 Baud Rate 2 RXD Pulse Width 3 TXD Pulse Width the frequency of operation of the system clock in ...
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JTAG Timing Operating Conditions SSIO SSA Characteristic 2 TCK frequency of operation TCK cycle time TCK clock pulse width TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO ...
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TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) TDO (Output) Figure 4-28 Test Access Port Timing Diagram TRST (Input) DE Figure 4-30 Enhanced OnCE—Debug Event Freescale Semiconductor t DS Input Data Valid ...
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GPIO Timing Operating Conditions SSIO SSA Characteristic GPIO input period GPIO input high/low period GPIO output period GPIO output high/low period GPIO Inputs GPIO Outputs 40 Table 4-15 GPIO Timing = 0V, V ...
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Part 5 56852 Packaging & Pinout Information This section contains package and pin-out information for the 81-pin MAPBGA configuration of the 56852 D15 TD0 XTAL V DE TDI DDIO D14 TMS V SSIO D13 D11 D12 V ...
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Table 5-1 56852 Pin Identification by Pin Number Pin No. Signal Name Pin No A10 H4 A11 G4 A12 ...
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Part 6 Design Considerations 6.1 Thermal Design Considerations An estimation of the chip junction temperature, T Equation Where ambient temperature ° package junction-to-ambient thermal resistance °C/W θ ...
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As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection ...
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Take special care to minimize noise levels on the V • When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-up device. • Designs that utilize the TRST pin for JTAG ...
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... DSP56852 1.8–3.3 V Mold Array Process Ball Grid Array (MAPBGA) DSP56852 1.8–3.3 V Mold Array Process Ball Grid Array (MAPBGA) *This package is RoHS compliant. 46 Pin Package Type Count 81 81 56852 Technical Data, Rev. 8 Frequency Order Number (MHz) 120 DSP56852VF120 120 DSP56852VFE * Freescale Semiconductor ...
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Freescale Semiconductor 56852 Technical Data, Rev. 8 Electrical Design Considerations 47 ...
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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005. All rights reserved. DSP56852 Rev. 8 ...