AD1879JD Analog Devices, AD1879JD Datasheet

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AD1879JD

Manufacturer Part Number
AD1879JD
Description
0-13.2V; high performance 16/18-bit stereo ADC. For digital tape recorders, professional, DCC and DAT, A/V digital amplifiers, CD-R, sound reinforcement
Manufacturer
Analog Devices
Datasheet

Specifications of AD1879JD

Dc
0027

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PRODUCT OVERVIEW
The AD1879 is a two-channel, 18-bit oversampling ADC based
on
cations. The AD1878 is identical to the 18-bit AD1879 except
that it outputs 16-bit data words. Statements in this data sheet
should be read as applying to both parts unless otherwise noted.
Each input channel of these ADCs is fully differential. Each
data conversion channel consists of a fifth order one-bit noise
shaping modulator and a digital decimation filter. An on-chip
voltage reference provides a voltage source to both channels sta-
ble over temperature and time. Digital output data from both
channels is time-multiplexed to a single, flexible serial interface.
The AD1878/AD1879 accepts a 256
Input signals are sampled at 64
eliminating external sample-and-hold amplifiers and minimizing
the requirements for antialias filtering at the input. With simpli-
fied antialiasing, linear phase can be preserved across the passband.
The AD1878/AD1879’s proprietary fifth-order differential
switched-capacitor modulator architecture shapes the one-bit
comparator’s quantization noise out of the audio passband. The
high order of the modulator randomizes the modulator output,
reducing idle tones in the AD1878/AD1879 to very low levels.
The AD1878/AD1879’s differential architecture provides in-
creased dynamic range and excellent common-mode rejection
characteristics. Because its modulator is single-bit, AD1878/
AD1879 is inherently monotonic and has no mechanism for
producing differential linearity errors.
The digital decimation filters are single-stage, 4095-tap finite
impulse response filters for filtering the modulator’s high fre-
quency quantization noise and reducing the 64
output data rate to a F
*
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Protected by U.S. Patent Numbers 5055843, 5126653, and others pending.
FEATURES
Fully Differential Dual Channel Analog Inputs
103 dB Signal-to-Noise (AD1879 typ)
–98 dB THD+N (AD1879 typ)
0.001 dB Passband Ripple and 115 dB Stopband
Fifth-Order, 64 Times Oversampling
Single Stage, Linear Phase Decimator
256
APPLICATIONS
Digital Tape Recorders
A/V Digital Amplifiers
CD-R
Sound Reinforcement
Attenuation
Professional, DCC, and DAT
technology and intended primarily for digital audio appli-
F
S
Input Clock
S
word rate. They provide linear
F
S
on switched-capacitors,
F
S
input master clock.
Modulator
F
S
single-bit
phase and a narrow transition band that permits the digitization
of 20 kHz signals while preventing aliasing into the passband
even when using a 44.1 kHz sampling frequency. Passband
ripple is less the 0.001 dB, and stopband attenuation exceeds
115 dB.
The flexible serial output port produces data in twos-complement,
MSB-first format. Input and output signals are to TTL and
CMOS-compatible logic levels. The port is configured by pin
selections. The AD1878/AD1879 can operate in either master
or slave mode. Each 16-/18-bit output word of a stereo pair can
be formatted within a 32-bit field as either right-justified, I
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
compatible, or at user-selected positions. The output can also be
truncated to 16-bits by formatting into a 16-bit field.
The AD1878/AD1879 consists of two integrated circuits in a
single ceramic 28-pin DIP package. The modulators and refer-
ence are fabricated in a BiCMOS process; the decimator and
output port, in a 1.0 m CMOS process. Separating these func-
tions reduces digital crosstalk to the analog circuitry. Analog and
digital supply connections are separated to further isolate the
analog circuitry from the digital supplies.
The AD1878/AD1879 operates from 5 V power supplies over
the temperature range of –25 C to +70 C.
AV
AV
VINR+
LRCK
DGND
AGND
VINR–
REFR
DV
64/32
APD
BCK
SS
SS
NC
S0
DD
1
2
10
12
13
14
11
1
2
3
4
5
6
7
8
9
16-/18-Bit
FUNCTIONAL BLOCK DIAGRAM
FIR DECIMATION
SINGLE-STAGE,
D
A
C
FILTER
4k-TAP
AD1878/AD1879*
SERIAL OUTPUT
REFERENCE
D
A
C
VOLTAGE
High Performance
INTERFACE
DIGITAL
ANALOG
CHIP
CHIP
D
A
C
FIR DECIMATION
SINGLE-STAGE,
FILTER
4k-TAP
Stereo ADCs
D
A
C
Fax: 617/326-8703
22
28
26
25
24
23
21
20
17
16
15
27
19
18
RESET
DV
WCK
DATA
DGND
AV
REFL
CLOCK
S1
AV
AV
AGND
VINL–
VINL+
2
DD
SS
DD
DD
S-
1
2
1

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AD1879JD Summary of contents

Page 1

... Protected by U.S. Patent Numbers 5055843, 5126653, and others pending. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices ...

Page 2

AD1878/AD1879–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages 5 Ambient Temperature 25 Input Clock (F ) 12.288 CLOCK Input Signal 974 –0.5 All minimums and maximums tested except as noted. ANALOG PERFORMANCE AD1879 Resolution AD1878 Resolution Clock Input Frequency Range ...

Page 3

DIGITAL INPUTS 360 1 DIGITAL TIMING ...

Page 4

... S Specifications subject to change without notice. Model AD1878JD AD1879JD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1878/AD1879 features proprietary ESD protection circuitry, permanent dam- age may occur on devices subjected to high energy electrostatic discharges ...

Page 5

DEFINITIONS Dynamic Range The ratio of a full-scale output signal to the integrated output noise in the passband (0 kHz to 20 kHz), expressed in decibels (dB). Dynamic range is measured with a –60 dB input signal and is equal ...

Page 6

... Through careful design, this transfer function can be specified to high-pass filter the quantization noise out of the audio band into higher frequency regions. See Figure 27. The Analog Devices’ AD1878/AD1879 also incorporates feedback resonators from the third integrator’s output to the second integrator’s input and from the fifth integrator’ ...

Page 7

Sample Delay The sample delay or “group delay” of the AD1878/AD1879 is dominated by the processing time of the digital decimation fil- ter. FIR filters convolve a vector representing time samples of the input with an equal-sized vector of coefficients. ...

Page 8

... NPO namic range and 98 dB S/(THD+N) in your system. Schematics of our AD1878/AD1879 Evaluation Board, which implements REFL these recommendations, are available from Analog Devices. .0047 µF 15 NPO The principles and their rationales are listed below in descend- 200 ing order of importance ...

Page 9

This input bypassing mini- mizes the RF transmission and reception capability of the AD1878/AD1879 inputs. • For best performance, do not use ...

Page 10

AD1878/AD1879 In the “slave modes,” the bit clock (BCK), the word clock (WCK), and the left/right clock (LRCK) are user-supplied in- puts. Note that, for performance reasons, the AD1878/AD1879 does not support asynchronous operation; these clocks must be externally derived ...

Page 11

BCK I/O WCK INPUT LRCK I/O PREVIOUS DATA AD1878 LSB ZEROS DATA OUTPUT Figure 10. AD1878 64-Bit Frame Output Timing with WCK as Input: WCK Held LO Until 16th BCK (Master Mode or Slave ...

Page 12

AD1878/AD1879 Also available with the AD1878/AD1879 is a 32-bit frame mode where the 1879’s 18-bit output is truncated to 16-bit words and for both parts the output packed “tightly” into two 16-bit fields in the 32-bit frame as shown in ...

Page 13

CLOCK INPUT t DLYCK BCK OUTPUT (64• PREVIOUS NEW LRCK OUTPUT WCK INPUT DATA OUTPUT Figure 16. AD1878/AD1879 Master Mode Clock Timing: WCK Input B B+1 B+2 L CLOCK INPUT t HLD t SET t BCK INPUT (64•F ...

Page 14

AD1878/AD1879 DATA SRD AD1879 BCK SCK WCK SC2 LRCK SC1 Figure 19. AD1879 to DSP56001 Interface To configure the DSP56001 for proper operation, the CRA register must he programmed for a 24-bit receive data register (RX). The CRB register must ...

Page 15

FREQUENCY – Hz Figure 23. AD1879 S/(THD+N)—10 kHz Tone at –10 dBFS (4k-Point FFT) 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 ...

Page 16

AD1878/AD1879 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 21.5 22.0 22.5 23.0 23.5 24.0 24.5 FREQUENCY – kHz Figure 29. AD1878/AD1879 Digital Filter Signal Transfer Function— Transition Band: 21.5 kHz to 26.5 kHz ...

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