ad1879 Analog Devices, Inc., ad1879 Datasheet
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ad1879
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ad1879 Summary of contents
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... The AD1879 is a two-channel, 18-bit oversampling ADC based on technology and intended primarily for digital audio appli- cations. The AD1878 is identical to the 18-bit AD1879 except that it outputs 16-bit data words. Statements in this data sheet should be read as applying to both parts unless otherwise noted. ...
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... CLOCK Modulator Sample Rate (F /4) CLOCK Output Word Rate ( /256) S CLOCK AD1879 Dynamic Range (0 kHz to 20 kHz, –60 dB input) Stereo Mode (No A-Weight Filter) 1 Mono Mode (No A-Weight Filter) Stereo Mode (with A-Weight Filter) 2 AD1879 Trimmed Signal to (Noise + Distortion) Full Scale –20 dB ...
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... Min Max 0 4.0 0.5 Min 0. Min 4.75 –5.25 Min Typ +25 –25 –60 –3– AD1878/AD1879 Units Typ Max Units 100 CLOCK Periods 32 BCK Periods 16 BCK Periods BCK Periods CLOCK Periods ns ns ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1878/AD1879 features proprietary ESD protection circuitry, permanent dam- age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... THEORY OF OPERATION Modulator Noise-Shaping The stereo, differential analog modulators of the AD1878/ AD1879 employ a proprietary feedforward and feedback archi- tecture that passes input signals in the audio band with a unity transfer function yet simultaneously shape the quantization noise generated by the one-bit comparator out of the audio band ...
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... The human ear operates effectively like a spec- trum analyzer and can be sensitive to tones below the integrated noise floor, depending on frequency and level. The AD1878/ AD1879 suppresses idle tones typically 110 dB or better below full-scale input levels. Previously it was thought that higher-order modulators could not be designed to be globally stable. However, the AD1878/ AD1879’ ...
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... Sample Delay The sample delay or “group delay” of the AD1878/AD1879 is dominated by the processing time of the digital decimation fil- ter. FIR filters convolve a vector representing time samples of the input with an equal-sized vector of coefficients. After each convolution, the input vector is updated by adding a new sample at one end of the “ ...
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... SS Figure 4. AD1878/AD1879 Recommended Bypassing and Oscillator Circuits • The digital bypassing of the AD1878/AD1879 is the most critical item on the board layout. There are two pairs of digi- tal supply pins of the part, each pair on opposite sides (Pins 5 and 6 and Pins 22 and 23). The user should tie a bypass ca- pacitor set (0 ...
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... AD1879 with a mono input. The minus (–) output from the in- put buffer is sent to both right and left minus AD1879 inputs; the plus (+) output from the input buffer is sent to both right and left plus AD1879 inputs. A stereo implementation would require using two AD1879s and using the full recommended in- put structure shown above in Figure 2 ...
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... AD1878 MSB DATA OUTPUT Figure 9. AD1878/AD1879 64-Bit Frame Output Timing with WCK as Input: WCK Transitions HI Before 16th BCK (AD1878)/14th BCK (AD1879) (Master Mode or Slave Mode) options are illustrated in Figures 9, 10, 11, and 12. For all op- tions, the first occurrence in a 32-bit field when the word clock (WCK bit clock (BCK) falling edge will cause the beginning of data transmission ...
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... BCK I/O WCK INPUT LRCK I/O PREVIOUS DATA LEFT DATA AD1879 ZEROS LSB MSB DATA OUTPUT Figure 11. AD1879 64-Bit Frame Output Timing with WCK as Input: WCK Held LO Until 14th BCK (Master Mode or Slave Mode BCK I/O WCK INPUT LRCK I/O LEFT DATA AD1879 ...
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... For master modes with word clock (WCK) output, bit clock (BCK), left/right clock (LRCK), and word clock (WCK) will be CLOCK INPUT RESET LRCK OUTPUT BCK OUTPUT Figure 14. AD1878/AD1879 RESET Clock Timing for Synchronizing Master Mode WCK Output CLOCK INPUT t DLYCK BCK OUTPUT (64• LRCK & ...
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... Synchronizing Multiple AD1878/AD1879s Multiple AD1878/AD1879s can be synchronized either by making all AD1878/AD1879s serial port slaves or by making one AD1879 the serial port master and all other AD1879s slaves. These two options are illustrated in Figure 18 third alternative possible to synchronize multiple mas- ters all in Master Mode— ...
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... This data is then transferred to the RX register. The 16-/18-bit word from the AD1879 will be located in Bits 8 through 23/21 of the RX register. Bits 0 through 7 will be zero-filled. The user may poll Bit 7 (RDF) of the SSI status register (SSISR) to detect when the data has been transferred to RX ...
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... FREQUENCY – Hz Figure 23. AD1879 S/(THD+N)—10 kHz Tone at –10 dBFS (4k-Point FFT) 1.0 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 –120 –100 –80 –60 AMPLITUDE – dBFS Figure 24. AD1879 Linearity Test—10 kHz Tone Fade to Noise – ...
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... FREQUENCY – kHz Figure 29. AD1878/AD1879 Digital Filter Signal Transfer Function— Transition Band: 21.5 kHz to 26.5 kHz PIN 1 0.225 (5.72) MAX 0.200 (5.08) 0.125 (3.18) 1.012 1.011 1.010 1.009 1.008 1.007 1.006 1.005 1.004 1.003 1.002 1 ...