74HC4024 NXP Semiconductors, 74HC4024 Datasheet

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74HC4024

Manufacturer Part Number
74HC4024
Description
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
2. Features
3. Applications
The 74HC4024 is a high-speed Si-gate CMOS device and is pin compatible with the 4024
of the 4000B series. The 74HC4024 is specified in compliance with JEDEC
standard no. 7A.
The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to
Q6).
The counter advances on the HIGH-to-LOW transition of CP.
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the
state of CP.
Each counter stage is a static toggle flip-flop.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
74HC4024
7-stage binary ripple counter
Rev. 03 — 12 November 2004
Low-power dissipation
Complies with JEDEC standard no. 7A
ESD protection:
Multiple package options
Specified from 40 C to +80 C and from 40 C to +125 C.
Frequency dividing circuits
Time delay circuits.
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Product data sheet

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74HC4024 Summary of contents

Page 1

... The 74HC4024 is a high-speed Si-gate CMOS device and is pin compatible with the 4024 of the 4000B series. The 74HC4024 is specified in compliance with JEDEC standard no. 7A. The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). ...

Page 2

... Conditions Min Typ pF pF 3.5 [ GND W where: o © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 74HC4024 Max Unit - ns - MHz - Version SOT27-1 SOT108-1 SOT337-1 SOT402 ...

Page 3

... 001aab908 Rev. 03 — 12 November 2004 74HC4024 7-stage binary ripple counter 001aab906 Fig 2. Logic symbol CTR7 001aab907 ...

Page 4

... V) 8 not connected 9 parallel output 2 10 not connected 11 parallel output 1 12 parallel output 0 13 not connected 14 positive supply voltage Rev. 03 — 12 November 2004 74HC4024 7-stage binary ripple counter n. 4024 n. n.c. 001aab905 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...

Page 5

... current V or GND current CC storage temperature power dissipation DIP14 package SO14, SSOP14 and TSSOP14 packages derates linearly with 12 mW/K. tot derates linearly with 8 mW/K. tot Rev. 03 — 12 November 2004 74HC4024 7-stage binary ripple counter Output change count Min 0.5 & ...

Page 6

... 5 GND 6 GND Rev. 03 — 12 November 2004 74HC4024 7-stage binary ripple counter Min Typ 2 Min Typ 1.5 1.2 3.15 2.4 4.2 3.2 - 0.8 - 2.1 - 2.8 1.9 2.0 4.4 4.5 5.9 6.0 3.98 4.32 5.48 5.81 ...

Page 7

... 5 GND 6 GND Rev. 03 — 12 November 2004 74HC4024 7-stage binary ripple counter Min Typ - - - - - - 1.9 - 4.4 - 5.9 - 3. ...

Page 8

... Figure see Figure GND Rev. 03 — 12 November 2004 74HC4024 7-stage binary ripple counter Min Typ Max - 47 175 - 200 - 23 40 ...

Page 9

... Figure see Figure see Figure Rev. 03 — 12 November 2004 74HC4024 7-stage binary ripple counter Min Typ Max Unit - - 220 100 250 ns ...

Page 10

... 6 see Figure see Figure where Rev. 03 — 12 November 2004 74HC4024 7-stage binary ripple counter Min Typ Max Unit - - 265 120 300 ns - ...

Page 11

... Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance. L Test data Input Rev. 03 — 12 November 2004 74HC4024 7-stage binary ripple counter 1/f max t rem PLH PHL TLH ...

Page 12

... 1.73 0.53 0.36 19.50 6.48 1.13 0.38 0.23 18.55 6.20 0.068 0.021 0.014 0.77 0.26 0.044 0.015 0.009 0.73 0.24 REFERENCES JEDEC JEITA MO-001 SC-501-14 Rev. 03 — 12 November 2004 74HC4024 7-stage binary ripple counter 3.60 8.25 10.0 2.54 7.62 3.05 7.80 8.3 0.14 0.32 0.39 0.1 0.3 0.12 0.31 0.33 EUROPEAN PROJECTION © ...

Page 13

... 0.49 0.25 8.75 4.0 6.2 1.27 0.36 0.19 8.55 3.8 5.8 0.019 0.0100 0.35 0.16 0.244 0.05 0.014 0.0075 0.34 0.15 0.228 REFERENCES JEDEC JEITA MS-012 Rev. 03 — 12 November 2004 74HC4024 7-stage binary ripple counter detail 1.0 0.7 1.05 0.25 0.25 0.1 0.4 0.6 0.039 0.028 0.041 0.01 0.01 0.004 ...

Page 14

... 2.5 scale (1) ( 0.38 0.20 6.4 5.4 7.9 0.65 0.25 0.09 6.0 5.2 7.6 REFERENCES JEDEC JEITA MO-150 Rev. 03 — 12 November 2004 74HC4024 7-stage binary ripple counter detail 1.03 0.9 0.13 1.25 0.2 0.63 0.7 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...

Page 15

... 2.5 scale (1) ( 0.30 0.2 5.1 4.5 6.6 0.65 0.19 0.1 4.9 4.3 6.2 REFERENCES JEDEC JEITA MO-153 Rev. 03 — 12 November 2004 74HC4024 7-stage binary ripple counter detail 0.75 0.4 1 0.2 0.13 0.1 0.50 0.3 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...

Page 16

... Product specification - 9397 750 13813 Product data sheet Data sheet status Change notice - Rev. 03 — 12 November 2004 74HC4024 7-stage binary ripple counter Doc. number Supersedes 9397 750 13813 74HC_HCT4024_CNV_2 - 74HC_HCT4024_1 - - © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...

Page 17

... Rev. 03 — 12 November 2004 74HC4024 7-stage binary ripple counter © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...

Page 18

... No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Published in The Netherlands 74HC4024 Date of release: 12 November 2004 Document number: 9397 750 13813 ...

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