MC56F8357VPY60 Freescale Semiconductor, Inc, MC56F8357VPY60 Datasheet
MC56F8357VPY60
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MC56F8357VPY60 Summary of contents
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Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8356 Rev. 13 01/2007 freescale.com ...
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Version History Rev 1.0 Initial Public Release Rev 2.0 Added Package Pins to GPIO Table in “Typical Min” values to throughout family. Updated values in Regulator Parameters Operation Timing Requirements Table 10-24, and IO Loading Coefficients at 10MHz Rev 3.0 ...
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General Description Note: Features in italics are NOT available in the 56F8156 device. • MIPS at 60MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • Access up to 1MB of off-chip ...
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Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5 1.1. 56F8356/56F8156 Features . . . . . . . . . . ...
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Part 1 Overview 1.1 56F8356/56F8156 Features 1.1.1 Core • Efficient 16-bit 56800E family controller engine with dual Harvard architecture • Million Instructions Per Second (MIPS) at 60MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) • ...
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Memory Note: Features in italics ae NOT available in the 56F8156 device. • Harvard architecture permits as many as three simultaneous accesses to program and data memory • Flash security protection feature • On-chip memory, including a low-cost, high-volume ...
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Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines) • two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional GPIO lines) — In the 56F8356, SPI1 can also ...
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Features The 56F8356 controller includes 256KB of Program Flash and 8KB of Data Flash (each programmable through the JTAG port) with 4KB of Program RAM and 16KB of Data RAM. It also supports program execution from external memory. ...
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A key application-specific feature of the 56F8156 is the inclusion of one Pulse Width Modulator (PWM) module. This module incorporates three complementary, individually programmable PWM signal output pairs and can also support six independent PWM functions to enhance motor control ...
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Architecture Block Diagram Note: Features in italics are NOT available in the 56F8156 device and are shaded in the following figures. The 56F8356/56F8156 architecture is shown in 56800E system buses communicate with internal memories, the external memory interface and ...
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JTAG / EOnCE 56800E CHIP TAP Controller TAP Linking External JTAG Port NOT available on the 56F8156 device. Note: Flash memories are encapsulated within the Flash Module(FM). Flash control is accomplished by the I/O to the FM over the ...
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CLKGEN (OSC/PLL) Timer A 4 Quadrature Decoder 0 2 Timer D Timer B 4 Quadrature Decoder NOT available on the 56F8156 device. 12 To/From IPBus Bridge SPI 1 GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF SPI0 SCI0 ...
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Name pdb_m[15:0] Program data bus for instruction word fetches or read operations. cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] Program memory ...
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Product Documentation The documents in Table 1-3 56F8356/56F8156 devices. Documentation is available from local Freescale distributors, Freescale semiconductor sales offices, http://www.freescale.com. Topic DSP56800E Detailed description of the 56800E family architecture, Reference Manual and 16-bit controller core processor and the ...
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Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8356 and 56F8156 are organized into functional groups, as detailed in Table 2-1 and as illustrated in present on a pin. Table 2-1 Functional Group Pin Allocations ...
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V Power V Power DDA_ADC V Power DDA_OSC_PLL Ground V Ground SSA_ADC OCR_DIS Other CAP Supply V 1 & Ports CLKMODE PLL EXTAL and Clock CLKO (GPIOA8 - 13) External A6 ...
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V Power V Power DDA_ADC V Power DDA_OSC_PLL Ground V Ground SSA_ADC OCR_DIS Other CAP Supply V 1 & Ports CLKMODE PLL EXTAL and Clock CLKO (GPIOA8 - 13) External A6 ...
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Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. If the “State During Reset” lists more than one state for a pin, the first state is the actual ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type OCR_DIS 79 Input Supply CAP V 2 128 CAP CAP CAP V 1 125 Input ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type A0 138 Output (GPIOA8) Input/ Output A1 10 (GPIOA9 (GPIOA10 (GPIOA11 (GPIOA12 (GPIOA13 Output ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type A8 19 Output (GPIOA0) Schmitt Input Output (GPIOA1) A10 21 (GPIOA2) A11 22 (GPIOA3) A12 23 (GPIOA4) A13 24 (GPIOA5) A14 25 ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type GPIOB0 33 Schmitt Input/ Output (A16) Output D0 59 Input/ Output (GPIOF9) Input/ Output D1 60 (GPIOF10 (GPIOF11 (GPIOF12) D4 ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type D7 28 Input/ Output (GPIOF0) Input/ Output D8 29 (GPIOF1 (GPIOF2) D10 32 (GPIOF3) D11 133 (GPIOF4) D12 134 (GPIOF5) D13 135 ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type RD 45 Output WR 44 Output PS 46 Output (CS0) (GPIOD8) Input/ Output 24 State During Signal Description Reset In reset, Read Enable — ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type DS 47 Output (CS1) (GPIOD9) Input/ Output GPIOD0 48 Input/ Output (CS2) Output GPIOD1 49 (CS3) TXD0 4 Output (GPIOE0) Input/ Output Freescale Semiconductor ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type RXD0 5 Input (GPIOE1) Input/ Output TXD1 42 Output (GPIOD6) Input/ Output RXD1 43 Input (GPIOD7) Input/ Output TCK 121 Schmitt Input TMS 122 ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type TDO 124 Output TRST 120 Schmitt Input PHASEA0 139 Schmitt Input (TA0) Schmitt Input/ Output (GPIOC4) Schmitt Input/ Output Freescale Semiconductor Preliminary State During ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type PHASEB0 140 Schmitt Input (TA1) Schmitt Input/ Output (GPIOC5) Schmitt Input/ Output INDEX0 141 Schmitt Input (TA2) Schmitt Input/ Output (GPOPC6) Schmitt Input/ Output ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type SCLK0 130 Schmitt Input/ Output (GPIOE4) Schmitt Input/ Output MOSI0 132 Input/ Output (GPIOE5) Input/ Output MISO0 131 Input/ Output (GPIOE6) Input/ Output Freescale ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type SS0 129 Input (GPIOE7) Input/ Output PHASEA1 6 Schmitt Input (TB0) Schmitt Input/ Output (SCLK1) Schmitt Input/ Output (GPIOC0) Schmitt Input/ Output 30 State ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type PHASEB1 7 Schmitt Input (TB1) Schmitt Input/ Output (MOSI1) Schmitt Input/ Output (GPIOC1) Schmitt Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type INDEX1 8 Schmitt Input (TB2) Schmitt Input/ Output (MISO1) Schmitt Input/ Output (GPIOC2) Schmitt Input/ Output HOME1 9 Schmitt Input (TB3) Schmitt Input/ Output ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type PWMA0 62 Output PWMA1 64 PWMA2 65 PWMA3 67 PWMA4 68 PWMA5 70 ISA0 113 Schmitt Input (GPIOC8) Schmitt Input/ ISA1 114 Output (GPIOC9) ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type ISB0 50 Schmitt Input (GPIOD10) Schmitt Input/ ISB1 52 Output (GPIOD11) ISB2 53 (GPIOD12) FaultB0 56 Schmitt Input FaultB1 57 FaultB2 58 FaultB3 61 ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type ANB0 104 Input ANB1 105 ANB2 106 ANB3 107 ANB4 108 Input ANB5 109 ANB6 110 ANB7 111 TEMP_SENSE 96 Output CAN_RX 127 Schmitt ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type TD0 116 Schmitt Input/ Output (GPIOE10) Schmitt Input/ TD1 117 Output (GPIOE11) IRQA 54 Schmitt Input IRQB 55 RESET 86 Schmitt Input RSTO 85 ...
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Table 2-2 Signal and Package Information for the 144-Pin LQFP (Continued) Signal Name Pin No. Type EXTBOOT 112 Schmitt Input EMI_MODE 143 Schmitt Input Freescale Semiconductor Preliminary State During Signal Description Reset Input, External Boot — This input is tied ...
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Part 3 On-Chip Clock Synthesis (OCCS) 3.1 Introduction Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design. specific OCCS ...
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The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. Crystal ...
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Resonator Frequency = 4 - 8MHz (optimized for 8MHz) 2 Terminal EXTAL XTAL R z CL1 CL2 Figure 3-3 Connecting a Ceramic Resonator Note: The OCCS_COHL bit must be set to 0 when a ceramic resonator is used. The reset ...
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This section provides memory maps for: • Program Address Space, including the Interrupt Vector Table • Data Address Space, including the EOnCE Memory and Peripheral Memory Maps On-chip memory sizes for each device are summarized in identified in the “Use ...
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Table 4-1 Chip Memory Configurations On-Chip Memory 56F8356 Data RAM 16KB Program Boot Flash 16KB 4.2 Program Map The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) control the Program memory map. At reset, these ...
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To address this situation, the EMI_MODE pin can be used to configure four GPIO pins as Address[19:16] upon reset (only one of these pins [A16] is usable in the 56F8356/56F8156). The EMI_MODE pin ...
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The priority of an interrupt can be assigned to different levels, as indicated, allowing some control over interrupt priorities. All level 3 interrupts will be serviced ...
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Table 4-5 Interrupt Vector Table Contents Vector Priority Peripheral Number Level PLL 0-2 FLEXCAN 26 0-2 FLEXCAN 27 0-2 FLEXCAN 28 0-2 FLEXCAN 29 0-2 GPIOF 30 0-2 GPIOE 31 ...
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Table 4-5 Interrupt Vector Table Contents Vector Priority Peripheral Number Level TMRD 52 0-2 TMRD 53 0-2 TMRD 54 0-2 TMRD 55 0-2 TMRC 56 0-2 TMRC 57 0-2 TMRC 58 0-2 TMRC 59 0-2 TMRB 60 0-2 TMRB 61 ...
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Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from the vector table, providing only 19 bits of address the VBA is set to ...
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Data Memory buses and is controlled separately by its own set of banked registers. The top nine words of the Program Memory Flash are treated as special memory locations. The content of these words is used to control ...
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EOnCE Memory Map Address Register Acronym X:$FF FF8A OESCR X:$FF FF8E OBCNTR X:$FF FF90 OBMSK (32 bits) X:$FF FF91 — X:$FF FF92 OBAR2 (32 bits) X:$FF FF93 — X:$FF FF94 OBAR1 (24 bits) X:$FF FF95 — X:$FF FF96 OBCR ...
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Peripheral Memory Mapped Registers On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary Data memory, except all peripheral registers should be ...
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Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued) Peripheral GPIO Port E GPIO Port F SIM Power Supervisor FM FlexCAN Table 4-10 External Memory Integration Registers Address Map Register Acronym Address Offset CSBAR 0 $0 CSBAR 1 $1 ...
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Table 4-10 External Memory Integration Registers Address Map (Continued) Register Acronym Address Offset CSOR 0 $8 CSOR 1 $9 CSOR 2 $A CSOR 3 $B CSOR 4 $C CSOR 5 $D CSOR 6 $E CSOR 7 $F CSTC 0 $10 ...
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Table 4-11 Quad Timer A Registers Address Map (Continued) Register Acronym TMRA0_SCR TMRA0_CMPLD1 TMRA0_CMPLD2 TMRA0_COMSCR TMRA1_CMP1 TMRA1_CMP2 TMRA1_CAP TMRA1_LOAD TMRA1_HOLD TMRA1_CNTR TMRA1_CTRL TMRA1_SCR TMRA1_CMPLD1 TMRA1_CMPLD2 TMRA1_COMSCR TMRA2_CMP1 TMRA2_CMP2 TMRA2_CAP TMRA2_LOAD TMRA2_HOLD TMRA2_CNTR TMRA2_CTRL TMRA2_SCR TMRA2_CMPLD1 TMRA2_CMPLD2 TMRA2_COMSCR TMRA3_CMP1 TMRA3_CMP2 TMRA3_CAP ...
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Table 4-11 Quad Timer A Registers Address Map (Continued) Register Acronym TMRA3_LOAD TMRA3_HOLD TMRA3_CNTR TMRA3_CTRL TMRA3_SCR TMRA3_CMPLD1 TMRA3_CMPLD2 TMRA3_COMSC Table 4-12 Quad Timer B Registers Address Map Quad Timer B is NOT available in the 56F8156 device Register Acronym TMRB0_CMP1 ...
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Table 4-12 Quad Timer B Registers Address Map (Continued) Quad Timer B is NOT available in the 56F8156 device Register Acronym TMRB1_SCR TMRB1_CMPLD1 TMRB1_CMPLD2 TMRB1_COMSCR TMRB2_CMP1 TMRB2_CMP2 TMRB2_CAP TMRB2_LOAD TMRB2_HOLD TMRB2_CNTR TMRB2_CTRL TMRB2_SCR TMRB2_CMPLD1 TMRB2_CMPLD2 TMRB2_COMSCR TMRB3_CMP1 TMRB3_CMP2 TMRB3_CAP TMRB3_LOAD ...
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Table 4-13 Quad Timer C Registers Address Map Register Acronym TMRC0_CMP1 TMRC0_CMP2 TMRC0_CAP TMRC0_LOAD TMRC0_HOLD TMRC0_CNTR TMRC0_CTRL TMRC0_SCR TMRC0_CMPLD1 TMRC0_CMPLD2 TMRC0_COMSCR TMRC1_CMP1 TMRC1_CMP2 TMRC1_CAP TMRC1_LOAD TMRC1_HOLD TMRC1_CNTR TMRC1_CTRL TMRC1_SCR TMRC1_CMPLD1 TMRC1_CMPLD2 TMRC1_COMSCR TMRC2_CMP1 TMRC2_CMP2 TMRC2_CAP TMRC2_LOAD TMRC2_HOLD TMRC2_CNTR TMRC2_CTRL 56 ...
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Table 4-13 Quad Timer C Registers Address Map (Continued) Register Acronym TMRC2_SCR TMRC2_CMPLD1 TMRC2_CMPLD2 TMRC2_COMSCR TMRC3_CMP1 TMRC3_CMP2 TMRC3_CAP TMRC3_LOAD TMRC3_HOLD TMRC3_CNTR TMRC3_CTRL TMRC3_SCR TMRC3_CMPLD1 TMRC3_CMPLD2 TMRC3_COMSCR Table 4-14 Quad Timer D Registers Address Map Quad Timer D is NOT available ...
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Table 4-14 Quad Timer D Registers Address Map (Continued) Quad Timer D is NOT available in the 56F8156 device Register Acronym TMRD1_CMP1 TMRD1_CMP2 TMRD1_CAP TMRD1_LOAD TMRD1_HOLD TMRD1_CNTR TMRD1_CTRL TMRD1_SCR TMRD1_CMPLD1 TMRD1_CMPLD2 TMRD1_COMSCR TMRD2_CMP1 TMRD2_CMP2 TMRD2_CAP TMRD2_LOAD TMRD2_HOLD TMRD2_CNTR TMRD2_CTRL TMRD2_SCR ...
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Table 4-14 Quad Timer D Registers Address Map (Continued) Quad Timer D is NOT available in the 56F8156 device Register Acronym TMRD3_CTRL TMRD3_SCR TMRD3_CMPLD1 TMRD3_CMPLD2 TMRD3_COMSCR Table 4-15 Pulse Width Modulator A Registers Address Map PWMA is NOT available in ...
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Table 4-16 Pulse Width Modulator B Registers Address Map Register Acronym PWMB_PMCTL PWMB_PMFCTL PWMB_PMFSA PWMB_PMOUT PWMB_PMCNT PWMB_PWMCM PWMB_PWMVAL0 PWMB_PWMVAL1 PWMB_PWMVAL2 PWMB_PWMVAL3 PWMB_PWMVAL4 PWMB_PWMVAL5 PWMB_PMDEADTM PWMB_PMDISMAP1 PWMB_PMDISMAP2 PWMB_PMCFG PWMB_PMCCR PWMB_PMPORT PWMB_PMICCR Table 4-17 Quadrature Decoder 0 Registers Address Map Register Acronym ...
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Table 4-17 Quadrature Decoder 0 Registers Address Map (Continued) Register Acronym DEC0_POSDH DEC0_REV DEC0_REVH DEC0_UPOS DEC0_LPOS DEC0_UPOSH DEC0_LPOSH DEC0_UIR DEC0_LIR DEC0_IMR Table 4-18 Quadrature Decoder 1 Registers Address Map Quadrature Decoder 1 is NOT available in the 56F8156 device Register ...
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Table 4-19 Interrupt Control Registers Address Map Register Acronym IPR 0 IPR 1 IPR 2 IPR 3 IPR 4 IPR 5 IPR 6 IPR 7 IPR 8 IPR 9 VBA FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 IRQP 0 IRQP 1 ...
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Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) Register Acronym ADCA_CR 2 ADCA_ZCC ADCA_LST 1 ADCA_LST 2 ADCA_SDIS ADCA_STAT ADCA_LSTAT ADCA_ZCSTAT ADCA_RSLT 0 ADCA_RSLT 1 ADCA_RSLT 2 ADCA_RSLT 3 ADCA_RSLT 4 ADCA_RSLT 5 ADCA_RSLT 6 ADCA_RSLT 7 ADCA_LLMT 0 ADCA_LLMT ...
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Table 4-20 Analog-to-Digital Converter Registers Address Map (Continued) Register Acronym ADCA_OFS 0 ADCA_OFS 1 ADCA_OFS 2 ADCA_OFS 3 ADCA_OFS 4 ADCA_OFS 5 ADCA_OFS 6 ADCA_OFS 7 ADCA_POWER ADCA_CAL Table 4-21 Analog-to-Digital Converter Registers Address Map Register Acronym ADCB_CR 1 ADCB_CR ...
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Table 4-21 Analog-to-Digital Converter Registers Address Map (Continued) Register Acronym ADCB_LLMT 1 ADCB_LLMT 2 ADCB_LLMT 3 ADCB_LLMT 4 ADCB_LLMT 5 ADCB_LLMT 6 ADCB_LLMT 7 ADCB_HLMT 0 ADCB_HLMT 1 ADCB_HLMT 2 ADCB_HLMT 3 ADCB_HLMT 4 ADCB_HLMT 5 ADCB_HLMT 6 ADCB_HLMT 7 ...
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Table 4-23 Serial Communication Interface 0 Registers Address Map Register Acronym SCI0_SCIBR SCI0_SCICR SCI0_SCISR SCI0_SCIDR Table 4-24 Serial Communication Interface 1 Registers Address Map Register Acronym SCI1_SCIBR SCI1_SCICR SCI1_SCISR SCI1_SCIDR Table 4-25 Serial Peripheral Interface 0 Registers Address Map Register ...
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Table 4-26 Serial Peripheral Interface 1 Registers Address Map Register Acronym SPI1_SPSCR SPI1_SPDSR SPI1_SPDRR SPI1_SPDTR Table 4-27 Computer Operating Properly Registers Address Map Register Acronym COPCTL COPTO COPCTR Table 4-28 Clock Generation Module Registers Address Map Register Acronym PLLCR PLLDB ...
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Table 4-29 GPIOA Registers Address Map (Continued) Address Offset Register Acronym $5 GPIOA_IENR $6 GPIOA_IPOLR $7 GPIOA_IPR $8 GPIOA_IESR GPIOA_PPMODE $9 $A GPIOA_RAWDATA Table 4-30 GPIOB Registers Address Map Register Acronym Address Offset GPIOB_PUR $0 GPIOB_DR $1 GPIOB_DDR $2 GPIOB_PER ...
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Table 4-31 GPIOC Registers Address Map (Continued) Register Acronym Address Offset GPIOC_IAR GPIOC_IENR GPIOC_IPOLR GPIOC_IPR GPIOC_IESR GPIOC_PPMODE GPIOC_RAWDATA Table 4-32 GPIOD Registers Address Map Register Acronym Address Offset GPIOD_PUR GPIOD_DR GPIOD_DDR GPIOD_PER GPIOD_IAR GPIOD_IENR GPIOD_IPOLR GPIOD_IPR GPIOD_IESR GPIOD_PPMODE GPIOD_RAWDATA Table ...
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Table 4-33 GPIOE Registers Address Map (Continued) Register Acronym Address Offset GPIOE_IENR GPIOE_IPOLR GPIOE_IPR GPIOE_IESR GPIOE_PPMODE GPIOE_RAWDATA Table 4-34 GPIOF Registers Address Map Register Acronym GPIOF_PUR GPIOF_DR GPIOF_DDR GPIOF_PER GPIOF_IAR GPIOF_IENR GPIOF_IPOLR GPIOF_IPR GPIOF_IESR GPIOF_PPMODE GPIOF_RAWDATA 70 (GPIOE_BASE = $00 ...
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Table 4-35 System Integration Module Registers Address Map Register Acronym SIM_CONTROL SIM_RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ID SIM_LSH_ID SIM_PUDR SIM_CLKOSR SIM_GPS SIM_PCE SIM_ISALH SIM_ISALL Table 4-36 Power Supervisor Registers Address Map Register Acronym LVI_CONTROL LVI_STATUS Table 4-37 Flash Module Registers ...
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Table 4-37 Flash Module Registers Address Map (Continued) Register Acronym FMPROT FMPROTB FMUSTAT FMCMD FMOPT 0 FMOPT 1 FMOPT 2 Table 4-38 FlexCAN Registers Address Map FlexCAN is NOT available in the 56F8156 device Register Acronym FCMCR FCCTL0 FCCTL1 FCTMR ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8156 device Register Acronym FCRX15MASK_L FCSTATUS FCIMASK1 FCIFLAG1 FCR/T_ERROR_CNTRS FCMB0_CONTROL FCMB0_ID_HIGH FCMB0_ID_LOW FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMB0_DATA FCMSB1_CONTROL FCMSB1_ID_HIGH FCMSB1_ID_LOW FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB1_DATA FCMB2_CONTROL FCMB2_ID_HIGH FCMB2_ID_LOW FCMB2_DATA ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8156 device Register Acronym FCMB2_DATA FCMB3_CONTROL FCMB3_ID_HIGH FCMB3_ID_LOW FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB3_DATA FCMB4_CONTROL FCMB4_ID_HIGH FCMB4_ID_LOW FCMB4_DATA FCMB4_DATA FCMB4_DATA FCMB4_DATA FCMB5_CONTROL FCMB5_ID_HIGH FCMB5_ID_LOW FCMB5_DATA FCMB5_DATA FCMB5_DATA FCMB5_DATA FCMB6_CONTROL ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8156 device Register Acronym FCMB6_DATA FCMB7_CONTROL FCMB7_ID_HIGH FCMB7_ID_LOW FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB7_DATA FCMB8_CONTROL FCMB8_ID_HIGH FCMB8_ID_LOW FCMB8_DATA FCMB8_DATA FCMB8_DATA FCMB8_DATA FCMB9_CONTROL FCMB9_ID_HIGH FCMB9_ID_LOW FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB9_DATA FCMB10_CONTROL ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8156 device Register Acronym FCMB10_DATA FCMB11_CONTROL FCMB11_ID_HIGH FCMB11_ID_LOW FCMB11_DATA FCMB11_DATA FCMB11_DATA FCMB11_DATA FCMB12_CONTROL FCMB12_ID_HIGH FCMB12_ID_LOW FCMB12_DATA FCMB12_DATA FCMB12_DATA FCMB12_DATA FCMB13_CONTROL FCMB13_ID_HIGH FCMB13_ID_LOW FCMB13_DATA FCMB13_DATA FCMB13_DATA FCMB13_DATA FCMB14_CONTROL ...
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Table 4-38 FlexCAN Registers Address Map (Continued) FlexCAN is NOT available in the 56F8156 device Register Acronym FCMB14_DATA FCMB14_DATA FCMB14_DATA FCMB15_CONTROL FCMB15_ID_HIGH FCMB15_ID_LOW FCMB15_DATA FCMB15_DATA FCMB15_DATA FCMB15_DATA 4.8 Factory Programmed Memory The Boot Flash memory block is programmed during manufacturing ...
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Programmable priority levels for each IRQ • Two programmable Fast Interrupts • Notification to SIM module to restart clocks out of Wait and Stop modes • Drives initial address on the address bus after reset For further information, see ...
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See IPIC field definition in 5.3.3 Fast Interrupt Handling Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes fast interrupts before the core does. A fast interrupt is defined (to the ITCN) by: 1. Setting ...
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Block Diagram Priority Level 2 -> 4 INT1 Decode Priority Level 2 -> 4 INT82 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • Functional Mode The ...
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The ITCN peripheral has 24 registers. Register Base Address + Acronym IPR0 $0 IPR1 $1 IPR2 $2 IPR3 $3 IPR4 $4 IPR5 $5 IPR6 $6 IPR7 $7 IPR8 ...
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Add. Register Offset Name IPR0 BKPT_U0 IPL IPR1 IPR2 FMCBE IPL FMCC IPL W R GPIOD $3 IPR3 IPL IPR4 SPI0_RCV ...
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Interrupt Priority Register 0 (IPR0) Base + $ Read 0 0 BKPT_U0 IPL Write RESET Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.1 Reserved—Bits 15–14 This bit field is reserved or not implemented. ...
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Reserved—Bits 15–6 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.2.2 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)—Bits 5–4 This field is used to set the ...
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Interrupt Priority Register 2 (IPR2) Base + $ Read FMCBE IPL FMCC IPL Write RESET Figure 5-5 Interrupt Priority Register 2 (IPR2) 5.6.3.1 Flash Memory Command, Data, Address Buffers Empty Interrupt Priority Level ...
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IRQ is priority level 2 5.6.3.4 PLL Loss of Lock Interrupt Priority Level (LOCK IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. ...
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IRQ is priority level 1 • IRQ is priority level 2 5.6.4 Interrupt Priority Register 3 (IPR3) Base + $ Read GPIOD GPIOE IPL IPL Write RESET Figure 5-6 ...
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FlexCAN Message Buffer Interrupt Priority Level (FCMSGBUF IPL)—Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ ...
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Interrupt Priority Register 4 (IPR4) Base + $ Read SPI0_RCV SPI1_XMIT IPL Write RESET Figure 5-7 Interrupt Priority Register 4 (IPR4) 5.6.5.1 SPI0 Receiver Full Interrupt Priority Level (SPI0_RCV IPL)— Bits 15–14 This ...
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IRQ is priority level 2 5.6.5.4 Reserved—Bits 9–6 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 5.6.5.5 GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 5–4 This field ...
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They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.6.2 Quadrature Decoder 1 HOME ...
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SCI 1 Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)— Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 ...
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Timer C, Channel 0 Interrupt Priority Level (TMRC0 IPL)— Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 ...
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Timer D, Channel 0 Interrupt Priority Level (TMRD0 IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 ...
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Interrupt Priority Register 7 (IPR7) Base + $ Read TMRA0 IPL TMRB3 IPL Write RESET Figure 5-10 Interrupt Priority Register (IPR7) 5.6.8.1 Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)— Bits 15–14 ...
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IRQ is priority level 1 • IRQ is priority level 2 5.6.8.5 Timer B, Channel 0 Interrupt Priority Level (TMRB0 IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This ...
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Interrupt Priority Register 8 (IPR8) Base + $ Read SCI0_RCV SCI0_RERR IPL Write RESET Figure 5-11 Interrupt Priority Register 8 (IPR8) 5.6.9.1 SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL)— Bits 15–14 This ...
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SCI0 Transmitter Empty Interrupt Priority Level (SCI0_XMIT IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • ...
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Interrupt Priority Register 9 (IPR9) Base + $ Read PWMA_F IPL PWMB_F IPL Write RESET Figure 5-12 Interrupt Priority Register 9 (IPR9) 5.6.10.1 PWM A Fault Interrupt Priority Level (PWMA_F IPL)—Bits 15–14 This ...
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IRQ is priority level 2 5.6.10.5 ADC A Zero Crossing or Limit Error Interrupt Priority Level ADCA_ZC IPL)—Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities ...
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Vector Base Address Register (VBA) Base + $ Read Write RESET Figure 5-13 Vector Base Address Register (VBA) 5.6.11.1 Reserved—Bits 15–13 This bit field is reserved or not implemented. It ...
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Fast Interrupt 0 Vector Address Low Register (FIVAL0) Base + $ Read Write RESET Figure 5-15 Fast Interrupt 0 Vector Address Low Register (FIVAL0) 5.6.13.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0 ...
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Fast Interrupt Vector Address registers without having jump table first; see Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will occur if ...
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IRQ Pending (PENDING)—Bits 16–2 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • IRQ pending for this vector number • IRQ pending for ...
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IRQ Pending 3 Register (IRQP3) Base + $ Read Write RESET Figure 5-23 IRQ Pending 3 Register (IRQP3) 5.6.21.1 IRQ Pending (PENDING)—Bits 64–49 This register combines with the other five to represent the ...
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IRQ Pending (PENDING)—Bit 81 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • IRQ pending for this vector number • IRQ pending for ...
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Required nested exception priority level is 3 5.6.30.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6 This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This field is only ...
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Resets 5.7.1 Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset vector will be presented until the second rising clock edge after RESET is released. 5.7.2 ITCN After ...
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Part 6 System Integration Module (SIM) 6.1 Overview The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls distribution of resets and clocks and provides a number of control features. The system ...
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Operating Modes Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the various chip operating modes and take appropriate action. These are: • Reset Mode, which has two submodes: — POR and ...
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Register Descriptions Address Offset Address Acronym Base + $0 SIM_CONTROL Base + $1 SIM_RSTSTS Base + $2 SIM_SCR0 Base + $3 SIM_SCR1 Base + $4 SIM_SCR2 Base + $5 SIM_SCR3 Base + $6 SIM_MSH_ID Base + $7 SIM_LSH_ID Base ...
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Add. Register Offset Name SIM_ $0 CONTROL SIM_ $1 RSTSTS SIM_SCR0 SIM_SCR1 SIM_SCR2 SIM_SCR3 SIM_MSH_ ...
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EMI_MODE (EMI_MODE)—Bit 6 This bit reflects the current (non-clocked) state of the EMI_MODE pin. During reset, this bit, coupled with the EXTBOOT signal, is used to initialize address bits [19:16] either as GPIO or as address. These settings can ...
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Base + $ Read Write RESET Figure 6-4 SIM Reset Status Register (SIM_RSTSTS) 6.5.2.1 Reserved—Bits 15–6 This bit field is reserved or not implemented read as 0 and cannot ...
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Base + $ Read Write POR Figure 6-5 SIM Software Control Register 0 (SIM_SCR0) 6.5.3.1 Software Control Data 1 (FIELD)—Bits 15–0 This register is reset only by the Power-On Reset (POR). It has no ...
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SIM Pull-up Disable Register (SIM_PUDR) Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by ...
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This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.6.11 CTRL—Bit 5 This bit controls the pull-up resistors on the WR and RD pins. 6.5.6.12 Reserved—Bit 4 This bit field ...
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Alternate GPIOB Peripheral Function for A22 (A22)—Bit 8 • Peripheral output function of GPIOB6 is defined to be A22 • Peripheral output function of GPIOB6 is defined to be SYS_CLK2 6.5.7.4 Alternate GPIOB Peripheral Function ...
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The four I/O pins associated with GPIOC can function as GPIO, Quad Decoder 1/Quad Timer SPI 1 signals. GPIO is not the default and is enabled/disabled via the GPIOC_PER, as shown in ...
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Table 6-2 Control of Pads Using SIM_GPS Control Pin Function SPI input 1 SPI output 1 1. This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of ...
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GPIOC0 (C0)—Bit 0 This bit selects the alternate function for GPIOC0. • PHASEA1/TB0 (default) • SCLK1 6.5.9 Peripheral Clock Enable Register (SIM_PCE) The Peripheral Clock Enable register is used to enable or disable clocks to ...
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The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.6 Decoder 0 Enable (DEC0)—Bit 10 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock ...
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The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.13 Serial Peripheral Interface 1 Enable (SPI1)—Bit 3 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • ...
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Bits from SIM_ISALL Register 2 bits from SIM_ISALH Register Full 24-Bit for Short I/O Address Figure 6-13 I/O Short Address Determination With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral ...
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Input/Output Short Address Low (ISAL[21:6])—Bit 15–0 This field represents the lower 16 address bits of the “hard coded” I/O short address. 6.6 Clock Generation Overview The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce ...
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Stop and Wait Mode Disable Function Permanent Disable Reprogrammable Disable Clock Select Figure 6-16 Internal Stop Disable Circuit The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest power consumption in Stop ...
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Flash security, and, finally, followed clock window in which the core is initialized. After completion of the described reset sequence, application code will ...
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Secure Mode When Flash security is enabled as described in the Flash Memory module specification, the device will boot in internal boot mode, disable all access to external P-space, and start executing code from the Boot Flash at address ...
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SYS_CLK 2 FM_CLKDIV JTAG FM_ERASE Figure 7-1 JTAG to FM Connection for Lockout Recovery Two examples of FM_CLKDIV calculations follow. EXAMPLE 1: If the system clock is the 8MHz crystal frequency because the PLL has not been set up, the ...
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Note: Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller (by asserting TRST) and the device (by asserting external chip reset) to return to normal unsecured operation. 7.2.4 Product Analysis The recommended method ...
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Table 8-1 56F8356 GPIO Ports Configuration Available GPIO Port Pins in Port Width 56F8356 14 pins - EMI Address pins pin - EMI Address pin pins - EMI Address pins - Not ...
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Table 8-2 56F8156 GPIO Ports Configuration Available GPIO Port Pins in Port Width 56F8156 pins - SCI0 2 pins - EMI Address pins 4 pins - SPI0 1 pin - TMRC 1 pin - TMRC - ...
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Table 8-3 GPIO External Signals Map Pins in shaded rows are not available in 56F8356/56F8156 Pins in italics are NOT available in the 56F8156 device GPIO Port GPIOA GPIOB Freescale Semiconductor Preliminary Reset GPIO Bit Function 0 Peripheral 1 Peripheral ...
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Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8356/56F8156 Pins in italics are NOT available in the 56F8156 device GPIO Port 1 This is a function of the EMI_MODE, EXTBOOT and Flash security ...
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Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8356/56F8156 Pins in italics are NOT available in the 56F8156 device GPIO Port GPIOD GPIOE Freescale Semiconductor Preliminary Reset GPIO Bit Function 0 GPIO 1 ...
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Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8356/56F8156 Pins in italics are NOT available in the 56F8156 device GPIO Port GPIOF 1. See Part 6.5.8 to determine how to select peripherals from ...
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In such systems, a bus may carry both 3.3V- and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during normal ...
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Table 10-1 Absolute Maximum Ratings (Continued) Characteristic Output Voltage (open drain) Ambient Temperature (Automotive) Ambient Temperature (Industrial) Junction Temperature (Automotive) Junction Temperature (Industrial) Storage Temperature (Automotive) Storage Temperature (Industrial corresponding GPIO pin is configured as open drain. Note: ...
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Characteristic Junction to ambient Natural convection Junction to ambient (@1m/sec) Junction to ambient Natural convection Junction to ambient (@1m/sec) Junction to case Junction to center of case I/O pin power dissipation Power dissipation Maximum allowed Theta-JA determined ...
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Table 10-4 Recommended Operating Conditions (V = 0V, V REFLO Characteristic ADC Supply Voltage Oscillator / PLL Supply Voltage Internal Logic Core Supply Voltage Device Clock Frequency Input High Voltage (digital) Input High Voltage (analog) Input High Voltage (XTAL/EXTAL, XTAL ...
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Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions; see Characteristic Symbol Output High Voltage V Output Low Voltage V Digital Input Current High pull-up enabled or disabled Digital Input Current High with pull-down Analog Input Current High ADC Input ...
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Table 10-6 Power on Reset Low Voltage Parameters Characteristic POR Trip Point 1 LVI, 2.5 volt Supply, trip point 2 LVI, 3.3 volt supply, trip point Bias Current 1. When V drops below V DD_CORE 2. When V drops below ...
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Table 10-8 Current Consumption per Power Supply Pin (Typical) On-Chip Regulator Disabled (OCR_DIS = High) I Mode DD_Core RUN1_MAC 150mA Wait3 86mA Stop1 900μA Stop2 100μ Output Switching Characteristic Unloaded Output Voltage (0mA Load) Loaded Output Voltage (200 ...
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Characteristics PLL Start-up time Resonator Start-up time Min-Max Period Variation Peak-to-Peak Jitter Bias Current Quiescent Current, power-down mode 10.2.1 Temperature Sense Note: Temperature Sensor is NOT available in the 56F8156 device. Table 10-11 Temperature Sense Parametrics Characteristics 1 Slope (Gain) ...
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AC Electrical Characteristics Tests are conducted using the input levels specified in propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in ...
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Specifies page erase time. There are 512 bytes per page in the Data and Boot Flash memories. The Program Flash module uses two interleaved Flash memories, increasing the effective page size to 1024 bytes. 10.5 External Clock Operation Timing ...
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This is the minimum time required after the PLL set up is changed to ensure reliable operation. 10.7 Crystal Oscillator Timing Table 10-15 Crystal Oscillator Parameters Characteristic Crystal Start-up time Resonator Start-up time Crystal ESR Crystal Peak-to-Peak Jitter Crystal ...
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When using the XTAL clock input directly as the chip clock without prescaling (ZSRC selects prescaler ÷ 1), clock and prescaler set to clock input. In this situation only, parameter values must be adjusted for the duty cycle at XTAL. ...
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Note: When multiple lines are given for the same wait state configuration, calculate each and then select the smallest or most negative. Table 10-16 External Memory Interface Timing Characteristic Address Valid to WR Asserted WR Width Asserted to WR Deasserted ...
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Table 10-16 External Memory Interface Timing (Continued) Characteristic RD Deasserted to RD Asserted WR Deasserted to WR Asserted RD Deasserted to WR Asserted 1. N/A since device captures data before it deasserts RWSS = RWSH = 0, ...
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Table 10-17 Reset, Stop, Wait, Mode Select, and Interrupt Timing Characteristic IRQA Width Assertion to Recover from Stop 5 State 1. In the formulas clock cycle. For an operating frequency of 60MHz 16.67ns. At 8MHz (used ...
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A0–A15 t IDM , IRQA IRQB General Purpose I/O Pin IRQA IRQB Figure 10-7 External Level-Sensitive Interrupt Timing IRQA , IRQB A0–A15 Figure 10-8 Interrupt from Wait State Timing t IW IRQA A0–A15 Figure 10-9 Recovery from ...
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Serial Peripheral Interface (SPI) Timing Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Data set-up time required for inputs Master ...
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Characteristic Fall time Master Slave 1. Parameters listed are guaranteed by design. SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) MOSI (Output) Figure 10-10 SPI Master Timing (CPHA = 0) 154 1 Table 10-18 ...
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SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref MOSI (Output) Figure 10-11 SPI Master Timing (CPHA = 1) Freescale Semiconductor Preliminary SS is held High on master ...
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SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 10-12 SPI Slave Timing (CPHA = 0) 156 ELD ...
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SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input MISO (Output) MOSI (Input) Figure 10-13 SPI Slave Timing (CPHA = 1) 10.11 Quad Timer Timing Characteristic Timer input period Timer input high / low period ...
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Timer Inputs Timer Outputs 10.12 Quadrature Decoder Timing Table 10-20 Quadrature Decoder Timing Characteristic Quadrature input period Quadrature input high / low period Quadrature phase period 1. In the formulas listed the clock cycle. For 60MHz operation, T=16.67ns. ...
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Serial Communication Interface (SCI) Timing Characteristic Symbol 2 Baud Rate 3 RXD RXD Pulse Width 4 TXD TXD Pulse Width 1. Parameters listed are guaranteed by design the frequency of operation of the system clock, ZCLK, ...
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CAN_RX CAN receive data pin (Input) Figure 10-18 Bus Wake Up Detection 10.15 JTAG Timing Characteristic TCK frequency of operation using 1 EOnCE TCK frequency of operation not 1 using EOnCE TCK clock pulse width TMS, TDI data set-up time ...
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TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) TDO (Output) Figure 10-20 Test Access Port Timing Diagram TRST (Input) 10.16 Analog-to-Digital Converter (ADC) Parameters Characteristic Input voltages Resolution 1 Integral Non-Linearity Differential Non-Linearity Monotonicity ADC internal clock Conversion ...
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Table 10-24 ADC Parameters (Continued) Characteristic ADC reference circuit power-up time Conversion time Sample time Input capacitance 5 Input injection current , per pin Input injection current, total V current REFH ADC A current ADC B current Quiescent current Uncalibrated ...
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Figure 10-22 ADC Absolute Error Over Processing and Temperature Extremes Before and After Calibration for VDC Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset error. The data was taken ...
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Equivalent Circuit for ADC Inputs Figure 10-23 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed & open, one ...
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Equivalent resistance for the ESD isolation resistor and the channel select mux; 500 ohms 4. Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only connected sampling ...
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Summation is performed over all output pins with capacitive loads • TotalPower is expressed in mW • Cload is expressed in pF Because of the low duty cycle on most device pins, power dissipation due to capacitive loads ...
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Part 11 Packaging 11.1 56F8356 Package and Pin-Out Information This section contains package and pin-out information for the 56F8356. This device comes in a 144-pin Low-profile Quad Flat Pack (LQFP). Figure 11-3 shows the mechanical parameters for this package, and ...
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Table 11-1 56F8356 144-Pin LQFP Package Identification by Pin Number Signal Pin No. Pin No. Name DD_IO CLKO 39 4 TXD0 40 5 RXD0 41 6 PHASEA1 42 7 PHASEB1 43 ...
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Table 11-1 56F8356 144-Pin LQFP Package Identification by Pin Number Signal Pin No. Pin No. Name 26 A15 DD_IO 32 D10 68 33 ...
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Orientation Mark V DD_IO CLKO Pin 1 TXD0 RXD0 SCLK1 MOSI1 MISO1 SS1 CAP V DD_IO A10 A11 A12 A13 A14 A15 ...
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Table 11-2 56F8156 144-Pin LQFP Package Identification by Pin Number Signal Pin No. Pin No. Name 3 CLKO 39 4 TXD0 40 5 RXD0 41 6 SCLK1 42 7 MOSI1 43 8 MISO1 44 9 SS1 ...
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Table 11-2 56F8156 144-Pin LQFP Package Identification by Pin Number Signal Pin No. Pin No. Name DD_IO 32 D10 68 33 GPIOB0 69 34 ...
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H B PIN 1 144 INDEX D1/2 D TOP VIEW H A SIDE VIEW PLATING BASE b METAL 0. SECTION A-A ° ...
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Please see www.freescale.com for the most current case outline. Part 12 Design Considerations 12.1 Thermal Design Considerations An estimation of the chip junction temperature θJΑ where ...
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T = Thermocouple temperature on top of package ( T Ψ = Thermal characterization parameter ( Power dissipation in package (W) D The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T ...
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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005, 2006. All rights reserved. MC56F8356 Rev. 13 ...