SAA7111 NXP Semiconductors, SAA7111 Datasheet
SAA7111
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SAA7111 Summary of contents
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... DATA SHEET SAA7111 Video Input Processor (VIP) Product specification Supersedes data of 1996 Oct 30 File under Integrated Circuits, IC22 INTEGRATED CIRCUITS 1998 May 15 ...
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... Anti-alias filter curve 17.2 Luminance filter curves 17.3 Chrominance filter curves START SET-UP 19 PACKAGE OUTLINE 20 SOLDERING 20.1 Introduction 20.2 Reflow soldering 20.3 Wave soldering 20.3.1 PLCC 20.3.2 QFP 20.3.3 Method (PLCC and QFP) 20.4 Repairing soldered joints 21 DEFINITIONS 22 LIFE SUPPORT APPLICATIONS 23 PURCHASE OF PHILIPS I 2 Product specification SAA7111 2 C COMPONENTS ...
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... BGHI, PAL M, PAL N, NTSC M and NTSC N), a brightness/contrast/saturation control circuit and a colour space matrix (see Fig.1). The CMOS circuit SAA7111, analog front-end and digital video decoder highly integrated circuit for desktop video applications. The decoder is based on the principle ...
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... A+D 5 ORDERING INFORMATION TYPE NUMBER NAME SAA7111WP PLCC68 plastic leaded chip carrier; 68 leads SAA7111H QFP64 plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 1998 May 15 PARAMETER PACKAGE DESCRIPTION 14 2 Product specification SAA7111 MIN. TYP. MAX. 4.5 5.0 5.5 V 4.75 5.0 5. 0.77 1.0 1.26 W VERSION ...
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... LFCO (30) (27) (17) (29) (28) (60 VREF RTS0 RTS1 RTCO Fig.1 Block diagram. 5 Product specification SAA7111 VPO YUV-to-RGB 15) CONVERSION (34 to 39) AND (42 to 51) OUTPUT FORMATTER (52) 63 FEI (31) 42 HREF 2 I C-BUS CONTROL (53) 64 GPSW 2 I C-BUS ...
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... VPO-bus are able to generate a bus timing with identical phase. If CCIR-656 format is selected (OFTS0 = 1 and OFTS1 = 1) an inverse composite blank signal (pixel qualifier) is provided on this pin. 6 Product specification DESCRIPTION 48H for write, 49H for read, 2 C-bit COMPO = 0) or inverse 2 C-bit COMPO = 1) (enabled via I 1 output (13.5 MHz). 2 SAA7111 2 C-bit ...
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... MSBs of the digitized input signal (AD1 [7 to 2]) are connected to these outputs. 40 GND Digital ground for positive supply voltage Positive digital supply voltage 2 (+5 V). 7 Product specification SAA7111 DESCRIPTION 2 C-bus is reset 2 C-bus bytes HSB and HSS. 2 C-bit RTSE1. Y component for PAL signals. 2 C-bit RTSE0 ...
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... Input terminal for 24.576 MHz crystal oscillator or connection of external oscillator with CMOS compatible square wave clock signal. 56 GND Digital ground for positive supply voltage Positive digital supply voltage 1 (+5 V). 8 Product specification SAA7111 DESCRIPTION 2 C-bits 2 C-bit VIPB = 1 the digitized input signals ...
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... DDA2 17 AI21 V SSA1 18 AI12 DDA1 AI11 AOUT 24 V DDA0 V 25 SSA0 26 VREF 1998 May 15 SAA7111 Fig.2 Pin configuration (PLCC68). 9 Product specification SAA7111 60 VPO3 59 VPO3 58 VPO4 57 VPO5 56 VPO6 55 VPO7 54 VPO8 53 VPO9 V 52 DD2 51 V SS2 50 VPO10 49 VPO11 48 VPO12 ...
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... AI22 V DDA2 7 AI21 8 V SSA1 9 10 AI12 V DDA1 11 AI11 AOUT V DDA0 15 V SSA0 16 1998 May 15 SAA7111 Fig.3 Pin configuration (QFP64). 10 Product specification SAA7111 48 VPO3 47 VPO4 46 VPO5 45 VPO6 44 VPO7 43 VPO8 42 VPO9 V DD2 41 V SS2 40 39 VPO10 38 VPO11 37 VPO12 36 VPO13 ...
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... Video Input Processor (VIP) 8 FUNCTIONAL DESCRIPTION 8.1 Analog input processing The SAA7111 offers four analog signal inputs, two analog main channels with clamp circuit, analog amplifier, anti-alias filter and video CMOS ADC (see Fig.6). 8.2 Analog control circuits The anti-alias filters are adapted to the line-locked clock frequency with help from a filter control ...
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... A pixel in the format tables is the time required to transfer a full set of samples. In the event format two luminance samples are transmitted in comparison to one (B Y) and one (R Y) sample within a pixel. The time frames are controlled by the HREF signal. 12 Product specification SAA7111 2 C-bus bits ...
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... Field 1 or 2). After valid data has been read the corresponding F*RDY bit is set to LOW until new data has arrived. The polling frequency has to be slightly supply DDA0 higher than the frame or field frequency, respectively. 13 Product specification SAA7111 2 C-bus programming 2 C-bus ...
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Acrobat reader. white to force landscape pages to be ... 64 n. SSA1 5 V SSA2 6 AI22 SOURCE CLAMP 8 SWITCH ...
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Acrobat reader. white to force landscape pages to be ... LUM CHR 10 (1) n.c. 1 (58) TRST 2 (59) QUADRATURE TCK TEST 12 ...
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Acrobat reader. white to force landscape pages to be ... LUM LUMINANCE CIRCUIT CHROMINANCE PREFILTER TRAP PREF BYPS VBLB PREFILTER SYNC LINE 21 TEXT ...
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... Fig.9 Amplifier curve. ANALOG INPUT ADC 1 0 VBLK <- CLAMP GAIN -> HCL 0 0 SBOT NO CLAMP CLAMP GAIN Fig.10 Clamp and gain flow. 17 Product specification MGC648 ( i 257 512 512 1 0 HSY WIPE slow GAIN GAIN fast GAIN MGC647 SAA7111 ...
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... GAIN ACCUMULATOR (18 BITS) ACTUAL GAIN VALUE 9-BIT (AGV dB AGV Fig.11 Gain flow chart. 18 Product specification 9 DAC LUMA/CHROMA DECODER HSY >254 1/LLC2 0 0 HSY UPDATE FGV GAIN VALUE 9-BIT MGC652 SAA7111 ...
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... C; unless otherwise specified. amb CONDITIONS 4.5 100 0.45 4.75 60 0. coupling 0.55 capacitor = 10 nF; note 1 clamping current off 200 MHz Product specification SAA7111 MIN. MAX. 0.5 +6.5 V 0.5 +6.5 V 100 mV 65 +150 +80 C 2000 +2000 V MIN. TYP. MAX. ...
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... PDZ 1998 May 15 CONDITIONS MIN. 0.5 0.7V 0.7V 0.5 2.0 inputs and outputs at high-impedance SDA/SCL sink current note 2 0 note 2 2.4 0.5 2 Product specification SAA7111 TYP. MAX. UNIT +1 0.5 V DDD DDD 0.3V V DDD V DDD +0 0.5 V DDD 0 ...
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... LLC/LLC2 = nominal frequency XTALI 50 Hz field 60 Hz field PAL BGHI and NTSC 443 NTSC M PAL M PAL N 21 Product specification SAA7111 MIN. TYP. MAX 15625 15734 5 ...
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... With amplifier, without anti-alias filter With amplifier plus anti-alias filter 1998 May 15 CONDITIONS MIN. 3rd harmonic OHD;DAT TYPICAL ANALOG DELAY AI22 ADCIN (AOUT) (ns Product specification SAA7111 TYP. MAX. 24.576 MHz 1.5 20% fF 3.5 20 pF. ...
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... Fig.13 Clock/data timing (12/16-bit CCIR-601 format of the VPO-bus). 1998 May 15 t LLC t LLCL LLCH OHD;DAT t LLC t LLC t LLCL LLCH OHD;CREF OHD;CREF t dLLC2 OHD;DAT 23 Product specification SAA7111 2.6 V 1 2.4 V 0.6 V MGC658 2.6 V 1.5 V 0.6 V 2 dLLC2 2.6 V 1.5 V 0.6 V 2.4 V 0.6 V MGC659 ...
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... PD;CREF t OHD;CREF t OHD;CREF t PD;CREF R G OHD;DAT Fig.14 Clock/data timing for RGB888 output format. t SU;DAT t PDZ t OHD;DAT to 3-state 24 Product specification t LLC t OHD;CREF t OHD;DAT G B HD;DAT t PD MGC656 from 3-state SAA7111 2.4 V 1.5 V 0.6 V 2.4 V 1.5 V 0.6 V 2.4 V 1.5 V 0.6 V 2.4 V 1.5 V 0.6 V MBH227 ...
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... Fig.16 Real time control output. t SU;DAT t PDZ t OHD;DAT to 3-state 25 SEQUENCE C-bit CDTO. RTCO sequence is generated in LLC/4. t HD;DAT t PD from 3-state Product specification SAA7111 (1) DTO RESET RESERVED 50 Hz fields: 235 60 Hz fields: 232 68 MGC649 MGC657 ...
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... LLC CREF LLC2 START OF ACTIVE LINE HREF Yn UVn HREF 715 Yn V714 UVn 1998 May 716 717 718 U716 V716 U718 Fig.18 HREF timing diagram. 26 Product specification SAA7111 END OF ACTIVE LINE 719 V718 MGC646 ...
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... CVBS->VPO 720 x 2/LLC 7 x 2/LLC 113 x 2/LLC (1) HS 108 2/LLC 720 x 2/LLC 107 0 2 C-bit RTSE1 = 0. Fig.19 Horizontal timing diagram. 27 Product specification burst (2) sync clipped 12 x 2/LLC 144 x 2/LLC 4/LLC 107 16 x 2/LLC 138 x 2/LLC 106 MGC664 SAA7111 ...
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... Fig.20 Vertical timing diagram for 50 Hz [nominal input signal VNL in normal mode (VNOI = 00b)]. 1998 May 15 625 624 a: 1st field 312 313 314 315 316 317 b: 2nd field 2 C-bit RTSE0 = 0. 28 Product specification 503 x 2/LLC 318 320 335 336 319 71 x 2/LLC 2 C-bit VBLB is set to logic 1. SAA7111 23 337 MGC662 ...
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... C-bit RTSE0 = (10) (11) (8) (9) (20) 493 x 2/LLC 267 268 269 270 271 (270) (271) (272) (273) (274 2/LLC 2 C-bit VBLB is set to logic 1. Product specification SAA7111 18 19 (22) (21) (2) 280 281 282 (283) (284) (285) (2) MGC663 ...
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... VPO (2) ( active active Z ZERO PHASE CROSS DETECTION DETECTION Fig.22 Block diagram of clock generation circuit. 30 Product specification SAA7111 CLOCK FREQUENCY (MHz) XTAL 24.576 LLC 27 LLC2 13.5 LLC4 6.75 LLC8 3.375 LOOP OSCILLATOR LLC FILTER DIVIDER DIVIDER LLC2 1/2 ...
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... RESINT = internal reset; LLC = line-locked system clock output; RES = reset output (active LOW). 1998 May 15 POC V DDA POC V DDD ANALOG CLOCK PLL LLC POC LOGIC 20 to 200 s PLL-delay digital delay < Fig.23 Power-on control circuit. 31 Product specification DIGITAL POC RES DELAY CLK0 896 LCC 128 LCC SAA7111 MGC633 ...
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... LLC2 OFTS0 = 0 OFTS1 = 0 RGB888 = 0 SAA7111 ( note 4 note 5 LLC OFTS0 = 0 ...
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... SAA7111 XTALI 66 (55 20 Fig.25 Oscillator application. 33 Product specification SAA7111 255 red 100% 240 212 red 75% colourless 128 V-COMPONENT cyan 75% 44 cyan 100 MGC634 c. V output range (Cr). XTAL 65 (54) SAA7111 XTALI 66 (55) MGC635 b. With external clock. ...
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... MGC651 n.c. n.c. n.c. n.c. n.c. n. SAA7111 V SS VPO( HREF VREF HS VS RTCO RTS1 RTS0 GPSW AOUT LLC LLC2 CREF RES ...
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... To avoid reflection effects use serial resistors in the clock, sync and data lines. 35 Product specification e.g. 74F240 LLC2N MGD137 SAA7111 ...
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... C-bus subaddress 00 has to be initialized with 0 before being read. 1998 May 15 SUBADDRESS ACK(s) ACK(s) ACK(s) DESCRIPTION read and write; note 3 read and write read and write read only read only 36 Product specification SAA7111 DATA (N BYTES) ACK(s) SUBADDRESS ACK(s) DATA (N BYTES) ACK( ...
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... OEHV CBR RGB888 DIT AOSL1 (1) (1) (1) (1) F2VAL F2RDY BYTE13 BYTE12 BYTE11 BYTE23 BYTE22 BYTE21 (1) (1) (1) GLIMB WIPA SLTCA SAA7111 D1 D0 ID01 ID00 (1) (1) MODE0 GAI28 GAI18 GAI11 GAI10 GAI21 GAI20 HSB1 HSB0 HSS1 HSS0 VNOI1 VNOI0 APER0 BRIG1 BRIG0 CONT0 ...
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... CONTROL BITS MODE 2 MODE CONTROL BITS GUDL 2 GUDL CONTROL BITS D7 AND D6 FUSE SAA7111 ID01 ID00 X X MODE GUDL FUSE ...
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... GAI1 level). AI22 handbook, halfpage CHROMA AI21 LUMA AI12 AI11 MGC643 Fig.35 Mode 7 Y (automatic gain (gain channel 2 adapted to Y gain). 39 Product specification SAA7111 AD2 CHROMA LUMA AD1 MGC638 AD2 CHROMA LUMA AD1 MGC640 AD2 CHROMA LUMA ...
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... Table 16 GAFIX 0 GAFIX 1 HOLDG 0 HOLDG 1 WPOFF 0 WPOFF 1 VBSL 0 VBSL 1 HLNRS 0 HLNRS 1 CONTROL BITS GAI14 GAI13 GAI12 Product specification SAA7111 CONTROL BIT GAI11 GAI10 ...
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... CONTROL BITS GAI24 GAI23 GAI22 HSB3 HSB2 HSS4 HSS3 HSS2 SAA7111 GAI21 GAI20 HSB1 HSB0 HSS1 HSS0 ...
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... Automatic field detection 1998 May 15 BIT NAME LOGIC LEVEL VNOI1 0 VNOI0 0 VNOI1 0 VNOI0 1 VNOI1 1 VNOI0 0 VNOI1 1 VNOI0 1 HPLL 0 HPLL 1 VTRC 0 VTRC 1 EXFIL 0 EXFIL 1 FSEL 0 FSEL 1 AUFD 0 AUFD 1 42 Product specification SAA7111 CONTROL BIT ...
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... APER1 0 APER0 1 APER1 1 APER0 0 APER1 1 APER0 1 UPTCV 0 UPTCV 1 VBLB 0 VBLB 1 BPSS1 0 BPSS0 0 BPSS1 0 BPSS0 1 BPSS1 1 BPSS0 0 BPSS1 1 BPSS0 1 PREF 0 PREF 1 BYPS 0 BYPS 1 43 Product specification SAA7111 CONTROL BIT ...
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... SATN5 SATN4 CONTROL BITS HUEC6 HUEC5 HUEC4 Product specification SAA7111 BRIG3 BRIG2 BRIG1 CONT3 CONT2 CONT1 ...
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... CHBW1 0 CHBW0 1 CHBW1 1 CHBW0 0 CHBW1 1 CHBW0 1 FCTC 0 FCTC 1 DCCF 0 DCCF 1 CSTD1 0 CSTD0 0 CSTD1 0 CSTD0 1 CSTD1 1 CSTD0 0 CSTD1 1 CSTD0 1 CM99 0 CM99 1 CDTO 0 CDTO 1 45 Product specification SAA7111 CONTROL BIT ...
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... Product specification CONTROL BITS YDEL1 VREF 625 LINES 0 286 first last first 24 309 23 337 622 336 CONTROL BITS D5 and D4 HDEL0 CONTROL BITS D7 and D6 OFTS0 SAA7111 YDEL0 288 last 310 623 ...
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... The pin number given in parenthesis refers to the 64-pin package. 1998 May 15 BIT NAME LOGIC LEVEL COLO 0 COLO 1 VIPB 0 VIPB 1 OEHV 0 OEHV 1 OEYC 0 OEYC 1 COMPO 0 COMPO 1 FECO 0 FECO 1 GPSW 0 GPSW 1 47 Product specification SAA7111 CONTROL BIT ...
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... The pin number given in parenthesis refers to the 64-pin package. 1998 May 15 BIT NAME LOGIC LEVEL AOSL1 0 AOSL0 0 AOSL1 0 AOSL0 1 AOSL1 1 AOSL0 0 AOSL1 1 AOSL0 1 DIT 0 DIT 1 RGB888 0 RGB888 1 CBR 0 CBR 1 RTSE0 0 RTSE0 1 RTSE1 0 RTSE1 1 48 Product specification SAA7111 CONTROL BIT ...
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... LOW = TV time-constant and HIGH = VTR time-constant 1998 May 15 ) ONLY REGISTER FUNCTION ) ONLY REGISTER FUNCTION ) ONLY REGISTER FUNCTION ) ONLY REGISTER FUNCTION 49 Product specification SAA7111 STATUS BIT DATA BITS DATA BITS STATUS BIT ...
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... Fig.37 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter on and different aperture band-pass centre frequencies. 1998 May Fig.36 Anti-alias filter. (1) (2) (4) ( Product specification (1) (2) (4) ( (MHz) SAA7111 MGD138 14 f (MHz) MGD139 8 ...
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... Fig.39 Luminance control SA 09H, 4.43 MHz Trap/CVBS mode, prefilter off and different aperture band-pass centre frequencies. 1998 May 15 (1) (2) (3) ( Product specification SAA7111 MGD140 (4) (3) (2) ( (MHz) MGD141 (1) (2) (4) ( ...
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... V Y (dB (1) = 80H; (2) = 81H; (3) = 82H; (4) = 83H. Fig.41 Luminance control SA 09H, Y/C mode, prefilter off and different aperture factors. 1998 May 15 (1) (2) (3) ( (1) (2) (3) ( Product specification SAA7111 MGD142 (MHz) MGD143 (MHz) ...
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... Fig.43 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter on and different aperture factors. 1998 May Product specification (1) (2) (4) ( (MHz) (4) (3) (2) ( (MHz) SAA7111 MGD144 8 MGD145 8 ...
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... V Y (dB) 6 (1) (2) (4) ( (1) = 03H; (2) = 13H; (3) = 23H; (4) = 33H. Fig.44 Luminance control SA 09H, 3.58 MHz Trap/CVBS mode, prefilter off and different aperture band-pass centre frequencies. 1998 May Product specification SAA7111 MGD146 (1) (2) (4) ( (MHz) 8 ...
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... CHBW [ 00; (2) CHBW [ 01; (3) CHBW [ 10; (4) CHBW [ 11 C-BUS START SET-UP The given values force the following behaviour of the SAA7111: – The analog input AI11 expects a signal in CVBS format; analog anti-alias filter active – Automatic field detection – YUV 422/16-bit output format enabled – ...
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... OEHV, VIPB and COLO RTSE(1 : 0), X, CBR, RGB888, DIT and AOSL F2VAL, F2RDY, F1VAL and F1RDY P1 and BYTE1 and BYTE2 STTC, HLCK, FIDT, GLIMT, GLIMB, WIPA and SLTCA and CODE 56 Product specification SAA7111 VALUES (BIN START ...
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... max. 25.27 25.27 1.22 1.44 0.51 0.18 0.18 25.02 25.02 1.07 1.02 0.995 0.995 0.048 0.057 0.020 0.007 0.007 0.004 0.985 0.985 0.042 0.040 EUROPEAN PROJECTION Product specification SAA7111 SOT188 (1) ( max. max. 0.10 2.16 2. 0.085 0.085 ISSUE DATE 92-11-17 95-03-11 ...
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... scale (1) ( 0.45 0.23 14.1 14.1 17.45 0.8 0.30 0.13 13.9 13.9 16.95 REFERENCES JEDEC EIAJ MS-022 detail 17.45 1.03 1.60 0.16 0.16 0.10 16.95 0.73 EUROPEAN PROJECTION Product specification SAA7111 SOT393 (1) ( 1.2 1 0.8 0.8 0 ISSUE DATE 96-05-21 97-08-04 ...
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... V) applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 59 Product specification SAA7111 QFP) ...
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... Philips. This specification can be ordered using the code 9398 393 40011. 1998 May 15 C COMPONENTS 2 C components conveys a license under the Philips’ system provided the system conforms to the I 60 Product specification SAA7111 2 C patent to use the 2 C specification defined by ...
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... Philips Semiconductors Video Input Processor (VIP) 1998 May 15 NOTES 61 Product specification SAA7111 ...
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... Philips Semiconductors Video Input Processor (VIP) 1998 May 15 NOTES 62 Product specification SAA7111 ...
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... Philips Semiconductors Video Input Processor (VIP) 1998 May 15 NOTES 63 Product specification SAA7111 ...
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Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, ...