AM28F010A-120JI Advanced Micro Devices, AM28F010A-120JI Datasheet
AM28F010A-120JI
Related parts for AM28F010A-120JI
AM28F010A-120JI Summary of contents
Page 1
... It is designed to be reprogrammed and erased in-system or in standard EPROM programmers. The Am28F010A is erased when shipped from the factory. The standard Am28F010A offers access times of as fast as 70 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#) and output enable (OE#) controls. AMD’ ...
Page 2
... During write cycles, the command register internally latches addresses and data needed for the program- ming and erase operations. For system design simpli- fication, the Am28F010A is designed to support either WE# or CE# controlled writes. During a system write 2 Embedded Erase ...
Page 3
... Erase Voltage Switch To Array Program Voltage Switch Chip Enable Output Enable Logic Embedded Algorithms Y-Decoder Program/Erase Pulse Timer X-Decoder Am28F010A Am28F010A -120 -150 -200 120 150 200 120 150 200 DQ0–DQ7 Input/Output Buffers Data Latch Y-Gating 1,048,576 Bit ...
Page 4
... A14 A13 A11 A10 DQ7 DQ0 DQ6 DQ5 DQ4 DQ3 16778D-2 Am28F010A PLCC A14 6 28 A13 A11 ( A10 12 22 CE# (E DQ7 14 ...
Page 5
... LOGIC SYMBOL 32-Pin TSOP—Standard Pinout 32-Pin TSOP—Reverse Pinout 17 8 A0–A16 DQ0–DQ7 # # Am28F010A OE# 32 A10 31 CE VSS A11 ...
Page 6
... AM28F010A -70 J DEVICE NUMBER/DESCRIPTION Am28F010A 1 Megabit (128 K x 8-Bit) CMOS Flash Memory with Embedded Algorithms Valid Combinations AM28F010A-70 AM28F010A-90 AM28F010A-120 AM28F010A-150 AM28F010A-200 OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In Contact an AMD representative for more information. TEMPERATURE RANGE C = Commercial (0° ...
Page 7
... The tar- get address is latched on the falling edge of the Write Enable pulse and the appropriate data is latched on the rising edge of the pulse. Write Enable high inhibits writ- ing to the device. Am28F010A must be at high voltage in 7 ...
Page 8
... WE# must be a logical zero while OE logical one. Power-Up Write Inhibit Power-up of the device with WE will not accept commands on the rising IH edge of WE#. The internal state machine is automati- cally reset to the read mode on power-up. Am28F010A CC power- The user must ensure LKO , IL and ...
Page 9
... FUNCTIONAL DESCRIPTION Description Of User Modes Table 1. Am28F010A Device Bus Operations (Notes 7 and 8) Operation Read Standby Output Disable Read-Only Auto-select Manufacturer Code (Note 2) Auto-select Device Code (Note 2) Read Standby (Note 5) Read/Write Output Disable Write Legend Don’t care, where Don’t Care is either < ...
Page 10
... For the device the two bytes are given in the table 2 of the device data sheet. All identifiers for manufac- turer and device codes will exhibit odd parity with the MSB (DQ7) defined as the parity bit. Table 2. Am28F010A Auto Select Code ...
Page 11
... In order to write, OE# must and CE# and WE# IH must any pin is not in the correct state a write IL command will not be executed. Table 3. Am28F010A Command Definitions Operation Command (Note 1) Read Memory (Note 4) Write Read Auto select Write Embedded Erase Set-up/ ...
Page 12
... Ramp Data = 30h Data = 30h # Data Polling to Verify Erasure Compare Output to FFh Available for Read Operations parameters. The V power supply can be hard-wired to the device may be ground, no connect with a resistor tied to ground, or less than V Am28F010A 16778D-6 Comments (see Note) PPH + 2.0 V. Refer CC ...
Page 13
... Ramp Data = 10h or 50h Valid Address/Data # Data Polling to Verify Completion Available for Read Operations parameters. The V power supply can be hard-wired to the device may be ground, no connect with a resistor tied to ground, or less than V Am28F010A 16778D-7 Comments (see Note) PPH + 2.0 V. Refer CC 13 ...
Page 14
... Toggle Bit. START Read Byte (DQ0–DQ7) Addr = VA Yes DQ7 = Data ? No No DQ5 = 1 ? Yes Read Byte (DQ0–DQ7) Addr = VA Yes DQ7 = Data ? No Fail Pass Figure 3. Data Polling Algorithm # Am28F010A VA = Byte address for programming = XXXXh during chip erase 16778D-8 ...
Page 15
... DQ0–DQ6 *DQ7 = Valid Data (The device has completed the Embedded operation.) Figure 4. AC Waveforms for Data DQ7# Valid Data t WHWH DQ0–DQ6 = Invalid Polling during Embedded Algorithm Operations # Am28F010A High Z DQ7 = DQ0–DQ7 Valid Data 16778D-9 15 ...
Page 16
... See Figures 5 and 6 for the Toggle Bit timing specifica- tions and diagrams. START VA = Byte address for programming Read Byte (DQ0–DQ7) Addr = VA No DQ6 = Toggle ? Yes No DQ5 = 1 ? Yes Read Byte (DQ0–DQ7) Addr = VA No DQ6 = Toggle ? Yes Fail Pass Figure 5. Toggle Bit Algorithm Am28F010A = XXXXh during chip erase 16778D-10 ...
Page 17
... The second Reset command safely aborts the programming operation and resets the device to the Read mode. Memory contents are not altered in any case. Am28F010A DQ6 DQ0–DQ7 Valid 16778D-11 ...
Page 18
... A read cycle from address 0001h returns the device code (see the Auto Select Code table of the corresponding device data sheet). To terminate the op- eration necessary to write another valid command, such as Reset (00h or FFh), into the register. Am28F010A ...
Page 19
... Read . . . . . . . . . . . . . . . . . . . . . . . . –0 +12 Program, Erase, and Verify . . . . . . +11 +12.6 V +2.0 V for periods Operating ranges define those limits between which the CC functionality of the device is guaranteed. is –0 may overshoot PP Am28F010A ) . . . . . . . . . . .0°C to +70° .–40°C to +85° .–55°C to +125° ...
Page 20
... MAXIMUM OVERSHOOT +0.8 V –0.5 V – 2.0 V 14 Maximum Negative Input Overshoot Maximum Positive Input Overshoot Maximum V Overshoot PP Am28F010A 16778D-12 16778D-13 16778D-14 ...
Page 21
... PP V PPH Operations V Low V Lock-out Voltage LKO CC Notes: 1. Caution: The Am28F010A must not be removed from (or inserted into) a socket when V volt, the voltage difference between V and fall time specification of 500 ns minimum tested with simulate open outputs. CC1 IH 3. Maximum active power usage is the sum ...
Page 22
... Read/Write PP V PPH Operations V Low V Lock-out Voltage LKO CC Notes: 1. Caution: The Am28F010A must not be removed from (or inserted into) a socket when V the voltage difference between V PP time specification of 500 ns minimum tested with simulate open outputs. CC1 IH 3. Maximum active power usage is the sum ...
Page 23
... Figure 7. Am28F010A—Average I TEST CONDITIONS Device Under Test C L 6.2 k Note: Diodes are IN3064 or equivalent Figure 8. Test Setup Frequency in MHz Active vs. Frequency 5.5 V, Addressing Pattern = Minmax CC Data Pattern = Checkerboard 5.0 V Test Condition 2.7 k Output Load Output Load Capacitance, C ...
Page 24
... V for a logic “0”. Input pulse rise and fall times are 10 ns. -70 Min 70 Max 70 Max 70 Max 35 Min 0 Max 20 Min 0 Max Min 0 Min 50 Am28F010A Test Points 1.5 V Input Output 16778D-17 Am28F010A Speed Options -90 -120 -150 -200 90 120 150 200 90 120 150 200 90 120 150 200 ...
Page 25
... Embedded Erase operation of 5 sec consists of 4 sec array pre-programming time and one sec array erase time. This is a typical time for one embedded erase operation. 4. Not 100% tested. Am28F010A Speed Options -70 -90 Min ...
Page 26
... Center Line is High Impedance State (High Z) Data Outputs Valid Enabled Addresses Stable AVAV GLQV ELQV CE t AXQX GLQX OLZ ELQX LZ Output Valid AVQV ACC Am28F010A OUTPUTS Changing, State Unknown Standby, Power-down t EHQZ ( GHQZ ( High Z 16778D-18 ...
Page 27
... PP t VPEL Note: # DQ7 is the complement of the data written to the device. Figure 10. AC Waveforms for Embedded Erase Operation Embedded # Data Polling Erase Erase WHWH3 WPH 30h DQ7 Am28F010A Read Standby DQ7 16778D-19 27 ...
Page 28
... D is the data written to the device. OUT Figure 11. AC Waveforms for Embedded Programming Operation 28 Embedded # Program Data Polling WHWH3 DQ7# DQ7 IN Am28F010A Read OUT 16778D-20 ...
Page 29
... Embedded erase operation of 5 sec consists of 4 sec array pre-programming time and one sec array erase time. This is a typical time for one embedded erase operation. 4. Not 100% tested. Am28F010A Speed Options -70 Min 70 ...
Page 30
... D is the data written to the device. OUT Figure 12. AC Waveforms for Embedded Programming Operation Using CE# Controlled Writes 30 Embedded Program CPH t EHEH3 50h Am28F010A # Data Polling PA # DQ7 DQ7 D OUT 16778D-21 ...
Page 31
... Cycles 14 µ (Note 3) Parameter = 5.0 V, one pin at a time. CC Test Conditions OUT 25° 1.0 MHz. A Test Conditions 150 C 125 C Am28F010A Comments Min Max ) –1 –1 1 –100 mA +100 mA Typ Max Unit Min Unit ...
Page 32
... SEATING PLANE .015 .016 .060 .022 .009 .015 .125 .140 .080 .095 SEATING PLANE .013 .021 .050 REF. Am28F010A .600 .625 .009 .015 .630 .700 0 10 16-038-S_AG PD 032 EC75 5-28-97 lv .042 .056 .400 REF. .490 .530 16-038FPO-5 PL 032 DA79 ...
Page 33
... PHYSICAL DIMENSIONS TS032—32-Pin Standard Thin Small Outline Package (measured in millimeters) Pin 1 I.D. 1 1.20 MAX 33 18.30 18.50 19.80 20. Am28F010A 0.95 1.05 7.90 8.10 0.50 BSC 0.05 0.15 0.08 16-038-TSOP-2 0.20 TS 032 DA95 0.10 3-25-97 lv 0.21 0.50 0.70 ...
Page 34
... PHYSICAL DIMENSIONS TSR032—32-Pin Reversed Thin Small Outline Package (measured in millimeters) Pin 1 I.D. 1 1.20 MAX 18.30 18.50 19.80 20. 0.50 0.70 Am28F010A 0.95 1.05 7.90 8.10 0.50 BSC 0.05 0.15 16-038-TSOP-2 0.08 TSR032 0.20 DA95 0.10 3-25-97 lv 0.21 34 ...
Page 35
... MODE section for programming the Flash memory de- vice in-system).” Revision D+2 General Description Embedded Program: Changed “The typical room tem- perature programming time of this device is four sec- onds.” to “The typical room temperature programming time of this device is two seconds.” Am28F010A ...