CDP1805ACE Intersil Corporation, CDP1805ACE Datasheet
CDP1805ACE
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CDP1805ACE Summary of contents
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... Pin Compatible With CDP1802 Except for Terminal 16 • 64K-Byte Memory Address Capability • 64 Bytes of On-Chip RAM † • Matrix of On-Board Registers • On-Chip Crystal or RC Controlled Oscillator • 8-Bit Counter/Timer n Ordering Information CDP1805AC CDP1806AC CDP1805ACE CDP1806ACE - CDP1806ACEX CDP1805ACQ CDP1806ACQ CDP1805ACD CDP1806ACD CDP1805ACDX - † CDP1805AC Only CAUTION: These devices are sensitive to electrostatic discharge ...
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Pinouts CDP1805AC, CDP1806AC (PDIP, SBDIP) TOP VIEW CLOCK 1 WAIT 2 CLEAR SC1 5 SC0 6 MRD 7 BUS 7 8 BUS 6 9 BUS 5 10 BUS 4 11 BUS 3 12 BUS 2 13 BUS ...
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CDP1805AC, CDP1806AC FIGURE 2. BLOCK DIAGRAM FOR CDP1805AC AND CDP1806AC 3 ...
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... +125 + .- +150 STG 0.79mm) from case for CDP1805ACD, CDP1805ACE CDP1806ACD, CDP1806ACE MIN MAX 0.625 CDP1805ACD, CDP1805ACE CDP1806ACD, CDP1806ACE V (NOTE 3) DD (V) MIN TYP MAX 200 5 1 0 -0 ...
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... 2 50pF - 50pF; Input -0.1V 5V, 5 PLH PHL , t PHL , t PHL 5 CDP1805ACD, CDP1805ACE CDP1806ACD, CDP1806ACE V (NOTE 3) DD (V) MIN TYP MAX 1 2.2 2.9 3.6 5 0.9 1.9 2.8 5 0.3 0 ...
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Dynamic Electrical Specifications PARAMETER Minimum Set-Up And Hold Times (Note 2) Data Bus Input Set-Up Data Bus Input Hold DMA Set-Up DMA Hold Set-Up Hold Interrupt ...
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Timing Waveforms For Possible Operating Modes INTERNAL RAM READ CYCLE CLOCK 01 11 TPA TPB MEMORY HIGH BYTE ADDRESS MRD MWR †ME IN VALID DATA FROM MEMORY ...
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W CLOCK 00 01 TPA TPB ...
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Enhanced CDP1805AC and CDP1806AC Operation Timing Timing for the CDP1805AC and CDP1806AC is the same as the CDP1802 microprocessor series, with the following exceptions: • 4.5 Clock Cycles Are Provided for Memory Access Instead of 5. • Q Changes 1/2 ...
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MA0 to MA7 (8 Memory Address Lines) In each cycle, the higher-order byte of a 16-bit memory address appears on the memory address lines MA0-7 first. Those bits required by the memory system can be strobed into external address latches ...
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The X designator selects one of the 16 registers R(X) to “point” to the memory for an operand (or data) in certain ALU or I/O operations. The N designator can perform the following five functions depending on the type of ...
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Interrupt Servicing Register R(1) is always used as the program counter when- ever interrupt servicing is initialized. When an interrupt request occurs and the interrupt is allowed by the program (again, nothing takes place until the completion of the cur- ...
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RET MASTER S Q INTERRUPT RESET ENABLE (MIE) DIS CIE COUNTER S INTERRUPT ENABLE RESET FF CID R Q (CIE) EXTERNAL XIE S Q INTERRUPT ENABLE RESET FF R XID (XIE) FIGURE 6. INTERRUPT LOGIC CONTROL DIAGRAM ...
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STPC R TPA 32 SPMI EF1 SCMI EF2 SPM2 SCM2 DTC GEC Because of the Schmitt Trigger input oscillator can be used as shown in Figure 9. The frequency is approxi- mately 1/RC (see Figure 10 ...
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The function of the modes are defined as follows: Reset The levels on the CDP1805A and CDP1806A external signal lines will asynchronously be forced by RESET to the follow- ing states SC1, SC0 = 0,1 MRD = ...
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State Transitions The CDP1805A and CDP1806A state transitions are shown in Figure 13. Each machine cycle requires the same period of time, 8 clock pulses, except the initialization cycle (INlT) ENTER RESUME PAUSE RUN PAUSE CLOCK ...
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Instruction Set The CDP1805AC and CDP1806AC instruction summary is given in Table 1. Hexadecimal notation is used to refer to the 4-bit binary codes. In all registers, bits are numbered from the least significant bit (LSB) to the most significant ...
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TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) NO. OF MACHINE INSTRUCTION CYCLES AND IMMEDIATE SHIFT RIGHT SHIFT RIGHT WITH CARRY RING SHIFT RIGHT SHIFT LEFT SHIFT LEFT WITH CARRY RING SHIFT LEFT ARITHMETIC OPERATIONS (Note 3) ADD DECIMAL ADD ADD ...
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TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) NO. OF MACHINE INSTRUCTION CYCLES DECIMAL SUBTRACT MEMORY WITH BORROW, IMMEDIATE BRANCH INSTRUCTIONS - SHORT BRANCH SHORT BRANCH NO SHORT BRANCH (See SKP) SHORT BRANCH SHORT BRANCH IF D ...
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TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) NO. OF MACHINE INSTRUCTION CYCLES BRANCH INSTRUCTIONS - LONG BRANCH LONG BRANCH NO LONG BRANCH (See LSKP) LONG BRANCH LONG BRANCH IF D NOT 0 LONG BRANCH IF DF ...
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TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) NO. OF MACHINE INSTRUCTION CYCLES SET Q RESET Q PUSH STACK TIMER/COUNTER INSTRUCTIONS LOAD COUNTER GET COUNTER STOP COUNTER DECREMENT TIMER/COUNTER SET TIMER MODE AND START SET COUNTER MODE 1 ...
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TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) MACHINE INSTRUCTION CYCLES OUTPUT 6 OUTPUT 7 INPUT 1 INPUT 2 INPUT 3 INPUT 4 INPUT 5 INPUT 6 INPUT 7 CALL AND RETURN STANDARD CALL STANDARD RETURN NOTES: 10. Previous contents of ...
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The short-branch instructions are two or three bytes long. The first byte specifies the condition to be tested, and the second specifies the branching address, except for the branches on interrupt. For those, the first two bytes specify the ...
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TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES STATE I N MNEMONIC S1 RESET S1 INITIALIZE, NOT PROGRAMMER AC- CESSIBLE S0 FETCH IDL S1 0 1-F LDN S1 1 0-F INC ...
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TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued) STATE I N MNEMONIC INP INP RET DIS ...
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TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued) STATE I N MNEMONIC # LONG SKIP S1 LONG SKIP S1 LONG SKIP # LONG SKIP S1#1 ...
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TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued) STATE I N MNEMONIC SPM2 SCM2 SPM1 SCM1 LDC S1 ...
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TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued) STATE I N MNEMONIC # DSBI S1#1 8 0-F SCAL #2 8 0-F SCAL #3 8 0-F SCAL #4 8 0-F SCAL #5 ...
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IDL BDF IRX OUT 7 RET DIS LDXA STXD ADC LBR LBQ LBZ LBDF NOP LDX OR AND ...
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