CDP1851E Intersil Corporation, CDP1851E Datasheet
CDP1851E
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CDP1851E Summary of contents
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... NO. 8-bit bus for both transmitting and receiving data. Handshaking signals are provided to maintain proper bus access control. CDP1851E E40.6 Port A handshaking lines are used for input control and port B handshaking lines are used for output; therefore port B must be - E40.6 in the bit-programmable mode where handshaking is not used ...
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Absolute Maximum Ratings DC Supply-Voltage Range (Voltage Referenced to V Terminal) SS CDP1851 . . . . . . . . . . . . . . . . . . . . . . . . ...
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Static Electrical Specifications PARAMETER Quiescent Device Current I DD Output Low Drive I OL (Sink) Current Output High Drive I OH (Source) Current Output Voltage Low-Level V OL (Note 2) Output Voltage High Level V OH (Note 2) Input Low ...
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In either case the proper code must be asserted on the RAO, RA1, and CS lines to read the buffer register (see Table 6). The INT ...
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Programming Initialization and Controls The CDP1851 PlO must be cleared by a low on the CLEAR input during power-on to set it for programming. Once programmed, modes can be changed without clearing except when exiting the bit-programmable mode. A low ...
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MODE SET 7 Input 0 Output 0 Bit-Programmable 1 Bidirectional 1 NOTE: 1. Modes should be set in order as shown in Table 1. If either port is set for bit-programmable mode, the two following control bytes should ...
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INTERRUPT CONTROL Interrupt Enable/Disable NOTES: 1. INT Enable = 1, INT Enabled = 0, INT Disabled 2. A Port Port B Status Register NOTES: 1. All Modes (D0) B INT status (1 means set) (D1) ...
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Function Pin Definition CLOCK (Input): Positive input pulse that latches READ and CS on its trailing edge CHIP SELECT (Input) A high-level voltage at this input selects the CDP1851 PlO. RA0 - REGISTER ADDRESS 0 (Input): This input ...
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CDP1851, CDP1851C TPA MRD TPB V CDP1802 DD 10k INT BUS 0-7 FIGURE 4. I/O SPACE I/O A RDY RA0 B RDY RA1 A STROBE CS CLOCK B STROBE RD/WE WR/RE PORT TPB CDP1851 ...
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Dynamic Electrical Specifications PARAMETER INPUT MODE SEE FIGURES 4 AND 5 Minimum Setup Times: Chip Select to CLOCK t CSCL RD/WE to CLOCK t RWCL WR/RE to CLOCK t WRCL Data in to STROBE t DlST Minimum Hold Times: Chip ...
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Test Circuit and Waveforms INT 1k B INT 50pF CDP1851 FIGURE 5. INTERRUPT SIGNAL PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORMS RDY INT STROBE DATA-IN TPB CLOCK = (TPA) CS WR/RE = (MRD) MEMORY SPACE RD/WE ...
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Dynamic Electrical Specifications PARAMETERS OUTPUT MODE SEE FIGURES 4 AND 6 Minimum Setup Times: Chip Select to CLOCK t CSCL RD/WE to CLOCK t RWCL WR/RE to CLOCK t WRCL Address to WRITE (Note Data Bus to ...
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Dynamic Electrical Specifications PARAMETERS Minimum Pulse Widths: CLOCK t WCL STROBE t WST WRITE (Note 3) t NOTES Typical values are for and nominal voltages Maximum limits of minimum characteristics are the ...
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... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...