HSP43168VC-45 Intersil Corporation, HSP43168VC-45 Datasheet
HSP43168VC-45
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HSP43168VC-45 Summary of contents
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... Ordering Information PART NUMBER PART MARKING HSP43168VC-45 HSP43168VC-45 HSP43168VC-45Z (Note) HSP43168VC-45Z HSP43168JC-33 HSP43168JC-33 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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Block Diagram CIN0 - CSEL0 - 4 10 INA0 - 9 10 INB0 - 9/ OUT0 - 8 OEL OEH Pinouts CIN 7 CIN 6 CIN 5 CIN 4 GND CIN 3 CIN 2 CIN 1 ...
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Pinouts (Continued) CIN8 NC CIN7 NC CIN6 CIN5 CIN4 GND GND CIN3 CIN2 CIN1 CIN0 INA9 INA8 INA7 INA6 INA5 INA4 INA3 INA2 INA1 INA0 NC NC INB9 INB8 INB7 3 HSP43168 HSP43168 100 LD MQFP ...
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Pin Description SYMBOL TYPE +5V power supply pin GND Ground. CIN0-9 I Control/Coefficient Data Bus. Processor interface for loading control data and coefficients. CIN0 is the LSB. A0-8 I Control/Coefficient Address Bus. Processor interface for ...
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TXFR DELAY 4 DELAY 3 FIR A REVERSE PATH DECIMATION REGISTERS FIR A FORWARD PATH DELAY 1-16 †† SHFTEN DELAY 3 10 DELAY INA0-9 DELAY 3 †† 1-16 M DELAY 3 U INB0 INB1- ...
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Functional Description As shown in Figure 1, the HSP43168 consists of two 4-multiplier FIR filter cells which process 10-bit data and coefficients. The FIR cells can operate as two independent 8-tap FIR filters or two 4-tap asymmetric filters at maximum ...
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TABLE 1. CONFIGURATION/CONTROL WORD 0 BIT DEFINITIONS CONTROL ADDRESS 000H BITS FUNCTION 3-0 Decimation Factor ( 0000 = No Decimation. 1111 = Decimation by 16. 4 Mode Select 0 = Single Filter Mode ...
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The MUX/DEMUX structure at the input to the Feedback Circuitry routes data to the LIFOs or the delay stage depending on the selected configuration. The MUX on the Feedback Circuitry Output selects which storage element ...
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Coefficient sets may be switched every clock to support polyphase filtering operations. The coefficients are loaded into On-Board Registers using the microprocessor interface, CIN0-9, A0-8, and WR. Each multiplier within the FIR Cells is driven by a coefficient bank with ...
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Input/Output Formats The Dual FIR supports mixed mode arithmetic with both unsigned and two's complement data and coefficients. The input and output formats for both data types are shown below. If the Dual FIR is configured as an even symmetric ...
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Register 001H, bit 4, is filter configuration unique. Table 7 details the configuration control register values, the number of filter coefficient banks required and the MUX1-0 control values for each filter example. TABLE 7. CONFIGURATION CONTROL ...
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(X8 + X1)C0 + (X7 + X2)C1 + (X6+X3)C2 + (X5 + X4)C3 FIGURE 7B. DATA FLOW AS DATA SAMPLE 8 IS CLOCKED INTO THE FEED FORWARD ...
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C3/2 + (X8+X2)C0+(X7+X3)C1+(X6+X4)C2+(X5+X5)C3/2 FIGURE 10C. DATA FLOW AS DATA SAMPLE 8 IS CLOCKED INTO THE FEED FORWARD STAGE FIGURE 10. DATA FLOW DIAGRAMS FOR 7-TAP SYMMETRIC FILTER In ...
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ACCUMULATOR (X0)C0+(X1)C1+(X2)C2+(X3)C3 FIGURE 13A. DATA SHIFTING DISABLED, BACKWARD SHIFTING DECIMATION REGISTERS FEEDING MULTIPLIERS ACCUMULATOR (X1)C0+(X2)C1+(X3)C2+(X4)C3 FIGURE 13C. DATA SHIFTING DISABLED, BACKWARD SHIFTING DECIMATION REGISTERS FEEDING MULTIPLIERS ...
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CLK INA0 CSEL0 ACCEN FWRD RVRS SHFTEN (TIED LOW) TXFR †Note that CLK is 2X data rate. FIGURE 14. CONTROL TIMING FOR 8-TAP ASYMMETRIC FILTER Example 4. Even-Tap ...
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ACCUMULATOR (X2 + X21)C2 + (X5 + X18)C5 + (X8 + X15)C8 + (X11 + X12)C11 FIGURE 17A. COMPUTATIONAL ...
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As in the 24-tap example, an output is required every third CLK which allows 3 CLKs for computation. On each CLK, one of three sets of coefficients are used to calculate the filter taps. Since this is an odd length ...
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C11 C10 C10 h( x( ...
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D11 D10 D10 h2( B( ...
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ACCUMULATOR (X1 + X23)D0 + (X4 + X20)D3 + (X7 + X17)D6 + (X14 + X10)D9 + (X2 + ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC Electrical Specifications V PARAMETER CLK Period CLK High CLK Low WR Period WR High WR Low Setup Time A0 Going Low Hold Time A0-8 from WR Going High Setup Time CIN0 Going High Hold Time ...
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Waveforms CLK CSEL0 - 4, MUX0 - 1 SHFTEN, FWRD RVRS, TXFR INA0 - 9, INB0 - 9, ACCEN OUT0 - CIN0 - 9 OEL, OEH OUT0 - 27 23 HSP43168 ...
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Metric Plastic Quad Flatpack Packages (MQFP -D- - PIN 1 - -16 0.40 0.20 0.016 MIN 0.008 o 0 MIN 0.13/0.17 0.005/0.007 -16 L ...
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... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...