CY7C1351-40AC Cypress Semiconductor Corporation., CY7C1351-40AC Datasheet
CY7C1351-40AC
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CY7C1351-40AC Summary of contents
Page 1
... The CY7C1351 is a 3.3V, 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to en- able consecutive Read/Write operations with data being trans- ferred on every clock cycle ...
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... V 20 DDQ DDQ 100-Pin TQFP CY7C1351 2 CY7C1351 DDQ DDQ ...
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... When left floating MODE will default HIGH inter- leaved burst order. Power supply inputs to the core of the device. Should be connected to 3.3V power supply. Power supply for the I/O circuitry. Should be connected to a 3.3V power supply. Ground for the device. Should be connected to ground of the system. 3 CY7C1351 controls DQ and DP , BWS 0 [7:0] 0 ...
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... Because the CY7C1351 is a common I/O device, Data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before present- ing data to the DQ three-state the output drivers safety precaution, DQ and DP ...
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... X L Valid L signifies at least one Byte Write Select is active, BWS x 5 CY7C1351 Comments I/Os three-state following next recognized clock. Clock ignored, all operations suspended. Address latched. Address latched, data presented two valid clocks later. Burst Read operation. Previous access was a Read operation. Ad- ...
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... BWS CY7C1351 Third Fourth Address Address Ax+1, Ax Ax+ BWS BWS BWS ...
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... > V – 0.3V DDQ f =0 Max Device Deselected, or 15-ns cycle, 66 MHz –0. DDQ 20-ns cycle, 50 MHz 1/t MAX CYC 25-ns cycle, 40 MHz 7 CY7C1351 Ambient [8] Temperature DDQ 0°C to 70°C 3.3V 5% Min. Max. Unit 3.135 3.465 V 3.135 3.465 V 2.4 V 0 ...
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... Tested initially and after any design or process change that may affect these parameters. Test Conditions MHz 3. 3.3V DDQ R=317 3.3V OUTPUT 5 pF R=351 GND INCLUDING JIG AND 1351-2 SCOPE (b) Test Conditions Symbol 8 CY7C1351 Max. Unit ALL INPUT PULSES 3.0V 1351-3 TQFP Typ. Units Notes ...
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... This parameter is sampled and not 100% tested. [11, 12, 13] –66 Min. Max. 15.0 5.0 5.0 2.0 0.5 11.0 1.5 2.0 0.5 2.0 0.5 2.0 0.5 1.7 0.5 2.0 0.5 3.0 [10, 12, 13, 14] [10, 12, 13, 14] 0 [12] is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ 9 CY7C1351 –50 –40 Min. Max. Min. Max. 20.0 25.0 6.0 7.0 6.0 7.0 2.0 2.5 1.0 1.0 12.0 14.0 1.5 1.5 2.0 2.5 1.0 1.0 2.0 2.5 1.0 1.0 2.0 2.5 1.0 1.0 2.0 2.5 1 ...
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... CL CH CYC WA5 RA4 RA6 t DOH t CHZ Out In Out to define a write cycle (see Write Cycle Description table and CE . All chip selects need to be active in order to select 3 = UNDEFINED = DON’T CARE 10 CY7C1351 t t CENH CENS RA7 t CHZ Q6 Q7 Out Out ...
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... AH AS WA2 CHZ DH Q1+2 Q1+3 D2 D2+1 Out Out defines a write cycle (see Write Cycle Description table). , and CE . All chip enables need to be active in order to select UNDEFINED = DON’T CARE 11 CY7C1351 RA3 t CLZ Q3 D2+2 D2+3 Out input signals. [3:0] Q3+1 Out ...
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... Switching Waveforms (continued) OE Timing Ordering Information Speed (MHz) Ordering Code 66 CY7C1351-66AC 50 CY7C1351-50AC 40 CY7C1351-40AC Document #: 38-00691 EOHZ Three-state I/Os t EOLZ Package Name Package Type A101 100-Lead 1.4 mm Thin Quad Flat Pack A101 100-Lead 1.4 mm Thin Quad Flat Pack A101 100-Lead 1.4 mm Thin Quad Flat Pack ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1351 51-85050-A ...