MC145191F Freescale Semiconductor, Inc, MC145191F Datasheet

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MC145191F

Manufacturer Part Number
MC145191F
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Part Number:
MC145191F
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1.1 GHz PLL Frequency
Synthesizer
Includes On–Board 64/65 Prescaler
of direct usage up to 1.1 GHz. A special architecture makes this PLL very easy
to program because a byte–oriented format is utilized. Due to the patented
BitGrabber
of the three registers. Thus, tuning can be accomplished via a 3–byte serial
transfer to the 24–bit A register. The interface is both SPI and MICROWIRE
compatible.
output and a double–ended phase detector output. Both phase detectors have
linear transfer functions (no dead zones). The maximum current of the
single–ended phase detector output is determined by an external resistor tied
from the Rx pin to ground. This current can be varied via the serial port.
ply systems of 5 V 10%.
single–ended mode. Also featured are on–board support of an external crystal
and a programmable reference output. The R, A, and N counters are fully
programmable. The C register (configuration register) allows the part to be
configured to meet various applications. A patented feature allows the C
register to shut off unused outputs, thereby minimizing system noise and
interference.
loaded into the counters, on–board circuitry synchronizes the update of the A
register if the A or N counters are loading. Similarly, an update of the R register
is synchronized if the R counter is loading.
the three counters (R, A, and N) simultaneously.
BitGrabber is a trademark of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp.
REV 1
12/99
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
The MC145191 is a single–package synthesizer with serial interface capable
The device features a single–ended current source/sink phase detector
The MC145191 has phase/frequency detectors optimized for single–sup-
The part includes a differential RF input which may be operated in a
In order to have consistent lock times and prevent erroneous data from being
The double–buffered R register allows new divide ratios to be presented to
Motorola, Inc. 1999
Maximum Operating Frequency: 1100 MHz @ V in = 200 mV p–p
Operating Supply Current: 7 mA Nominal
Operating Supply Voltage Range (V DD and V CC Pins): 4.5 to 5.5 V
Operating Supply Voltage Range of Phase Detectors (V PD Pin):
4.5 to 5.5 V
Current Source/Sink Phase Detector OUTPUT Capability: 2 mA Maximum
Gain of Current Source/Sink Phase/Frequency Detector Controllable via
Serial Port
Operating Temperature Range: – 40 to + 85 C
R Counter Division Range: (1 and) 5 to 8191
Dual–Modulus Capability Provides Total Division up to 262,143
High–Speed Serial Interface: 4 Mbps
OUTPUT A Pin, When Configured as Data Out, Permits Cascading of Devices
Two General–Purpose Digital Outputs — OUTPUT A: Totem–Pole (Push–Pull)
Patented Power–Saving Standby Feature with Orderly Recovery for
Minimizing Lock Times, Standby Current: 30 A
Evaluation Kit Available (Part Number MC145191EVK)
See Application Note AN1253/D for Low–Pass Filter Design, and
AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping
registers, no address/steering bits are required for random access
NOT RECOMMENDED FOR NEW DESIGN
Consider MC145193 for New Designs.
DEVICES TO BE PHASED OUT.
OUTPUT B: Open–Drain
20
20
MC145191F
MC145191DT
ORDERING INFORMATION
REF out
TEST 1
PD out
MC145191
GND
V PD
LD
Rx
f in
PIN ASSIGNMENT
R
V
1
1
1
2
3
4
5
6
7
8
9
10
SOG Package
TSSOP
Order this document
20
19
18
17
16
15
14
13
12
11
SOG PACKAGE
CASE 948D
DT SUFFIX
CASE 751J
by MC145191/D
F SUFFIX
TSSOP
REF in
D in
CLK
ENB
OUTPUT A
OUTPUT B
V DD
TEST 2
V CC
f in
MC145191
1

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MC145191F Summary of contents

Page 1

... Motorola, Inc. 1999 SOLUTIONS DEVICE DATA OUTPUT B: Open–Drain Order this document by MC145191/D MC145191 F SUFFIX SOG PACKAGE 20 CASE 751J 1 DT SUFFIX TSSOP 20 CASE 948D 1 ORDERING INFORMATION MC145191F SOG Package MC145191DT TSSOP PIN ASSIGNMENT REF out 1 20 REF CLK ...

Page 2

REF in OSC OR 4–STAGE DIVIDER 1 (CONFIGURABLE) REF out 18 CLK SHIFT REGISTER 19 AND D in CONTROL 24 LOGIC 17 ENB INTERNAL CONTROL INPUT 10 AMP f in SUPPLY CONNECTIONS: PIN 12 = ...

Page 3

ELECTRICAL CHARACTERISTICS ( 4.5 to 5.5 V, Voltages Referenced to GND – unless otherwise stated 4.5 to 5.5 V with ...

Page 4

ANALOG CHARACTERISTICS—CURRENT SOURCE/SINK OUTPUT—PD out (I out 2 mA 4 Parameter Maximum Source Current Variation (Part–to–Part) Maximum Sink–vs–Source Mismatch (Note 3) Output Voltage Range (Note 3) NOTES: 1. Percentages ...

Page 5

CLK 50% 10 1/f clk t PLH t PHL 90% OUTPUT A 50% (DATA OUT) 10% t TLH t THL Figure 1. VALID 50 50% ...

Page 6

LOOP SPECIFICATIONS ( 4.5 to 5.5 V unless otherwise indicated – Symbol Parameter V in Input Voltage Range ref Input Frequency Range, REF in ...

Page 7

NORMALIZED INPUT IMPEDANCE — SERIES FORMAT ( (PIN 11) SOG PACKAGE Frequency Marker (MHz 1100 MOTOROLA WIRELESS SEMICONDUCTOR SOLUTIONS DEVICE DATA (100 MHz to 1.1 GHz Resistance ...

Page 8

START 50 MHz START 50 MHz Marker MC145191 8 RETURN LOSS STOP 1500 MHz STANDING WAVE RATIO ...

Page 9

PIN DESCRIPTIONS DIGITAL INTERFACE PINS D in Serial Data Input (Pin 19) The bit stream begins with the most significant bit (MSB) and is shifted in on the low–to–high transition of CLK. The bit pattern is 1 byte (8 bits) ...

Page 10

A counter, and N counter. The divide ratio between the f in in- put and the f V signal the divide ratio of the N counter and A is the divide ratio of ...

Page 11

C4 = high). The PD out circuit is powered The phase detec- tor gain is controllable by bits C3, C2, and C1: gain (in amps ...

Page 12

ENB CLK NOTE: It may not be convenient to control the ENB or CLK pins during power up per the Pin Descriptions. If this is the case, the part may be initialized through ...

Page 13

Nominal MC145191 PD out Source ...

Page 14

ENB 1 CLK MSB this point, the new byte is transferred to the C register and stored. No other registers are affected. C7 — POL: Selects the output polarity of the phase/frequency detectors. When set ...

Page 15

ARCHIVE INFORMATION ENB CLK MSB D in A23 A22 A21 A20 A19 A18 A17 1 1 BOTH BITS MUST BE HIGH PORT out ...

Page 16

ENB CLK MSB R15 R14 R13 R12 R11 CRYSTAL MODE, SHUT DOWN 1 CRYSTAL MODE, ACTIVE 2 REFERENCE MODE, REF in ENABLED and REF out STATIC LOW 3 REFERENCE MODE, REF out ...

Page 17

R REFERENCE REF FEEDBACK out High voltage level Low voltage level *At this point, when both f R and ...

Page 18

OUTPUT function of supply voltage. (REF out is not used because loading impacts the oscillator.) The frequency should increase very slightly as the dc supply voltage is increased. An overdriven crystal decreases ...

Page 19

PHASE–LOCKED LOOP—LOW PASS FILTER DESIGN (A) PD out VCO R C NOTE: For (A), using K in amps per radian with the filter’s impedance transfer function, Z(s), maintains units of volts per radian for the detector/ filter combination. Additional sideband ...

Page 20

THRESHOLD DETECTOR INTEGRATOR OPTIONAL LOOP ERROR SIGNALS (NOTE LOW–PASS FILTER 1000 pF NOTES: 1. When used, the R and V outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter Design page ...

Page 21

ARCHIVE INFORMATION ENB CLK REGISTER BITS OF DEVICE #2 *At this point, the new bytes are transferred to the C registers of both devices and stored. No other ...

Page 22

ARCHIVE INFORMATION ENB CLK X R15 R14 REGISTER BITS OF DEVICE #2 IN FIGURE 23 NOTES APPLICABLE TO EACH DEVICE this point, bits R13, R14, and R15 are ...

Page 23

SOG (SMALL OUTLINE GULL–WING) PACKAGE - - 0.13 (0.005 0.13 (0.005 TSSOP (THIN SHRUNK SMALL OUTLINE PACKAGE ...

Page 24

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of ...

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