MC145532L Freescale Semiconductor, Inc, MC145532L Datasheet
MC145532L
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MC145532L Summary of contents
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... S REG REG PROCESSOR Order this document by MC145532/D MC145532 DW SUFFIX SOG PACKAGE 16 CASE 751G 1 L SUFFIX CERAMIC PACKAGE 16 CASE 620 1 ORDERING INFORMATION MC145532DW SOG Package MC145532L Ceramic Package PIN ASSIGNMENT MODE DDO 2 15 EDO DOE 3 14 EOE DDC 4 13 EDC ...
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DEVICE DESCRIPTION An Adaptive Differential PCM (ADPCM) transcoder is used to reduce the data rate required to transmit a PCM encoded voice signal while maintaining the voice fidelity and intelli- gibility of the PCM signal. The transcoder is used on ...
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APD Absolute Power Down (Pin 9) A logic 1 applied to this input forces the transcoder into a power saving mode. This pin has a CMOS compatible input. POWER SUPPLY V DD Positive Power Supply (Pin 16) The most positive ...
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DECODER OUTPUT — SHORT FRAME Figure 7 shows the timing of the decoder output in short frame mode. The DDO will provide the 8–bit PCM word for the decoding rate that was selected for this frame of data on the ...
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ENCODER INPUT — SHORT FRAME ( 5 – Parameter Enable Low Setup Time Enable Low Hold Time Enable Valid Time Enable Hold Time Data Valid Time Data Hold Time ...
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ENCODER INPUT — LONG FRAME ( 5 – Parameter Enable Low Hold Time Enable Valid Time Data Valid Time Data Hold Time EDC EIE 32 kbps ...
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ENCODER OUTPUT — SHORT FRAME Parameter Enable Low Hold Time Enable Valid Time Enable Hold Time Data Valid Time Data Three–State Time (with 150 pF Load) EDC EOE * LSB EDO MSB * 32 kbps transcoding ...
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ENCODER OUTPUT — LONG FRAME Parameter Enable Low Hold Time Enable Valid Time Enable to Data Time (Whichever Edge Occurs Last) Clock to Data Time (Whichever Edge Occurs Last EDC EOE 32 kbps MSB EDO EOE ...
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DECODER INPUT — SHORT FRAME ( 5 – Parameter Enable Low Setup Time to Falling DDC Enable Low Hold Time from Falling DDC Enable Valid Time to Falling DDC ...
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DECODER INPUT — LONG FRAME ( 5 – Parameter Enable Hold Time from Falling DDC Enable Valid Time to Falling DDC Data Valid Time to Falling DDC Data Hold ...
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DECODER OUTPUT — SHORT FRAME Parameter Enable Low Hold Time Enable Valid Time Enable Hold Time Rising Edge of DDC to Valid DDO Delay Time from 8th DDC Low to DDO Output Disabled DDC DOE DDO ...
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DECODER OUTPUT — LONG FRAME Parameter Enable Low Hold Time Enable Valid Time Rising Edge of DDE to Valid DDO (When DDC is High) Rising Edge of DDC to Valid DDO (When DOE is High) Delay Time from 8th DDC ...
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PCM Y BUS OUT ADPCM Z BUS IN 1.544 MHz PCM X BUS OUT POWER–DOWN 1.544 MHz PCM BUS OUT DDO DDO x PCM BUS IN EDI y 1 ...
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MC145503 V AG RxO ANALOG OUT +Tx ANALOG IN Txl – Mu/A PDI V SS – POWER–DOWN 1.544 MHz = RDC = DDC 1 = TDE = EDC TSm1 = RCE = TDE EDI = ...
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V ANALOG OUT + 5 V 2.048 MHz ADPCM IN POWER–DOWN 2.048 MHz = MCLK R = BCLK R = DDC 1 = MCLK X = BCLK X = EDC 8 kHz = DOE = DIE = F ...
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D 16X 0.010 (0.25 14X K - -T- SEATING PLANE 0.25 (0.010) M Motorola reserves the right to make ...