SAB80C515A-N18-T3 Infineon Technologies AG, SAB80C515A-N18-T3 Datasheet
SAB80C515A-N18-T3
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SAB80C515A-N18-T3 Summary of contents
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Microcomputer Components 8-Bit CMOS Single-Chip Microcontroller SAB 80C515A/83C515A-5 Data Sheet 08.95 ...
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High-Performance 8-Bit CMOS Single-Chip Microcontroller Preliminary SAB 83C515A-5 SAB 80C515A SAB 80C515A / 83C515A- MHz operation frequency ROM (SAB 83C515A-5 only, ROM-Protection available) 256 8 on-chip RAM Additional on-chip RAM (XRAM) ...
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Ordering Information Type Ordering Code SAB 80C515A-N18 Q67120-C0581 SAB 83C515A-5N18 Q67120-DXXXX P-LCC-68 SAB 80C515A-N18-T3 Q67120-C0784 SAB 83C515A-5N18-T3 Q67120-DXXXX P-LCC-68 SAB 80C515A-M18-T3 Q67120-C0851 SAB 83C515A-5M18-T3 Q67120-DXXXX P-MQFP-80 with mask-programmable ROM, Notes : Versions for extended temperature range The ordering number of ...
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Logic Symbol Semiconductor Group SAB 80C515A/83C515A-5 3 ...
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The pin functions of the SAB 80C515A are identical with those of the SAB 80C515 with following exception: Pin Pin Configuration (P-LCC-68) Semiconductor Group SAB 80C515A HWPD P0.4/ADST PE/SWD 4 SAB 80C515A/83C515A-5 SAB 80C515 V CC P4.0 ...
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RESET 1 N.C. VAREF VAGND P6.7 / AIN7 5 P6.6 / AIN6 P6.5 / AIN5 P6.4 / AIN4 P6.3 / AIN3 P6.2 / AIN2 10 P6.1 / AIN1 P6.0 / AIN0 N.C. N.C. P3.0 / RXD0 15 P3.1 / ...
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Pin Definitions and Functions Symbol Pin Pin P-LCC-68 P-MQFP-80 P4.0-P4.7 1-3, 5-9 72-74, 76-80 PE/SWD 4 75 RESET AREF1 AGND Semiconductor Group SAB 80C515A/83C515A-5 Input (I) Function Output (O) I/O Port 4 ...
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Pin Definitions and Functions (cont’d) Symbol Pin Pin P-LCC-68 P-MQFP-80 P6.7-P6.0 13-20 5-12 P3.0-P3.7 21-28 15-22 Semiconductor Group SAB 80C515A/83C515A-5 Input (I) Function Output (O) I Port 8-bit unidirectional input port to the A/ D converter. Port ...
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Pin Definitions and Functions (cont’d) Symbol Pin Pin P-LCC-68 P-MQFP-80 P1.7 - 29-36 24-31 P1.0 XTAL2 39 36 Semiconductor Group SAB 80C515A/83C515A-5 Input (I) Function Output (O) I/O Port 8-bit bidirectional I/O port with internal pullup resistors. ...
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Pin Definitions and Functions (cont’d) Symbol Pin Pin P-LCC-68 P-MQFP-80 XTAL1 40 37 P2.0-P2.7 41-48 38-45 PSEN 49 47 ALE 50 48 Semiconductor Group SAB 80C515A/83C515A-5 Input (I) Function Output (O) - XTAL1 Output of the inverting oscillator amplifier. To ...
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Pin Definitions and Functions (cont’d) Symbol Pin Pin P-LCC-68 P-MQFP- P0.0-P0.7 52-59 52-59 P5.7-P5.0 60-67 60-67 HWPD 32 34 N.C. 2, 13, 14, 23, – 46, 50, ...
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Figure 1 Block Diagram Semiconductor Group SAB 80C515A/83C515A-5 11 ...
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Functional Description The SAB 80C515A is based on 8051 architecture fully compatible member of the Siemens SAB 8051/80C51 microcontroller family being an significantly enhanced SAB 80C515. The SAB 80C515A is therefore code compatible with the SAB 80C515. ...
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Program Memory ('Code Space') The SAB 83C515A-5 has 32 Kbyte of on-chip ROM, while the SAB 80C515A has no internal ROM. The program memory can externally be expanded Kbyte. Pin EA determines whether program fetches below address ...
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Data Memory ('Data Space') The data memory space consists of an internal and an external memory space.The SAB 80C515A contains another 1 Kbyte on On-Chip RAM additional to the 256-bytes internal RAM of the base type SAB 80C515. This RAM ...
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Accesses to XRAM Because the XRAM is used in the same way as external data memory the same instruction types must be used for accessing the XRAM. Note reset occurs during a write operation to XRAM, the effect ...
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Special Function Register XPAGE Addr The reset value of XPAGE is 00 XPAGE can be set and read by software. The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri instructions. If the ...
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Control of XRAM in the SAB 80C515A There are two control bits in register SYSCON which control the use and the bus operation during accesses to the additional On-Chip RAM (XRAM). Special Function Register SYSCON Addr. 0B1 H Bit Function ...
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XMAP0 is hardware protected by an unsymmetric latch. An unintentional disabling of XRAM could be dangerous since indeterminate values would be read from external bus. To avoid this the XMAP-bit is forced to '1' only by reset. Additionally, during reset ...
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Table 1: Behaviour of P0/P2 and / during MOVX accesses DPTR < XRAM a) P0/P2 Bus address / active range c) ext. memory is used MOVX @DPTR DPTR XRAM a) P0/P2 BUS address ( ...
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Special Function Registers All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function registers include arithmetic registers, pointers, and registers that provide an interface between the CPU ...
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Table 2: Special Function Register (cont’d) Address Register SYSCON H B2 reserved H B3 reserved H B4 reserved H B5 reserved H B6 reserved H B7 reserved H B8 EN1 IP1 H ...
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Table 2: Special Function Register (cont’d) Address Register reserved F1 H reserved F2 H reserved F3 H reserved F4 H reserved F5 H reserved F6 H reserved Bit-addressable special function registers 2) X ...
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Table 3 Special Function Registers - Functional Blocks Block Symbol Name CPU ACC Accumulator B B-Register DPH Data Pointer, High Byte DPL Data Pointer, Low Byte PSW Program Status Word Register SP Stack Pointer A/D- ADCON0 A/D Converter Control Register ...
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Table 3 Special Function Registers - Functional Blocks (cont’d) Block Symbol Ports Pow.Sav.M PCON ode 2) Serial ADCON0 Channels PCON 2) SBUF SCON SRELL SRELH Timer 0/ TCON Timer 1 TH0 TH1 TL0 ...
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A/D Converter In the SAB 80C515A a new high performance / high-speed 8-channel 10-bit A/D-Converter (ADC) is implemented. Its successive approximation technique provides 7 s conversion time ( MHz). The conversion principle is upward compatible to the one ...
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Figure 3 Block Diagram A/D Converter Semiconductor Group SAB 80C515A/83C515A-5 26 ...
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Timers /Counters The SAB 80C515A contains three 16-bit timers/counters wich are useful in many applications for timing and counting. the input clock for wach timer/counter is 1/12 of the oscillator frequency in the timer operation or can be taken from ...
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Capture This feature permits saving of the actual timer/counter contents into a selected register upon an external event or a software write operation. Two modes are provided to latch the current 16-bit value of timer 2 registers TL2 and TH2 ...
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Figure 4 Block Diagram of Timer/Counter 2 Semiconductor Group SAB 80C515A/83C515A-5 29 ...
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Interrupt Structure The SAB 80C515A has 12 interrupt vectors with the following vector addresses and request flags. Table 4 Interrupt Sources and Vectors Source (Request Flags) IE0 TF0 IE1 TF1 TF2 + EXF2 IADC IEX2 IEX3 IEX4 ...
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Figure 5 Interrupt Request Sources Semiconductor Group SAB 80C515A/83C515A-5 31 ...
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Figure 6 Interrupt Priority Level Structure Semiconductor Group SAB 80C515A/83C515A-5 32 ...
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I/O Ports The SAB 80C515A has six 8-bit I/O ports and one input port. Port open-drain bidirectional I/O port, while ports are quasi-bidirectional I/O ports with internal pull-up resistors. That means, when configured as ...
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Power Saving Modes The SAB 80C515A provides – due to Siemens ACMOS technology – four modes in which power consumption can be significantly reduced. – The Slow Down Mode The controller keeps up the full operating functionality, but is driven ...
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Requirements for Hardware Power Down Mode There is no dedicated pin to enable the Hardware Power Down Mode. The control pin PE/SWD has no control function in this mode. It enables and disables only the use of software controlled power ...
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Software Power Down Mode The power down mode is entered by two consecutive instructions directly following each other. The first instruction has to set the flag PDE (power down enable) and must not set PDS (power down set). The following ...
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Table 5 Status of all pins during Idle Mode, Power Down Mode and Hardware Power Down Mode Pins Idle Mode Last instruction executed from internal external ROM P0 Data float P1 Data Dat alt outputs alt outputsa P2 Data Address ...
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Serial Interface The SAB 80C515A has a full duplex and receive buffered serial interface functionally identical with the serial interface of the SAB 8051. Table 6 shows possible configurations and the according baud rates. Table 6 Baud Rate ...
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The Serial Interface can operate in 4 modes: Mode 0: Shift register mode: Serial data enters and exits through R are transmitted/received (LSB first). The baud rate is fixed at 1/12 of the oscillator fre- quency. Mode 1: 8-bit UART, ...
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Fail Safe Units The SAB 80C515A offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure: – a programmable watchdog timer (WDT), with variable time-out period from 512 appr. 1.1 s ...
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Figure 8 shows the block diagram of the oscillator watchdog unit. It consists of an internal RC oscillator which provides the reference frequency for the frequency comparator. Figure 7 Block Diagram of the Programmable Watchdog Timer Figure 8 Functional Block ...
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Fast internal reset after power-on The SAB 80C515A can use the oscillator watchdog unit for a fast internal reset procedure after power-on. Normally members of the 8051 family (like the SAB 80C515) enter their default reset state not before the ...
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Absolute Maximum Ratings Ambient temperature under bias Storage temperature Voltage on V pins with respect to ground (V CC Voltage on any pin with respect to ground (V Input current on any pin during overload condition Absolute sum of all ...
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DC Characteristics (cont’d) Parameter Output low voltage (ports Output low voltage (ports 0, ALE, RESET) Output high voltage, (ports1 Output high voltage (port 0 in external bus mode,- ALE, PSEN) Logic ...
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Notes for page 44: 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the V of ALE and ports and 5. The noise is due to external bus capacitance ...
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A/D Converter Characteristics – AREF CC AGND Parameter Analog input capacitance C Sample time (inc. load time) Conversion time (inc. sample time) Total ...
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AC Characteristics – for port 0, ALE and PSEN outputs = 100 pF Parameter Symbol Program Memory Characteristics ALE pulse width t Address setup to ALE ...
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AC Characteristics (cont’d) Parameter Symbol External Data Memory Characteristics RD pulse width t WR pulse width t Address hold after t ALE RD to valid data in t DATA hold after RD t Data float after RD t ALE to ...
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Program Memory Read Cycle Data Memory Read Cycle Semiconductor Group SAB 80C515A/83C515A-5 49 ...
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Data Memory Write Cycle Semiconductor Group SAB 80C515A/83C515A-5 50 ...
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AC Characteristics (cont'd) Parameter Symbol External Clock Drive Oscillator period t High time t Low time t Rise time t Fall time t Oscillator frequency 1/t External Clock Cycle Semiconductor Group Variable clock Frequ. = 3.5 MHz to 18 MHz ...
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AC Characteristics (cont’d) Parameter Symbol System Clock Timing ALE to CLKOUT t CLKOUT high time t CLKOUT low time t CLKOUT low to ALE t high System Clock Timing Semiconductor Group 18 MHz clock min. max. 349 – LLSH 71 ...
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ROM Verification Characteristics ˚C 5 ˚ – Parameter Symbol ROM Verification Mode 1 (Standard Verify Mode for not Read Protected ROM) Address to valid data ...
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ROM Verification Mode 2 (New Verify Mode for Protected and not Protected ROM) ROM Verification Mode 2 Semiconductor Group SAB 80C515A/83C515A-5 54 ...
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Application Example for Verifying the Internal ROM with ROM Verify Mode 2 Semiconductor Group SAB 80C515A/83C515A-5 55 ...
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AC Inputs during testing are driven at V ments are made at V for a logic ’1’ and V IHmin AC Testing: Input, Output Waveforms For timing purposes a port pin is no longer floating when a 100 mV change ...