TDA5250D2 Infineon Technologies AG, TDA5250D2 Datasheet
TDA5250D2
Available stocks
Related parts for TDA5250D2
TDA5250D2 Summary of contents
Page 1
Wireless Components ASK/FSK 868MHz Wireless Transceiver TDA 5250 D2 Version 1.6 Specification July 2002 confidential preliminary ...
Page 2
... Components used in life-support devices or systems must be expressly authorized for such purpose! 1 Critical components of the Infineon Technologies AG, may only be used in life-support devices or systems Infineon Technologies AG critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life- support device or system affect its safety or effectiveness of that device or system ...
Page 3
Product Info General Description The low power consumption single chip FSK/ASK Transceiver for half duplex low datarate communica- tion in the 868-870MHz band. The IC offers a very high level of integration and needs only a ...
Page 4
Table of Contents 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
Data Valid Detection ...
Page 7
Product Description Contents of this Chapter 2.1 Overview ...
Page 8
Overview The low power consumption single chip FSK/ASK Transceiver for the fre- quency band 868-870 MHz. The IC combines a very high level of integration and minimum external part count. The device contains a low ...
Page 9
Features Low supply current (I I both supply voltage, 25°C) Supply voltage range 2 5 Operating temperature range -40°C to +85°C I Power down mode with very low supply current consumption ...
Page 10
Package Outline Figure 2-1 Wireless Components P-TSSOP-38-1 package outlines TDA 5250 D2 preliminary Product Description P-TSSOP-38-1.EPS Specification, July 2002 ...
Page 11
Functional Description Contents of this Chapter 3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 12
Pin Configuration VCC BUSMODE LF ____ ASKFSK __ RxTx LNI LNIx GND1 GNDPA PA VCC1 PDN PDP SLC VDD BUSDATA BUSCLK VSS XOUT Figure 3-1 Wireless Components ...
Page 13
Pin Definition and Function Table 3-1 Pin Definition and Function Pin No. Symbol Equivalent I/O-Schematic 1 VCC 2 BUSMODE ASKFSK 5 RXTX 5 6 LNI 6 Wireless Components Function Analog supply (antiparallel diodes between ...
Page 14
LNIx 8 Gnd1 9 GNDPA VCC1 12 PDN 12 13 PDP 13 14 SLC 14 15 VDD 16 BUSDATA 16 Wireless Components see Pin see Pin 8 10 Ω ...
Page 15
BUSCLK 18 VSS 19 XOUT 20 XSWF 21 XIN 22 XSWA 23 XGND RESET Wireless Components 350 17 see Pin 8 Vcc 4k Vcc-860mV 19 150µA 21 125fF ..... 4pF 20 250fF ..... 8pF 23 ...
Page 16
CLKDIV 27 PWDDD 28 DATA 28 29 RSSI 29 30 GND 31 CQ2x 32 CQ2 33 CI2x 34 CI2 35 CQ1x 36 CQ1 37 CI1x 38 CI1 Wireless Components Clock output 350 26 Power Down input (active high), ...
Page 17
Functional Block Diagram BUSMODE __ EN BUSCLK BUSDATA Figure 3-2 Wireless Components SLC 31 CQ2x 32 CQ2 33 CI2x 34 CI2 35 CQ1x 36 CQ1 37 CI1x 38 CI1 (digital) (analog) (LNA/PA) Main Block Diagram ...
Page 18
Functional Blocks 3.4.1 Power Amplifier (PA) The power amplifier is operating in C-mode. It can be used in either high or low power mode. In high-power mode the transmit power is approximately +13dBm into 50 Ohm at 5V ...
Page 19
Downconverter 2 3.4.4 The Low pass filter is followed by 2 mixers (inphase I and quadrature Q) that convert the 289MHz IF signal down to zero-IF. These two mixers are driven by a signal that is generated by dividing ...
Page 20
The bandwidth of the filters is controlled by the values set in the filter-register. It can be adjusted between 50 and 350kHz in 50kHz steps via the bits the LPF register (subaddress 03H). 3.4.7 I/Q ...
Page 21
Data Filter The 2-pole data filter has a Sallen-Key architecture and is implemented fully on- chip. The bandwidth can be adjusted between approximately 5kHz and 102kHz via the bits the LPF register as shown ...
Page 22
Crystal Oscillator 3.4.12 The reference oscillator is an NIC oscillator type (Negative Impedance Converter) with a crystal operating in serial resonance. The nominal operating frequency of 18.083MHz and the frequencies for FSK modulation can be adjusted via 3 external ...
Page 23
Timing and Data Control Unit The timing and data control unit contains a wake-up logic unit microcontroller interface, a “data valid” detection unit and a set of configuration registers as shown in the subsequent figure. Figure ...
Page 24
Bus Interface and Register Definition The TDA5250 supports the I Operation is selectable by the BusMode pin (pin 2) as shown in the following table. All bus pins (BusData, BusCLK, EN, BusMode) have a Schmitt-triggered input stage. The ...
Page 25
Start Condition (STA): A start condition is defined by a HIGH to LOW transition of the BusData line while BusCLK is HIGH. This start condition must precede any command and initiate a data transfer onto the bus. Stop Condition ...
Page 26
Bus Data Format in I Table 3-7 Chip address Organization MSB Table 3 Bus Write Mode 8 Bit MSB CHIP ADDRESS (WRITE) LSB MSB SUB ADDRESS (WRITE) STA ...
Page 27
Data Transfer Write Mode: To start the communication the EN line has to be set to LOW. The desired sub address byte and data bytes have to follow. The subaddress (00H...0FH) determines which of the data bytes are transmitted. ...
Page 28
Subaddress Organization Table 3-13 Sub Addresses of Data Registers Write MSB LSB HEX 00h CONFIG 01h FSK ...
Page 29
Table 3-16 01H: FSK Sub Address Bit Function Value Description D15 not used D14 not used D13 FSK+5 8pF Setting for D12 FSK+4 4pF positive D11 FSK+3 2pF frequency D10 FSK+2 1pF shift: +FSK or D9 FSK+1 500fF ASK-RX ...
Page 30
Table 3-22 Sub Address 08H: RSSI_TH3 Bit Function Description D7 not used D6 SELECT 0= VCC, 1= RSSI D5 TH3_5 D4 TH3_4 D3 TH3_3 D2 TH3_2 D1 TH3_1 D0 TH3_0 Table 3-26 Sub Address 80H: STATUS Function Description Bit ...
Page 31
Wakeup Logic 3.4.16 Figure 3-9 Table 3-28 MODE settings: CONFIG register MODE_1 SLAVE MODE: The receive and transmit operation is fully controlled by an external control device via the respective RxTx, AskFsk, PwdDD, and Data pins. The wakeup logic ...
Page 32
If ADC & Data Detect Logic are in continuous mode the 15µs LOW impulse is applied at PwdDD after each data valid decision. In self polling mode if D9=0 (Register 00h) and when PwdDD pin level is HIGH the ...
Page 33
Data Valid Detection, Data Pin Data signals generate a typical spectrum and this can be used to determine if valid data is on air. RSSI Figure 3-12 The “data valid” criterion is generated from the result of RSSI-TH3 ...
Page 34
Sequence Timer The sequence timer has to control all the enable signals of the analog components inside the chip. The time base is the 32 kHz RC oscillator. After the first POWER ON or RESET a 1 MHz ...
Page 35
RESET POWER ON PWDDD = high STATUS XTAL EN CLOCK FOR EXTERNAL µP DC OFFSET COMPENSATION PEAK DETECTOR EN DATADETECTION EN POWER AMP 0.5ms Figure 3-16 Note: The time values ...
Page 36
Clock Divider It supports an external logic with a programmable Clock at pin 26 (CLKDIV). INTERNAL BUS 18 MHz Figure 3-18 The Output Selection and Divider Ratio can be set in the CLK_DIV register. Table 3-29 CLK_DIV Output ...
Page 37
Table 3-30 CLK_DIV Setting Note: As long as default settings are used, there is no clock available at the clock output ...
Page 38
Wireless Components Functional Description Specification, July 2002 TDA 5250 D2 preliminary ...
Page 39
Wireless Components Functional Description Specification, July 2002 TDA 5250 D2 preliminary ...
Page 40
Wireless Components Functional Description Specification, July 2002 TDA 5250 D2 preliminary ...
Page 41
Applications Contents of this Chapter 4.1 LNA and PA Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 42
LNA and PA Matching 4.1.1 RX/TX Switch Figure 4-1 The RX/TX-switch combines the PA-output and the LNA-input into a single 50 Ohm SMA-connector. Two pin-diodes are used as switching elements current flows through a pin diode, ...
Page 43
The RF-signal is able to run from the RF-input-SMA-connector to the LNA- input-pin LNI via C1, C2, C7, L3 and C9. R1 does not affect the matching circuit due to its high resistance. The other input of the differential ...
Page 44
An approximation of the losses of the input matching network can be made with the formula: = − Loss The noise figure of the LNA-input-matching network is equal to its losses. The input matching network is always a compromise ...
Page 45
Switch in TX-Mode The evalboard can be set into the TX-Mode by grounding the RX/TX-jumper on the evalboard or programming the TDA5250 to operate in the TX-Mode. If the IC is programmed to operate in the TX-Mode, the ...
Page 46
The LNA-matching is RF-grounded now power is lost in the LNA-input. The PA-matching consists of C2, C3 L2, C4 and L1. When designing the matching of the PA, C2 must not be changed anymore because its value ...
Page 47
RF peak voltage swing at the collector of the PA transistor to just reach the supply voltage V efficiency under “critical” operating conditions can be explained by the low power loss at the ...
Page 48
Figure 4-7 The DC collector current I vary with the load resistor R amplifiers. The collector current will show a characteristic dip at the resonance frequency for this type of “overcritical” operation. The depth of this dip will increase ...
Page 49
C4, L2 and C3||C2 are the main matching components which are used to transform the 50 Ohm load at the SMA-RF-connector to a higher impedance at the PA-output (240Ohm@3V). L1 can be used for finetuning of the resonance frequency ...
Page 50
Above you can see the measurement of the evalboard with a span of 200MHz. The evalboard has been optimized for 3V. The load is about 240+j0 at 868.3MHz. A tuning-free realization requires a careful design of the components within ...
Page 51
Figure 4-11 Regarding CEPT ERC recommendation 70-03 and ETSI regulation EN 300220 both of the following figures show full compliance in case of ASK and FSK modulation spectrum. Data signal is a Manchester encoded PRBS9 (Pseudo Random Binary Sequence), ...
Page 52
Figure 4-12 Figure 4-13 Wireless Components ASK_25kBaud_Manch_PRBS9_10dBm_3V_Spectrum_CEPT_ERC7003.wmf ASK Transmit Spectrum 25kBaud, Manch, PRBS9, 9dBm, 3V FSK_40kBaud_Manch_PRBS9_10dBm_3V_Spectrum_CEPT_ERC7003.wmf FSK Transmit Spectrum 40kBaud, Manch, PRBS9, 9dBm TDA 5250 D2 preliminary Applications Specification, July 2002 ...
Page 53
Crystal Oscillator The equivalent schematic of the crystal with its parameters specified by the crystal manufacturer can be taken from the subsequent figure. Here also the load capacitance of the crystal C in order to oscillate at the ...
Page 54
D = δ Choosing C other hand a small C tolerances associated to it small (see formula [4-17]). Start-up Time t ~ Start where: -R: The proportionality crystal with a small C the ...
Page 55
Figure 4- With the aid of this formula it becomes obvious that the higher the serial capac- itance C V The tolerance of the internal oscillator inductivity is much higher, so the induc- tivity is the ...
Page 56
With calculated. Alternatively, an external AC coupled (10nF in series to 1k applied at pin 19 (Xout). The drive level should be approximately 100mVpp. 4.2.1 Synthesizer Frequency setting Generating ASK and FSK modulation 3 setable frequencies ...
Page 57
FSK-mode: In transmit mode the two frequencies representing logical HIGH and LOW data states have to be adjusted depending on the intended frequency deviation and separately according to the following formulas : f COSC HI e.g. f COSC ...
Page 58
Figure 4-17 In receive mode the crystal oscillator frequency is set to yield a direct-to-zero conversion of the receive data. Thus the frequency may be calculated as e.g. which is identical to ...
Page 59
In this case the ASK-switch is closed. The necessary C C The C-bank C finetuning of the FSK receive frequency. In this case the switches of the C-bank are controlled by the bits the XTAL_TUNING ...
Page 60
Table 4-2 Typical values of parasitic capacitances With the given parasitics the actual --------------------------------------------------------------------------------------------------------------------------- vm Note: Please keep in mind also to include the Pad parasitics of the circuit board. 4.2.4 Calculation of ...
Page 61
To compensate frequency errors due to crystal and component tolerance C C and C v2 capacitance variation has to be realized with the internal C-banks finetuning is intended it is recommended to leave XIN (Pin 21) open. ...
Page 62
Finetuning and FSK modulation relevant registers Case FSK-RX or ASK-TX (C Table 4-4 Bit Case FSK-TX or ASK-RX (C Table 4-5 Bit D13 D12 D11 D10 ...
Page 63
Chip and System Tolerances Quartz: fp=18.08958MHz; C1=8fF; C0=2,08pF; CL=12pF (typical values) Cv1=4.7pF, Cv2=1.8pF, Cv3=12pF Table 4-7 Internal Tuning Frequency set accuracy Temperature (-40...+85C) Supply Voltage(2.1...5.5V) Table 4-8 Default Setup (without internal tuning & without Pin21 usage) Internal capacitors ...
Page 64
The frequency stabilities of both the receiver and the transmitter and the modulation bandwidth set the limit for the bandwidth of the IQ filter. To achieve a high receiver sensitivity and efficient suppression of adjacent interference signals, the narrowest ...
Page 65
Figure 4-21 4.4 Data Filter The Data-Filter should be set to values corresponding to the bandwidth of the transmitted Data signal via the bits of the LPF register (subaddress 03H). Table 4-10 3dB cutoff frequencies ...
Page 66
Limiter and RSSI The I/Q Limiters are DC coupled multistage amplifiers with offset-compensating feedback circuit and an overall gain of approximately 80dB each in the frequency range of 100Hz up to 350kHz. Receive Signal Strength Indicator (RSSI) generators ...
Page 67
Figure 4-23 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 Figure 4-24 Wireless Components v [dB 3dB 3dB lower limit IQ Filter Limiter frequency characteristics -120 -110 -100 -90 ...
Page 68
Data Slicer - Slicing Level The data slicer is an analog-to-digital converter necessary to generate a threshold value for the negative comparator input (data slicer). The TDA5250 offers an RC integrator and a peak detector which ...
Page 69
Peak Detectors Table 4-13 Sub Address 00H: CONFIG Bit Function D15 SLICER The TDA5250 has two peak detectors built in, one for positive peaks in the data stream and the other for the negative ones. Necessary external components: ...
Page 70
Figure 4-27 Component calculation: (rule of thumb) ⋅ 2 ≥ 100k ⋅ 2 ≥ 100k 4.6.3 Peak Detector - Analog output signal The TDA5250 data output can be digital (pin 28 analog form ...
Page 71
Peak Detector – Power Down Mode For a safe and fast threshold value generation the peak detector is turned on by the sequencer circuit (see Section 3.4.18) only after the entire receiving path is active. In the off ...
Page 72
Data Valid Detection In order to detect valid data two criteria must be fulfilled. One criteria is the data rate, which can be set in register 06h and 07h. The other one is the received RF power level, ...
Page 73
Timing in Single Shot mode can be seen in the subsequent figure: Figure 4-32 4.7.1 Frequency Window for Data Rate Detection The high time of data is used to measure the frequency of the data signal. For Manchester coding ...
Page 74
Example to calculate the thresholds for a given data rate: - Data signal manchester coded - Data Rate: 2kbit 18,0896 MHz clk Then the period equals to respectively the high time is 0,25ms. We set the ...
Page 75
RSSI threshold voltage - RF input power The RF input power level is corresponding to a certain RSSI voltage, which can be seen in Section 4.5. The threshold TH3 of this RSSI voltage can be calculated with the ...
Page 76
Calculation of ON_TIME and OFF_TIME 16 ON OFF Frequency of internal RC Oszillator RC Example: t ON= 65535-(32300*0,005) ~ 65373= 1111111101011101 OFF= 65535-(32300*0,055) ~ 63758= 1111100100001110 The values have to be written into ...
Page 77
Example for Self Polling Mode The settings for Self Polling Mode depend very much on the timing of the transmitted Signal. To create an example we consider following data structure transmitted in FSK ...
Page 78
One possible Solution 15ms This gives 15ms ON time of a total period of 150ms which results in max. 0.9mA mean current consumption in Self Polling Mode. The resulting worst case timing is shown in ...
Page 79
Sensitivity Measurements 4.10.1 Test Setup The test setup used for the measurements is shown in the following figure. In case of ASK modulation the Rohde & Schwarz SMIQ generator, which is a vec- tor signal generator, is connected ...
Page 80
In the following figures the RF power level shown is the average power level. These investigations have been made on an Infineon evaluation board using a data rate of 4 kBit/s with manchester encoding and a data filter bandwidth ...
Page 81
Sensitivity depending on the ambient Temperature Demonstrating a wide band of application possibilities the temperature behavior must not be forgotten. In automotive systems the required temperature range is from -40 °C to +85 °C. The receivers very good ...
Page 82
BER performance depending on Supply Voltage Due to the wide supply voltage range of this transeiver chip also the sensitivity behaviour over this parameter is documented is the subsequent graph. Figure 4-38 Please notice the tiny sensitivity changes ...
Page 83
Datarates and Sensitivity The TDA 5250 can handle datarates up to 64kbit/s, as can be taken from the following figure. (see also Section 5.1.4) Figure 4-39 Wireless Components Datarates and Sensitivity TDA 5250 D2 preliminary ...
Page 84
Sensitivity at Frequency Offset Applying the test setup in Figure 4-36 even a wide offset in the received frequency spectrum results only in a slight decrease of receiving sensitivity offset of 100kHz one of the two ...
Page 85
Default Setup Default setup is hard wired on chip and effective after a reset or return of power supply. Table 4-14 Default Setup Parameter IQ-Filter Bandwidth Data Filter Bandwidth Limiter lower fg Slicing Level Generation Nom. Frequency Capacity ...
Page 86
TDA 5250 D2 Reference Contents of this Chapter 5.1 Electrical Data ...
Page 87
Electrical Data 5.1.1 Absolute Maximum Ratings WARNING The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. Table 5-1 Absolute Maximum Ratings # Parameter 1 ...
Page 88
AC/DC Characteristics AC/DC characteristics involve the spread of values guaranteed within the spec- ified voltage and ambient temperature range. Typical characteristics are the median of the production. Table 5-3 AC/DC Characteristics with T # Parameter Symbol RECEIVER Characteristics ...
Page 89
Table 5-3 AC/DC Characteristics with T # Parameter Symbol TRANSMITTER Characteristics 1 Supply current TX, FSK Supply current TX, FSK Supply current TX, FSK Output power out 5 Output ...
Page 90
Table 5-4 AC/DC Characteristics with T # Parameter Symbol GENERAL Characteristics 1 Power down current I PWDN_32k timer mode (standby) 2 Power down current I PWDN_32k timer mode (standby) 3 Power down current I PWDN_Xtl with XTAL ON 4 ...
Page 91
Digital Characteristics Bus Timing BusMode = LOW t BUF BusData LOW t BusCLK HD.STA t HD.DAT t HIGH EN pulsed or t mandatory low SU.ENASDA t SU.ENASDA Figure 5-1 3-wire Bus Timing ...
Page 92
Table 5-5 Digital Characteristics with T # Parameter Sym- bol 1 Data rate TX ASK f TX.ASK 2 Data rate TX ASK f TX.ASK 3 Data rate TX FSK f TX.FSK 4 Data rate RX ASK f RX.ASK 5 ...
Page 93
Table 5-5 Digital Characteristics with T # Parameter Sym- bol 17 Data hold time t HD.DAT 18 Data setup time t SU.DAT 19 Rise, fall time of both Bus- t Data and BusCLK signals 20 Setup time for STOP ...
Page 94
Test Circuit The device performance parameters marked with sured on an Infineon evaluation board (IFX board). Figure 5-3 Wireless Components Schematic of the Evaluation Board TDA 5250 D2 preliminary TDA 5250 D2 Reference in Section ...
Page 95
Test Board Layout Gerberfiles for this Testboard are available on request. Figure 5-4 Note: The LNA and PA matching network was designed for minimum required space and maximum performance and thus via holes were deliberately placed into solder ...
Page 96
Bill of Materials Table 5-6 Bill of Materials Reference R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 ...
Page 97
Table 5-6 Bill of Materials Reference C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 IC1 IC2 IC3 D1 Wireless Components ...