X24645 Intersil Corporation, X24645 Datasheet
X24645
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X24645 Summary of contents
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... The Programmable Hardware Write Protect feature allows the user to install the X24645 with WP tied to V program the entire memory array in place, and then enable the hardware write protection by programming a WPEN bit in the write protect register ...
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... first and second bits of the 8-bit slave address. This allows up to four X24645 devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to V appropriate. If actively driven, they must be driven with CMOS levels (driven to V ...
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... The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and pro- vide the clock for both transmit and receive operations. Therefore, the X24645 will be considered a slave in all applications. Figure 1. Data Validity SCL ...
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... X24645 will respond with an acknowl- edge after the receipt of each subsequent 8-bit word. In the read mode the X24645 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge acknowledge is detected and no stop condition is generated by the master, the X24645 will continue to transmit data ...
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... The master then terminates the transfer by gener- ating a stop condition, at which time the X24645 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24645 inputs are disabled, and the device will not respond to any re- quests from the master ...
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... X24645 Page Write The X24645 is capable of a 32-byte page write opera- tion initiated in the same manner as the byte write operation, but instead of terminating the write cycle af- ter the first data word is transferred, the master can transmit up to thirty-one more bytes. After the receipt of each byte, the X24645 will respond with an acknowl- edge ...
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... R/W bit set HIGH. This will be followed by an acknowledge from the X24645 and then by the data byte. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 8 for the address, acknowledge and data trans- fer sequence ...
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... At the end of the address space (address 8191), the counter “rolls over” and the X24645 continues to output data for each acknowledge received. Refer to Figure 9 for the address, acknowledge and data transfer sequence. ...
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... X24645 WRITE PROTECT REGISTER The Write Protect Register (WPR) is located at the highest address, 1FFFh. Figure 11. Write Protect Register WPR (ADDR = 1FFFh WPEN 0 0 BP1 BP0 WPR.1 = WEL – “Write Enable” Latch (Volatile Write enable latch reset, writes disabled 1 = Write enable latch set, writes enabled If WEL = “ ...
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... X24645 Block Protect Bits The Block Protect Bits BP0 and BP1 determine which blocks of the memory are write-protected: Table 1. Block Protect Bits Protected BP1 BP0 Addresses 0 0 None 0 1 1800h–1FFFh 1 0 1000h–1FFFh 1 1 0000h–1FFFh Table 2. Write Protect Status Table ...
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... X24645 ABSOLUTE MAXIMUM RATINGS* Temperature under Bias X24645.......................................– +135 C Storage Temperature ........................– +150 C Voltage on any Pin with Respect to V .................................... –1V to +7V SS D.C. Output Current ..............................................5mA Lead Temperature (Soldering, 10 seconds) .............................. 300 C RECOMMENDED OPERATING CONDITIONS Temperature Min. Commercial 0 C Industrial –40 C Military – ...
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... X24645 A.C. CONDITIONS OF TEST Input Pulse Levels V CC Input Rise and Fall Times Input and Output Timing Levels A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read & Write Cycle Limits Symbol f SCL Clock Frequency SCL T Noise Suppression Time I Constant at SCL, SDA Inputs ...
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... BUS CAPACITANCE (pF) t HIGH t LOW HD:STA t HD:DAT t SU:DAT Min. Typ. X24645 bus interface circuits are disabled, SDA is allowed to remain HIGH, and the device does not respond to its slave address. ACK t WR STOP CONDITION SYMBOL TABLE 2783 ILL F19 ...
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... X24645 PACKAGING INFORMATION HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) TYP. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 0.430 (10.92) 0.360 (9.14) PIN 1 INDEX PIN 1 0.300 (7.62) REF. SEATING PLANE 0.150 (3.81) 0.125 (3.18) ...
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... X24645 PACKAGING INFORMATION 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0 – 8 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.150 (3.80) 0.158 (4.00) PIN 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7 0.004 (0.19) 0.050 (1.27) 0.010 (0.25 0.0075 (0.19) 0.250" 0.010 (0.25) ...
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... X24645 PACKAGING INFORMATION 14-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S PIN 1 INDEX PIN 1 0.014 (0.35) 0.020 (0.51) (4X) 7 0.050 (1.27) 0.010 (0.25) 0.020 (0.50) 0 – 8 0.016 (0.41) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.150 (3.80) 0.158 (4.00) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25 0.0075 (0.19) 0.250" 0.010 (0.25) FOOTPRINT 16 0 ...
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... X24645 PACKAGING INFORMATION 20-LEAD PLASTIC, TSSOP PACKAGE TYPE V 0 – 8 See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .252 (6.4) .300 (6.6) .047 (1.20) .0075 (.19) .002 (.05) .0118 (.30) .006 (.15) .010 (.25) Gage Plane Seating Plane .019 (.50) .029 (.75) Detail A (20X) ...
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... X24645 Device Part Mark Convention X24645 LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fi ...