AD875JST Analog Devices, AD875JST Datasheet
AD875JST
Related parts for AD875JST
AD875JST Summary of contents
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... C to +70 C) temperature range. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices ...
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AD875–SPECIFICATIONS ( MIN DC SPECIFICATIONS REFBF Parameter RESOLUTION DC ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Codes 0 to 255 Codes 256 to 1023 No Missing Codes Offset Gain ANALOG INPUT Input Range ...
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DIGITAL SPECIFICATIONS Parameter LOGIC INPUT High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Low Level Input Current (CLK Only) Input Capacitance LOGIC OUTPUTS High Level Output Voltage ( ...
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AD875 PIN DESCRIPTIONS Symbol Pin No. Type Name and Function D0 (LSB Least Significant Bit D1–D4 2–5 DO Data Bits 1 Through 4 D5–D8 8–11 DO Data Bits 5 Through 8 D9 (MSB Most Significant Bit ...
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... DD (NOT TO SCALE (MSB) 12 ORDERING GUIDE Model Temperature Range Package AD875JST +70 C AD875JST-Reel +70 C ABSOLUTE MAXIMUM RATINGS* Parameter DRV AIN REFTS, REFTF, REFBS, REFBF Digital Inputs, CLK Junction Temperature Storage Temperature Lead Temperature (10 sec) *Stresses above those listed under “ ...
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AD875 DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity (INL) Integral nonlinearity refers to the deviation of each individual code from a line drawn from “zero” through “full scale.” The point used as “zero” occurs 1/2 LSB before the first code transition. “Full ...
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In general, a low drive impedance is suggested to minimize noise coupled on the AIN inputs Figure 5. Simple AD875 Drive Requirements For systems which must level ...
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AD875 REFTF and REFBF is also recommended for optimum performance. This reference configuration provides the lowest cost solution but has several disadvantages including poor dc power supply rejection and poor accuracy due to the variability of the internal and external ...
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Figure 12. + 74XX74 30MHz Q S +5V Figure 12. Divide-By-Two Clock Input Circuit The AD875 is designed to support a ...
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AD875 Also, a sleep mode feature is provided such that for STBY = HIGH and the clock disabled, the static power of the AD875 will drop below 50 mW. The AD875 reaches rated accuracy 4 clock cycles after STBY is ...
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APPLICATIONS IMAGING SYSTEM OVERVIEW While the specifics of a particular imaging system will vary, most architectures will employ some or all of the building blocks shown in Figure 15. The image sensor, often a charged-coupled device (CCD), transforms light to ...
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AD875 MULTICHANNEL IMAGE ACQUISITION SYSTEM The AD875’s fast conversion rate combined with the AD783 sample/hold amplifiers (SHAs) and the AD9300 high speed multiplexer can be used to construct an analog front-end capable of acquiring and digitizing three or more analog ...
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HIGH SPEED SAMPLE-AND-HOLD AMPLIFIER (SHA) A sample-hold amplifier is often needed as part of a correlated double sampler or when high bandwidth inputs such as video signals are to be converted by the AD875. For fast, precise sampling required for ...
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AD875 TP6 D +5D FB2 +5VD 0.01 33 0.1 DGND WJ1 FB3 0.01 33 0.1 +3.3V +3.3D + C19 0 C14 0 REFTF C15 29 R4 REFTS ...
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Figure 21. Silkscreen Layer, Component Side PCB Layout Figure 22. Silkscreen Layer, Circuit Side PCB Layout REV. 0 –15– AD875 ...
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AD875 Figure 23. Component Side PCB Layout Figure 24. Circuit Side PCB Layout –16– REV. 0 ...
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REV. 0 Figure 25. Ground Layer PCB Layout Figure 26. Power Layer PCB Layout –17– AD875 ...
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AD875 0.02 ± 0.008 (0.5 ± 0.2) SEATING PLANE 0.004 ± 0.002 (0.1 ± 0.05) ° °) (3.5 ± 3.5 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). TQFP 0.059 +0.008 –0.004 0.354 ± 0.008 (9.00 ± 0.2) SQ (1.50 ...
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