AD875JST Analog Devices, AD875JST Datasheet

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AD875JST

Manufacturer Part Number
AD875JST
Description
Manufacturer
Analog Devices
Datasheet
a
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PRODUCT DESCRIPTION
The AD875 is a CMOS, low power 10-bit, 15 MHz analog-to-
digital converter (ADC). The AD875 combines high speed
10-bit resolution and performance with low power and single
supply operation. By implementing a multistage pipelined
architecture with output error correction logic, the AD875
offers accurate performance and guarantees no missing codes
over the full operating temperature range. To minimize external
voltage drops, the reference ladder top and bottom are provided
with force and sense pins.
The AD875’s digital I/Os can interface to either +5 V or +3.3 V
logic. The AD875 can be placed into a standby mode of operation
reducing the power below 50 mW. Digital output data can be
placed in a high impedance state and is offered in a variety of
formats, including straight binary and twos complement output.
The AD875 also provides both underrange and overrange
output bits, indicating when the analog input has exceeded the
analog input range.
The AD875’s speed, resolution and single-supply operation are
ideally suited for a variety of applications in imaging, high speed
data acquisition and communications. The AD875’s low power
and single supply operation are required for high speed portable
applications. Its speed and resolution are ideally suited for charge
coupled device (CCD) input systems such as color scanners, digital
copiers, electronic still cameras and camcorders.
The AD875 is packaged in a space saving 48-pin thin quad
flatpack (TQFP) and is specified over the commercial (0 C to
+70 C) temperature range.
FEATURES
CMOS 10-Bit, 15 MHz A/D Converter
Low Power Dissipation: 185 mW
+5 V Single-Supply Operation
Differential Nonlinearity: 0.4 LSB
Guaranteed No Missing Codes
Power-Down (Standby) Mode: <50 mW
Three-State Outputs
Digital l/Os Compatible with +5 V or +3.3 V Logic
Adjustable Reference Input
Small Size: 48-Pin Thin Quad Flatpack (TQFP)
PRODUCT HIGHLIGHTS
Low Power—The AD875 at 185 mW consumes a fraction of the
power of presently available 10-bit, video-speed converters.
Power-down mode and single-supply operation further enhance
its desirability in low power, battery operated applications such
as electronic still cameras, camcorders and communication
systems.
Superior Differential Nonlinearity Performance—The AD875’s
typical DNL performance is 0.4 LSB and a maximum of 0.8 LSBs
for the 0 to 255 code range (ideal for imaging systems). No
missing codes are guaranteed.
Very Small Package—The AD875 is available in a 48-pin surface
mount, thin quad flatpack. The TQFP package is ideal for very
tight, low headroom designs. The AD875 is available in tape
and-reel.
Digital I/O Functionality—The AD875 offers several digital
features which allow output data formatting, fixed output test
pattern generation to facilitate in-circuit testing, three-state
output control and over/underrange indicators.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
REFMID
REFBQ
REFTS
REFTQ
REFBS
REFBF
REFTF
AIN
AIN
FUNCTIONAL BLOCK DIAGRAM
A/D
CLK
AD875
CML
SHA
10-Bit, 15 MHz, 185 mW
D/A
CMOS A/D Converter
GAIN
CORRECTION LOGIC
OUTPUT BUFFERS
AV
AV
A/D
SHA
SS
DD
D/A
DV
DV
SS
DD
GAIN
DRV
DRV
SS
DD
A/D
AD875
Fax: 617/326-8703
LINV
TEST MODE
THREE-STATE
STBY
MINV
D9 (MSB)–
D0 (LSB)
OVR,
UNR

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AD875JST Summary of contents

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... C to +70 C) temperature range. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices ...

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AD875–SPECIFICATIONS ( MIN DC SPECIFICATIONS REFBF Parameter RESOLUTION DC ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Codes 0 to 255 Codes 256 to 1023 No Missing Codes Offset Gain ANALOG INPUT Input Range ...

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DIGITAL SPECIFICATIONS Parameter LOGIC INPUT High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Low Level Input Current (CLK Only) Input Capacitance LOGIC OUTPUTS High Level Output Voltage ( ...

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AD875 PIN DESCRIPTIONS Symbol Pin No. Type Name and Function D0 (LSB Least Significant Bit D1–D4 2–5 DO Data Bits 1 Through 4 D5–D8 8–11 DO Data Bits 5 Through 8 D9 (MSB Most Significant Bit ...

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... DD (NOT TO SCALE (MSB) 12 ORDERING GUIDE Model Temperature Range Package AD875JST +70 C AD875JST-Reel +70 C ABSOLUTE MAXIMUM RATINGS* Parameter DRV AIN REFTS, REFTF, REFBS, REFBF Digital Inputs, CLK Junction Temperature Storage Temperature Lead Temperature (10 sec) *Stresses above those listed under “ ...

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AD875 DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity (INL) Integral nonlinearity refers to the deviation of each individual code from a line drawn from “zero” through “full scale.” The point used as “zero” occurs 1/2 LSB before the first code transition. “Full ...

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In general, a low drive impedance is suggested to minimize noise coupled on the AIN inputs Figure 5. Simple AD875 Drive Requirements For systems which must level ...

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AD875 REFTF and REFBF is also recommended for optimum performance. This reference configuration provides the lowest cost solution but has several disadvantages including poor dc power supply rejection and poor accuracy due to the variability of the internal and external ...

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Figure 12. + 74XX74 30MHz Q S +5V Figure 12. Divide-By-Two Clock Input Circuit The AD875 is designed to support a ...

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AD875 Also, a sleep mode feature is provided such that for STBY = HIGH and the clock disabled, the static power of the AD875 will drop below 50 mW. The AD875 reaches rated accuracy 4 clock cycles after STBY is ...

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APPLICATIONS IMAGING SYSTEM OVERVIEW While the specifics of a particular imaging system will vary, most architectures will employ some or all of the building blocks shown in Figure 15. The image sensor, often a charged-coupled device (CCD), transforms light to ...

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AD875 MULTICHANNEL IMAGE ACQUISITION SYSTEM The AD875’s fast conversion rate combined with the AD783 sample/hold amplifiers (SHAs) and the AD9300 high speed multiplexer can be used to construct an analog front-end capable of acquiring and digitizing three or more analog ...

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HIGH SPEED SAMPLE-AND-HOLD AMPLIFIER (SHA) A sample-hold amplifier is often needed as part of a correlated double sampler or when high bandwidth inputs such as video signals are to be converted by the AD875. For fast, precise sampling required for ...

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AD875 TP6 D +5D FB2 +5VD 0.01 33 0.1 DGND WJ1 FB3 0.01 33 0.1 +3.3V +3.3D + C19 0 C14 0 REFTF C15 29 R4 REFTS ...

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Figure 21. Silkscreen Layer, Component Side PCB Layout Figure 22. Silkscreen Layer, Circuit Side PCB Layout REV. 0 –15– AD875 ...

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AD875 Figure 23. Component Side PCB Layout Figure 24. Circuit Side PCB Layout –16– REV. 0 ...

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REV. 0 Figure 25. Ground Layer PCB Layout Figure 26. Power Layer PCB Layout –17– AD875 ...

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AD875 0.02 ± 0.008 (0.5 ± 0.2) SEATING PLANE 0.004 ± 0.002 (0.1 ± 0.05) ° °) (3.5 ± 3.5 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). TQFP 0.059 +0.008 –0.004 0.354 ± 0.008 (9.00 ± 0.2) SQ (1.50 ...

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