ad875 Analog Devices, Inc., ad875 Datasheet
ad875
Available stocks
Related parts for ad875
ad875 Summary of contents
Page 1
... The AD875’s digital I/Os can interface to either + +3.3 V logic. The AD875 can be placed into a standby mode of operation reducing the power below 50 mW. Digital output data can be placed in a high impedance state and is offered in a variety of formats, including straight binary and twos complement output ...
Page 2
... AD875–SPECIFICATIONS ( MIN DC SPECIFICATIONS REFBF Parameter RESOLUTION DC ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Codes 0 to 255 Codes 256 to 1023 No Missing Codes Offset Gain ANALOG INPUT Input Range Input Resistance Input Current Input Capacitance REFERENCE INPUT Reference Top Voltage ...
Page 3
... Symbol Min SAMPLE N+2 SAMPLE N SAMPLE N DATA N–3 DATA N–2 Figure 1. AD875 Timing Diagram –3– AD875 = + +4 +2 REFTF REFBF Min Typ Max 2.4 3.8 4.2 0.6 0.95 1.05 –10 +10 –50 +50 –10 +10 5 2.4 3.8 2.4 0.7 1.05 0.4 5 – ...
Page 4
... AD875 PIN DESCRIPTIONS Symbol Pin No. Type Name and Function D0 (LSB Least Significant Bit D1–D4 2–5 DO Data Bits 1 Through 4 D5–D8 8–11 DO Data Bits 5 Through 8 D9 (MSB Most Significant Bit UNR 46 DO Underrange Output OVR 47 DO Overrange Output TESTMODE 19 DI TESTMODE = LOW ...
Page 5
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD875 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
Page 6
... REFTF (V) (V) +1.6 +3.6 +2.0 +4.0 +2.1 +4.1 While the input impedance of the AD875 is quite high, the switched capacitor input structure results in a small dynamic input current. In order to prevent gain variations as a result of the input current, maintaining a source impedance of less than –6– +V Ø2 Ø1 Input Span (V) +2 ...
Page 7
... AIN The voltage drop across the internal resistor ladder determines 5 the input span of the AD875. The driving voltages required at 40 AIN the REFTF and REFBF pins are nominally +4 V and + respectively resulting input span. In order to maintain the requisite 2 V drop across the internal ladder, the external reference must be capable of typically providing current ...
Page 8
... REFBS Like any high resolution converter, the layout and decoupling of the reference is critical. The actual voltage digitized by the AD875 is relative to the reference voltages. In Figure 11, for example, the reference returns and the bypass capacitors are connected to the shield of the incoming analog signal. Disturbances in the ...
Page 9
... Q S +5V Figure 12. Divide-By-Two Clock Input Circuit The AD875 is designed to support a conversion rate of 15 MHz; running the part at slightly faster clock rates may be possible, although at reduced performance levels. Conversely, some slight performance improvements might be realized by clocking the AD875 at slower clock rates. ...
Page 10
... Separate analog and digital grounds should be joined together directly under the AD875. A solid ground plane under the AD875 is also acceptable if care is taken in the management of the power and ground return currents. A general “rule-of-thumb” for mixed signal layouts dictates that the return currents from digital circuitry should not pass through critical analog circuitry ...
Page 11
... A/D, thus requiring faster conversion rates. Similarly, area CCDs (CCDs which capture video information in two dimensions) operate at higher rates than linear (one dimensional) CCDs. BLACK LEVEL CONTROL SHA DC A/D CONVERTER GAIN RESTORE CDS GAIN CONTROL –11– AD875 DIGITAL PROCESSING ...
Page 12
... After allowing the SHAs to settle (250 ns), the R channel is digitized at the conversion rate of 12 MHz (83.3 ns). Next, the MUX is switched to the G channel, allowed to settle (83.3 ns), and digitized. The B channel is digitized similarly. While the B channel is converted, the R channel data becomes available at the output of the AD875 (due to the pipelined latency). The +5V – ...
Page 13
... HIGH SPEED SAMPLE-AND-HOLD AMPLIFIER (SHA) A sample-hold amplifier is often needed as part of a correlated double sampler or when high bandwidth inputs such as video signals are to be converted by the AD875. For fast, precise sampling required for video signals, an integrated solution such as the AD9101 track-and-hold amplifier is suggested for optimum performance ...
Page 14
... D 10 REFBF D C16 (OPTIONAL) A 100pF NOTE: ALL CAPACITOR VALUES ARE IN µF. NOTE THAT GROUND PLANE IS SOLID. D Figure 20. AD875 Evaluation Board Schematic Table III. Components List Description AD875 74HC04 74HC541 Resistor, 51 Resistor Resistor, 165 Resistor, 340 Resistor, 22 Resistor Network Capacitor, Electrolytic Capacitor, NPO Ceramic, 0 ...
Page 15
... Figure 21. Silkscreen Layer, Component Side PCB Layout Figure 22. Silkscreen Layer, Circuit Side PCB Layout REV. 0 –15– AD875 ...
Page 16
... AD875 Figure 23. Component Side PCB Layout Figure 24. Circuit Side PCB Layout –16– REV. 0 ...
Page 17
... REV. 0 Figure 25. Ground Layer PCB Layout Figure 26. Power Layer PCB Layout –17– AD875 ...
Page 18
... AD875 0.02 ± 0.008 (0.5 ± 0.2) SEATING PLANE 0.004 ± 0.002 (0.1 ± 0.05) ° °) (3.5 ± 3.5 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). TQFP 0.059 +0.008 –0.004 0.354 ± 0.008 (9.00 ± 0.2) SQ (1.50 +0.2 –0.1) 0.276 ± 0.004 (7.0 ± 0 0.055 ± 0.002 (1.40 ± 0.05 TOP VIEW PIN 1 ...
Page 19
–19– ...
Page 20
–20– ...