AT17C65 ATMEL Corporation, AT17C65 Datasheet
AT17C65
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AT17C65 Summary of contents
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Features • EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) • ...
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Table 1-1. Package 8-lead LAP 8-lead PDIP 8-lead SOIC 20-lead PLCC 20-lead SOIC 44-lead TQFP Notes: 2. Pin Configuration Figure 2-1. Figure 2-2. Figure 2-3. AT17LV65/128/256/512/010/002/040 2 AT17LV Series Packages AT17LV65/ AT17LV128/ AT17LV512/ AT17LV256 AT17LV010 Yes Yes Yes Yes Use ...
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Figure 2-4. Notes: Figure 2-5. Note: 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 20-lead PLCC CLK 4 (2) (WP1 ) NC 5 (1) (WP ) RESET/OE 6 (2) (WP2 ) This pin is only available on AT17LV65/128/256 devices. 2. This ...
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Figure 2-6. Notes: Figure 2-7. Note: AT17LV65/128/256/512/010/002/040 4 (1) 20-lead SOIC DATA CLK RESET/ This pinout only applies to AT17LV512/010/002 devices. 2. ...
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Figure 2-8. Block Diagram SER_EN (2) WP1 (2) WP2 POWER ON RESET Notes: 1. This pin is only available on AT17LV65/128/256 devices. 2. This pin is only available on AT17LV512/010/002 devices. 3. The CEO feature is not available on the ...
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Device Description The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration pro- cess and retrieve data from the configuration EEPROM without ...
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DATA Three-state DATA output for configuration. Open-collector bi-directional pin for programming. 4.2 CLK Clock input. Used to increment the internal address and bit counter for reading and programming. 4.3 WP1 WRITE PROTECT (1). Used to protect portions of memory ...
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A2 Device selection input, A2. This is used to enable (or select) the device during programming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor. 4.11 READY Open collector reset state indicator. Driven Low during power-up reset, ...
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Cascading Serial Configuration EEPROMs For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded configurators provide additional memory. After the last bit from the first configurator is read, the clock signal to the configurator ...
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Absolute Maximum Ratings* Operating Temperature................................... -40° +85° C Storage Temperature .................................... -65° +150° C Voltage on Any Pin with Respect to Ground ..............................-0. Supply Voltage (V ) .........................................-0.5V to +7.0V CC Maximum Soldering ...
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DC Characteristics V = 3.3V ± 10% CC Symbol Description V High-level Input Voltage IH V Low-level Input Voltage IL V High-level Output Voltage ( Low-level Output Voltage ( High-level Output Voltage (I ...
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AC Waveforms CE RESET/OE CLK T CE DATA 16. AC Waveforms when Cascading RESET/OE CE CLK T DATA LAST BIT T CEO AT17LV65/128/256/512/010/002/040 12 T SCE CAC CDF T OCK OCE T ...
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AC Characteristics V = 3.3V ± 10% CC Symbol Description ( Data Delay OE ( Data Delay CE (1) T CLK to Data Delay CAC T Data Hold from CE, OE, or CLK ...
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AC Characteristics ± 5% Commercial ± 10% Industrial CC CC Symbol Description ( Data Delay OE ( Data Delay CE (1) T CLK to Data Delay CAC ...
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Thermal Resistance Coefficients Package Type 8CN Leadless Array Package (LAP) 4 Plastic Dual Inline Package 8P3 (PDIP) Plastic Gull Wing Small Outline 8S1 (SOIC) Plastic Leaded Chip Carrier 20J (PLCC) Plastic Gull Wing Small Outline 20S2 (SOIC) Thin Plastic ...
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Figure 21-1. Ordering Code Voltage Size (Bits) 3.0V to 5.5V 65 128 256 512 010 002 040 8CN4 8-lead mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOID Packages 8P3 8-lead, 0.300" ...
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Ordering Information 22.1 Standard Package Options Memory Size (1) 64-Kbit (1) 128-Kbit (1) 256-Kbit (1) 512-Kbit (1) 1-Mbit (1) 2-Mbit Notes: 1. For operating 5V operating voltage, please refer to the corresponding AC and DC Characteristics. 2. For the ...
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Green Package Options (Pb/Halide-free/RoHS Compliant) Memory Size (1) 256-Kbit (1) 512-Kbit (1) 1-Mbit (1) 2-Mbit AT17LV002-10TQU (1) 4-Mbit AT17LV040-10TQU Note: 1. For operating 5V operating voltage, please refer to the corresponding AC and DC Characteristics. AT17LV65/128/256/512/010/002/040 18 Ordering Code ...
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Packaging Information 23.1 8CN4 – LAP Marked Pin1 Indentifier E Top View 0.10 mm TYP Bottom View Note: 1. Metal Pad Dimensions. 2. All exposed metal area shall have the following finished platings. ...
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PDIP Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with ...
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SOIC TOP VIEW e e SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 ...
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PLCC 1.14(0.045) X 45˚ B 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...
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SOIC 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 23 ...
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TQFP PIN 1 PIN 1 IDENTIFIER e C 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per ...
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Revision History Revision Level – Release Date H – March 2006 I – February 2008 2321I–CNFG–2/08 AT17LV65/128/256/512/010/002/040 History Added last-time buy for AT17LVXXX-10CC and AT17LVXXX-10CI. Removed -10SC, 10SI, -10TQC, -10TQI, -10BJC and -10BJI devices from ordering information. 25 ...
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