XC68EZ328PU16V Motorola, XC68EZ328PU16V Datasheet
XC68EZ328PU16V
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XC68EZ328PU16V Summary of contents
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... Integrated Processor Motorola, Incorporated Semiconductor Products Sector 6501 William Cannon Drive West Austin TX 78735-8598 MC68EZ328 UserÕs Manual Order this document by MC68EZ328UM/D (Motorola Order Number) Rev. 1, 11/98 ...
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... Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc ...
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... Signals GROUped by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 POWER and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.3 CLOCK and System Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.4 ADDRESS BUS Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.5 DATA BUS Signals 2-5 2.6 BUS CONTROL Signals 2-6 2.7 INTERRUPT CONTROLler Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.8 LCD CONTROLLER Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 MOTOROLA Title PREFACE SECTION 1 BASIC ARCHITECTURE SECTION 2 SIGNAL DESCRIPTIONS MC68EZ328 USERÕS MANUAL Page Number v ...
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... Changing the VCO Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.1.5 PLL Operation at System Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2.1 PLL Control Register 5-4 5.2.2 PLL Frequency Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.3 POWER CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.3.1 Operating the Power Control Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.3.2 Power Control Register 5-9 vi SECTION 3 SYSTEM CONTROL SECTION 4 CHIP-SELECT LOGIC SECTION 5 SECTION 6 INTERRUPT CONTROLLER MC68EZ328 USERÕS MANUAL MOTOROLA ...
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... Port F Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 7.2.7 Port G Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 8.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1.1 Playback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1.2 Tone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.1.3 D/A Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.2.1 PWM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.2.2 PWM Sample Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.2.3 PWM Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.2.4 PWM Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.3 Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 9.1 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 MOTOROLA SECTION 7 PARALLEL PORTS SECTION 8 PULSE-WIDTH MODULATOR SECTION 9 GENERAL-PURPOSE TIMER MC68EZ328 USERÕS MANUAL vii ...
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... UART Receiver Register 11-12 11.3.4 UART Transmitter Register 11-14 11.3.5 UART Miscellaneous Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 11.3.6 UART Non-Integer Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . 11-18 11.4 Non-Integer Prescaler Programming Example 11-19 12.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.1.1 Connecting the LCD Controller to an LCD Panel . . . . . . . . . . . . . . . . . 12-3 12.1.2 Controlling the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.1.3 Using Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 viii SECTION 10 SECTION 11 SECTION 12 LCD CONTROLLER MC68EZ328 USERÕS MANUAL MOTOROLA ...
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... RTC Hours, Minutes, and Seconds Register . . . . . . . . . . . . . . . . . . . . 13-4 13.2.2 RTC Alarm Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.2.3 Watchdog Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.2.4 RTC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.2.5 RTC Interrupt Status Register 13-7 13.2.6 RTC Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 13.2.7 Stopwatch Minutes Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 13.2.8 RTC Day Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 13.2.9 RTC Day Alarm Register 13-12 14.1 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 MOTOROLA SECTION 13 REAL-TIME CLOCK SECTION 14 DRAM CONTROLLER MC68EZ328 USERÕS MANUAL ix ...
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... Application Development Design Example . . . . . . . . . . . . . . . . . . . . . . . 15-12 16.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.1.1 Entering Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.1.2 Bootstrap Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.1.3 Setting Up the RS-232 Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.1.4 Changing the Speed of Communication . . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.2 System Initialization Programming Example . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.3 Application Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.4 Instruction Buffer Usage Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 16.5 Bootloader Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 x SECTION 15 IN-CIRCUIT EMULATION SECTION 16 BOOTSTRAP MODE MC68EZ328 USERÕS MANUAL MOTOROLA ...
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... Normal Mode and Emulation Mode Timing 18-14 18.3.15 Emulation Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14 18.3.16 Bootstrap Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15 MECHANICAL DATA AND ORDERING INFORMATION 19.1 Ordering Information 19-1 19.2 TQFP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.3 TQFP Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.4 PBGA Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 19.5 PBGA Package Dimensions 19-4 MOTOROLA SECTION 17 APPLICATION GUIDE SECTION 18 SECTION 19 MC68EZ328 USERÕS MANUAL xi ...
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... MC68EZ328 USERÕS MANUAL MOTOROLA ...
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... LCD Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12-2 LCD Interface Timing for 4-, 2-, and 1-Bit Data Widths 12-4 12-3 LCD Screen Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 12-4 Mapping Memory Data on the Screen . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 13-1 Real-Time Clock Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 14-1 DRAM Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14-2 DRAM Address Multiplexer Options 14-2 MOTOROLA Title MC68EZ328 USERÕS MANUAL Page Number xiii ...
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... LCD Controller and DRAM Controller Interface . . . . . . . . . . . . . . . . . . 14-4 14-4 Data Retention for the Reset Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 15-1 In-Circuit Emulation Module Block Diagram . . . . . . . . . . . . . . . . . . . . . 15-1 15-2 Typical Emulator Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15-3 Plug-in Emulator Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 15-4 Application Development System Design Example . . . . . . . . . . . . . . 15-12 16-1 Bootstrap Mode Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16-2 Bootloader Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 19-1 Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 xiv MC68EZ328 USERÕS MANUAL MOTOROLA ...
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... Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1-3 ProgrammerÕs Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 2-1 Signal Function Groups 2-3 6-1 Exception Vector Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6-2 Interrupt Vector Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 11-1 Non-Integer Prescaler Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11-2 Non-Integer Prescaler Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11-3 Selected Baud Rate Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 12-1 Gray-Scale Palette Options 12-7 13-1 Sampling Timer Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 MOTOROLA LIST OF TABLES Title MC68EZ328 USERÕS MANUAL Page Number xv ...
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... MC68EZ328 USERÕS MANUAL MOTOROLA ...
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... M68EZ328ADS UserÕs Manual , which is only available from our website. ¥ M68000 ProgrammerÕs Reference Manual (part number M68000PM/AD). You can go to the Motorola website at documents or you can contact your local sales office and request a printed version. The website also has application notes that may be useful to you. ...
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... MC68EZ328 USERÕS MANUAL MOTOROLA ...
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... This manual assumes you are familiar with 68K architecture. If you are not, get a copy of the M68000 UserÕs Manual (part number M68000UM/AD) and M68000 ProgrammerÕs Reference Manual (part number M68000PM/AD) from your local Motorola sales office. MOTOROLA MC68EZ328 USERÕS MANUAL ...
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... The next seven registers (A6ÐA0) and the user 1-2 PARALLEL I/O PORTS 68EC000 HCMOS STATIC CORE 68EC000 INTERNAL BUS LCD SPI PWM CONTROLLER PARALLEL I/O PORTS MC68EZ328 USERÕS MANUAL 16-BIT TIMER MODULE UART WITH INFRA-RED SUPPORT MOTOROLA ...
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... The status register contains the interrupt mask with seven available levels, as well as an extend (X), negative (N), zero (Z), overflow (V), and carry (C) condition code. The T bit indicates when the processor is in trace mode and the S bit indicates when supervisor or user mode. MOTOROLA ...
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... Absolute Words Program counter relative Long words Immediate Implied Table 1-1. Address Modes ADDRESS MODE = 8-Bit Offset (Displacement) = 16-Bit Offset (Displacement) MC68EZ328 USERÕS MANUAL SYNTAX Dn An xxx.W xxx.L d (PC (PC, Xn) 8 (An) (An)+ Ð(An) d (An (An, Xn) 8 #xxx #1Ð#8 SR/USP/SP/PC MOTOROLA ...
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... CMPM Compare memory CMPI Compare immediate DBcc Test cond, decrement and branch DIVS Signed divide DIVU Unsigned divide MOTOROLA Table 1-2. Instruction Set MNEMONIC MOVEM Move multiple registers MOVEP Move peripheral data MOVEQ Move quick MOVE from SR Move from status register MOVE to SR ...
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... Stop SUB Subtract SUBA Subtract address SUBI Subtract immediate SUBQ Subtract quick SUBX Subtract with extend SWAP Swap data register halves TAS Test and set operand TRAP Trap TRAPV Trap on overflow TST Test UNLK Unlink MC68EZ328 USERÕS MANUAL DESCRIPTION MOTOROLA ...
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... The serial peripheral interface (SPI) is mainly used for controlling external peripherals. The passed data is synchronized with the SPI clock and it is transmitted and received with the same SPI clock. The SPI module is only in master mode, which initiates SPI transfers from the MC68EZ328 to the peripheral. MOTOROLA MC68EZ328 USERÕS MANUAL Basic Architecture 1-7 ...
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... The memory map is a guide to all on-chip resources. Use the following figure and table as a guide when you configure your chip. The base address used in the table is 0xFFFFFF00 and 0xFFF000 from reset double-mapped bit is cleared in the system control register, 1-8 MC68EZ328 USERÕS MANUAL MOTOROLA ...
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... Table 1-3. SUPERVISOR MEMORY MAP MONITOR PROGRAM (DEFINED BY USER) SYSTEM MEMORY 0x1FFFFFFF 0xFFFC0000 EMULATOR MONITOR 0xFFFDFFFF 0xFFFFF000 MC68EZ328 REGISTER 0xFFFFF000 BOOTSTRAP Figure 1-4. MC68EZ328 System Memory Map MOTOROLA 512M RESERVED MC68EZ328 USERÕS MANUAL Basic Architecture USERÕS MEMORY MAP PROGRAM / DATA MEMORY 1-9 ...
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... RESET VALUE PAGE # 0x1C -2 Ñ Ñ 0x0000 -4 0x0000 -4 0x0000 -4 0x0000 -4 0x00E0 -5 0x0000 -5 0x0000 -5 0x0200 -5 0x0060 -8 0x2430 -4 0x0123 -5 Ñ Ñ 0x1F -9 0x00 -6 0x0000 -7 0x00FFFFFF -9 Ñ Ñ 0x00000000 -11 0x00000000 -16 0x00 -2 0x00 -2 0xFF -2 Ñ Ñ 0x00 -3 0x00 -3 0xFF -3 0xFF -3 0x00 -5 0x00 -5 0xFF -5 0xFF -5 0x00 -7 0x00 -7 MOTOROLA ...
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... TCN 0xFFFFF60A TSTAT 0xFFFFF800 SPIMDATA 0xFFFFF802 SPIMCONT 0xFFFFF900 USTCNT 0xFFFFF902 UBAUD 0xFFFFF904 URX 0xFFFFF906 UTX MOTOROLA DESCRIPTION 8 Port D Pull-Up Enable Register 8 Port D Select Register 8 Port D Polarity Register 8 Port D Interrupt Request Enable Register 8 Port D Keyboard Enable Register 8 Port D Interrupt Request Edge Register 8 ...
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... RESET VALUE PAGE # 0x0000 -16 0x0000 -18 0x00000000 -9 0xFF -10 0x03FF -10 0x01FF -11 0x0000 -11 0x0000 -12 0x0101 -12 0x7F -13 0x00 -13 0x00 -14 0x00 -14 0x00 -15 0x40 -15 0xFF -16 Ñ Ñ 00 -17 0xB9 -17 0x84 -18 0x0000 -18 0x00000000 -4 0x00000000 -5 0x0001 -5 0x00 -6 0x00 -7 0x00 -9 0x00 -11 0x0xxx -12 0x0000 -12 0x00000000 -6 0x00000000 -8 Ñ Ñ 0x00000000 -4 0x00000000 -4 MOTOROLA ...
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... Table 1-3. ProgrammerÕs Memory Map (Continued) ADDRESS NAME WIDTH 0xFFFFFD08 ICEMCCR 0xFFFFFD0A ICEMCMR 0xFFFFFD0C ICEMCR 0xFFFFFD0E ICEMSR 0xFFFFFExx Bootloader MOTOROLA DESCRIPTION 16 ICEM Control Compare Register 16 ICEM Control Mask Register 16 ICEM Control Register 16 ICEM Status Register Ñ Bootloader Microcode Space MC68EZ328 USERÕS MANUAL Basic Architecture ...
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... Basic Architecture 1-14 MC68EZ328 USERÕS MANUAL MOTOROLA ...
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... The terms ÒassertÓ and ÒassertionÓ are used to indicate that a signal is active or true, regardless of whether that level is represented by a high or low voltage. The terms ÒnegateÓ and ÒnegationÓ are used to indicate that a signal is inactive or false. MOTOROLA MC68EZ328 USERÕS MANUAL 2-1 ...
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... SYNTHESIZER AND POWER CONTROL REAL-TIME CLOCK LCD CONTROLLER INTERRUPT CONTROLLER PORTS C AND F PROCESSOR CONTROL, EMULATION AND BOOT STRAP MC68EZ328 USERÕS MANUAL PORT B DRAM CONTROLLER 16-BIT STATIC TIMER CORE SERIAL UART WITH PERIPHERAL PWM INFRA-RED INTERFACE SUPPORT PORT B PORT E PORT E MOTOROLA ...
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... Note: All pins, except EXTAL, support TTL levels. When EXTAL is used as an input clock, it needs a CMOS level. To ensure proper low-power operation, all inputs should be driven to CMOS level. More power is consumed when you use a TTL level to drive those inputs. MOTOROLA SIGNALS V , PLLV ...
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... This signal is inactive while the core is executing the reset instruction. When you are using an R/C circuit to generate this input signal to the MC68EZ328, the R/C circuit must be as close to the chip as possible. 2-4 32.768kHz OR 38.4kHz EXTAL XTAL 20pF MC68EZ328 USERÕS MANUAL MOTOROLA ...
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... MD[12:0]/A[13:1]ÑMultiplexed DRAM Bits 12-0 and Address Bits 13-1. These address output lines are multiplexed with the DRAM row and column address signals. The MD signal is selected on DRAM access cycles. MOTOROLA MC68EZ328 USERÕS MANUAL Signal Descriptions 2-5 ...
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... I schmitt trigger interrupt input. When it is configured as an interrupt input it can be programmed as a level high or level low trigger interrupt. 2-6 Register. If this bit is not enabled, the UCLK signal Registers. To generate a DTACK signal, refer to Section 6.1 Interrupt MC68EZ328 USERÕS MANUAL Processing. The pin defaults MOTOROLA ...
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... LCONTRAST/PF0ÑLCD Contrast and Port F Bit 0. This output controls the pulse-width modulator (PWM) inside the LCD controller to adjust the supply voltage to the LCD panel. This pin can also be programmed as an I/O port. This pin defaults to a PFx input signal pulled high. MOTOROLA MC68EZ328 USERÕS MANUAL Signal Descriptions 2-7 ...
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... SPMRXD/PE1ÑSPI Master Receive Data and Port E Bit 1. This pin is the input to the master SPI shift register. This pin defaults to a general-purpose PE1 input signal. 2-8 Register. When it is programmed as parallel I/O, it Section 11.3.4 UART Transmitter Register MC68EZ328 USERÕS MANUAL for more MOTOROLA ...
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... It cannot be used to select 16-bit data bus memory devices. EMUCS is not only activated in emulation mode, but in normal and bootstrap modes as well. See for more information about EMUCS operation. This pin defaults to an EMUCS signal. MOTOROLA MC68EZ328 USERÕS MANUAL Signal Descriptions ...
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... Signal Descriptions 2-10 MC68EZ328 USERÕS MANUAL MOTOROLA ...
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... The BETO bit in the system control register is set after a bus time-out, which could be caused by a write-protect violation. The software watchdog timer resets the MC68EZ328 if enabled and not cleared or disabled before reaching terminal count. The software watchdog timer is enabled at reset. MOTOROLA MC68EZ328 USERÕS MANUAL 3-1 ...
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... A privilege violation has occurred. BETENÑBus-Error Time-Out Enable This control bit enables the bus error timer Disable the bus error timer Enable the bus error timer. 3 PRV BETEN SO 0x1C 0x(FF)FFF000 MC68EZ328 USERÕS MANUAL DMAP RESERVED WDTH8 MOTOROLA ...
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... The on-chip registers are mapped at 0xFFFFF000Ð0xFFFFFFFF and 0xFFF000Ð0xFFFFF. Bit 1ÑReserved This bit is reserved and reads 0. WDTH8Ñ8-Bit Width Select This control bit allows the D[7:0] pins to be used for port B input/output Not an 8-bit system 8-bit system. MOTOROLA MC68EZ328 USERÕS MANUAL System Control 3-3 ...
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... System Control 3-4 MC68EZ328 USERÕS MANUAL MOTOROLA ...
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... The basic chip-select model allows the chip-select output signal to assert in response to an address match. The signals are asserted externally shortly after the internal AS signal goes low. The address match is described in terms of a group base address register and a MOTOROLA ROM, SRAM, FLASH MEMORY CHIP-SELECT ROM, SRAM, FLASH MEMORY CHIP-SELECT ...
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... However, a certain area of this chip-select controlled area can be programmed as read/ write, which provides optimal memory use, as shown in Figure 4-2. This area can be defined by programming the UPSIZ bits in the CSB, CSC, and CSD registers to between 32K and 256K. 4-2 MC68EZ328 USERÕS MANUAL MOTOROLA ...
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... A logic 0 on the BUSW pin sets the boot deviceÕs data bus to 8 bits wide and a logic 1 sets bits wide. At reset, the data bus port size for CSA0 and the data width of the boot ROM device are determined by the state of BUSW. The other chip-selects are initialized to MOTOROLA UNPROTECTED MEMORY (READ/WRITE) CSB0 ...
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... CSGBA register and CSA1 returns the selected memory size apart from CSA0. CSGBA-CSGBD BIT FIELD GBA28 GBA27 GBA26 GBA25 RESET ADDR 4 GBA24 GBA23 GBA22 GBA21 GBA20 GBA19 0x0000 0x(FF)FFF100, 102, 104, 106 MC68EZ328 USERÕS MANUAL GBA18 GBA17 GBA16 GBA15 GBA14 Ñ MOTOROLA ...
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... CSB AND CSC BIT UPSIZ FIELD RO SOP ROP 1 RESET ADDR CSD BIT UPSIZ FIELD RO SOP ROP 1 RESET ADDR MOTOROLA Ñ FLASH BSW WS2 0x0000 0x(FF)FFF110 UPSIZ Ñ FLASH BSW WS2 0 0x0000 0x(FF)FFF112 AND 0x114 ...
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... This bit controls combining RAS0 and RAS1 memory space to generate RAS0. When this bit is set to 1, RAS1 can be used as a general-purpose I/O signal RAS0 to RAS0 memory space RAS0 covers both RAS0 and RAS1 memory space B. 4-6 for more information. Section 3.2.1 System Control Register MC68EZ328 USERÕS MANUAL for more MOTOROLA ...
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... Two wait states. 011 = Three wait states. 100 = Four wait states. 101 = Five wait states. 110 = Six wait states. 111 = External DTACK. Note: When using the external DTACK signal, you must configure the BUSW/DTACK/PG0 pin. MOTOROLA MC68EZ328 USERÕS MANUAL Chip-Select Logic 4-7 ...
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... You can also use the external logic (DTACK) to have longer wait-states. EMUCS is only valid for the 0xFFFC0000-0xFFFDFFFF memory location. EMUCS BIT FIELD RESET ADDR 4 Ñ WS2 0x0060 0x(FF)FFF118 MC68EZ328 USERÕS MANUAL WS1 WS0 Ñ MOTOROLA ...
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... START move.b #0x00,PBSel move.w #0x0000,BASEA move.w #0x8081,CSA move.w #0x2000,BASEB MOTOROLA internal registers base address group A base register group B base register group C base register group D base register group A chip select register group B chip select register group C chip select register group D chip select register ...
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... CSB0 0x4000000-0x403ffff,read/write,16-bit,1 wait-state,256K * CSB1 0x4040000-0x407ffff,read/write,16-bit,1 wait-state,256K * CSC0 0x4080000-0x4087fff,read/write,flash,16-bit,1 wait-state, 32K * CSC1 0x4088000-0x408ffff,read/write,flash,16-bit,1 wait-state, 32K * CSD0 disabled * CSD1 disabled 4-10 read/write,16-bit,1 wait-state,256K set base addrs 0x4080000 read/write,flash,16-bit,1 ws,32K config CSC,CSD as non-DRAM memory type MC68EZ328 USERÕS MANUAL MOTOROLA ...
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... The PLL, used in conjunction with the power control block, provides an efficient power-control mechanism for the MC68EZ328 microprocessor, as illustrated in Figure 5-1. WAKEUP EXTAL CRYSTAL OSCILLATOR XTAL MOTOROLA MPU BUS MPU INTERFACE VCO PHASE-LOCKED PRESCALER LOOP Figure 5-1. PLL Block Diagram MC68EZ328 USERÕ ...
Page 58
... When the MC68EZ328 is awakened from sleep mode by a wake-up event, the PLL achieves lock within 1ms. The crystal oscillator is always on after initial power-up, so the crystal startup time is not a factor. The master clock starts operating once the PLL achieves lock. 5-2 Frequency. MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 59
... After the rte instruction in the wake-up service routine, the CPU returns and starts execution on the instruction following the stop instruction. The instruction sequence below illustrates a typical shut-down sequence. It assumes that all peripherals have been shut down before the PLL is stopped. MOTOROLA Phase-Locked Loop and Power Control ;P and Q value of new frequency ;PLL Control Register ...
Page 60
... These bits are reserved and should be set to 0. 5-4 ;Set PLL to full running ;look for 32K clock low ;look for 32K clcok high ;Stop PLL ;enable wake up event SYSCLK SEL RESERVED 0x2420 0x(FF)FFF200 MC68EZ328 USERÕS MANUAL PRES CLKEN DISPLL RESERVED C MOTOROLA ...
Page 61
... This bit protects the ÒPÓ and ÒQÓ counter values from additional writes. After this bit is set by software, the frequency select register cannot be written. Only a reset clears this bit. MOTOROLA Phase-Locked Loop and Power Control for a description of the preferred method for system clock ...
Page 62
... An interrupt from the keyboard, for example, disables the power controller and runs the CPU clock. When the software finishes servicing the task, the power controller can again disable the clock and reduce power consumption. Clock control is in increments of approximately 3% (1/31). 5-6 MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 63
... The power controller burst period is 31 CLK32 periods or approximately 1msec. Notice that the LCD DMA controller has access to the bus at all times and the SYSCLK (master clock to all peripherals) is continuously active. MOTOROLA Phase-Locked Loop and Power Control MPU INTERFACE BURST WIDTH ...
Page 64
... LCD controller, are not affected by the power control module. 5.3.1.3 SLEEP MODE. The PLL is disabled in sleep mode. Only the 32kHz clock works to keep the real-time clock operational. Wake-up events activate the PLL and the system clock starts operating after 1msec. 5-8 MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 65
... You should reenable the power control module that services the interrupt. 00000 = 0/31 duty-cycle. 00001 = 1/31 duty-cycle. 00010 = 2/31 duty-cycle. ¥ ¥ ¥ 11111 = 31/31 duty-cycle. MOTOROLA Phase-Locked Loop and Power Control 0x001F 0x(FF)FFF207 MC68EZ328 USERÕS MANUAL ...
Page 66
... Phase-Locked Loop and Power Control 5-10 MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 67
... The core processor responds to the interrupt request by executing an interrupt acknowledge bus cycle after the completion of the current instruction. 3. The interrupt controller recognizes the interrupt acknowledge (IACK) cycle and places the interrupt vector for that interrupt request onto the core processor bus. MOTOROLA MC68EZ328 USERÕS MANUAL 6-1 ...
Page 68
... All interrupts are maskable. Writing bit in the interrupt mask register disables that interrupt interrupt is masked, you can find out its status in the interrupt pending register. 6 EC000 CORE NO 4 MC68EZ328 USERÕS MANUAL 0xFFF..... INTERRUPT HANDLER MOTOROLA ...
Page 69
... 10Ð17 16Ð 100 1A 26 104 1B 27 108 1C 28 112 1D 29 116 1E 30 120 1F 31 124 MOTOROLA SPACE HEX 000 SP 004 SP 008 SD 00C SD 010 SD 014 SD 018 SD 01C SD 020 SD 024 SD 028 SD 02C SD 030 SD 034 SD 038 SD 03C ...
Page 70
... NOTES: 1.Vector numbers 12Ð14, 16Ð23, and 48Ð63 are reserved for future enhancements by Motorola. None of your peripheral devices should be assigned to these numbers. 2.Reset vector 0 requires four words, unlike the other vectors which only require two words, and it is located in the supervisor program space. ...
Page 71
... All interrupts are maskable by the interrupt controller interrupt is masked, its status can still be accessed in the interrupt pending register (IPR). MOTOROLA MC68EZ328 USERÕS MANUAL Interrupt Controller 6-5 ...
Page 72
... CPU as an uninitialized interrupt, which has the interrupt vector 0x3C. IVR BIT 7 6 FIELD 6-6 INTERRUPT VECTOR NUMBER Level 7 xxxxx111 Level 6 xxxxx110 Level 5 xxxxx101 Level 4 xxxxx100 Level 3 xxxxx011 Level 2 xxxxx010 Level 1 xxxxx001 interrupt vector register VECTOR MC68EZ328 USERÕS MANUAL RESERVED MOTOROLA ...
Page 73
... Positive polarity means that an interrupt occurs when the signal goes from logic level low to logic level high Negative polarity Positive polarity. MOTOROLA 0x00 ...
Page 74
... IRQ2 bit in the interrupt status register to clear this interrupt. When this bit is low, IRQ2 is a level-sensitive interrupt. In this case, you must clear the external source of the interrupt Level-sensitive interrupt Edge-sensitive interrupt. 6-8 MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 75
... At reset, all the interrupts are masked and all the bits in this register are set to 1. IMR BIT FIELD RESERVED RESET BIT FIELD RESERVED RESET ADDR MOTOROLA MEMIQ MSAM 0x00FFFFFF MINT3 MINT2 MINT1 MINT0 ...
Page 76
... Enable IRQ2 interrupt Mask IRQ2 interrupt. MIRQ1ÑMask IRQ1 Interrupt 0 = Enable IRQ1 interrupt Mask IRQ1 interrupt. Bits 15Ð12ÑReserved These bits are reserved and should be set to 0. MINT3ÑMask External INT3 Interrupt 0 = Enable INT3 interrupt Mask INT3 interrupt. 6-10 MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 77
... Mask serial peripheral interface interrupt. 6.6.4 Interrupt Status Register During the interrupt service, the interrupt handler can determine the source of the interrupt by examining the interrupt status register (ISR). When the bits in this register are set, they MOTOROLA MC68EZ328 USERÕS MANUAL Interrupt Controller 6-11 ...
Page 78
... INT3 INT2 INT1 INT0 PWM KB 0x00000000 0x(FF)FFF30C MC68EZ328 USERÕS MANUAL Section 10.2.2 SPIM Register, and Section 8.2 RES IRQ5 IRQ6 IRQ3 IRQ2 IRQ1 RES RTC WDT UART TMR SPI for more MOTOROLA ...
Page 79
... IRQ1 signal is set level-sensitive interrupt, you must clear the source of the interrupt. If IRQ1 is set edge-triggered interrupt, you must clear the interrupt by writing this bit (writing a 0 has no effect level 1 interrupt is pending level 1 interrupt is pending. MOTOROLA MC68EZ328 USERÕS MANUAL Interrupt Controller 6-13 ...
Page 80
... When it is programmed as edge-triggered, it can only be cleared by writing the port D register, which is described INT2 interrupt is pending INT2 interrupt is pending. 6-14 Section 7.2.4 Port D Registers. Section 7.2.4 Port D Registers. Section 7.2.4 Port D Registers. Section 7.2.4 Port D Registers. Section 7.2.4 Port D Registers. Section 7.2.4 Port D Registers. MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 81
... A real-time clock interrupt is pending. WDTÑWatchdog Timer Interrupt Request This bit indicates that a watchdog timer interrupt is pending. This is a level 4 interrupt watchdog timer interrupt is pending watchdog timer interrupt is pending. MOTOROLA Section 7.2.4 Port D Registers. Section 7.2.4 Port D Registers. MC68EZ328 USERÕS MANUAL ...
Page 82
... Section 10.2.2 SPIM Control/Status EMIQ SAM 0x00000000 INT3 INT2 INT1 INT0 PWM KB 0x00000000 0x(FF)FFF310 MC68EZ328 USERÕS MANUAL RES IRQ5 IRQ6 IRQ3 IRQ2 IRQ1 RES RTC WDT UART TMR SPI MOTOROLA ...
Page 83
... A level 3 interrupt is pending. IRQ2ÑInterrupt Request Level 2 This bit indicates that an external device has requested an interrupt on level 2. If the IRQ2 signal is set level-sensitive interrupt, you must clear the source of the interrupt. If MOTOROLA MC68EZ328 USERÕS MANUAL Interrupt Controller for more information. ...
Page 84
... This bit indicates that a level 4 interrupt has occurred usually for a keyboard interface. When it is programmed as edge-triggered, it can only be cleared by writing the port D register. See Section 7.2.4 Port D Registers INT1 interrupt is pending INT1 interrupt is pending. 6-18 for more information. for more information. for more information. MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 85
... No UART service request is pending UART service is needed. TMRÑTimer Interrupt Status This bit indicates that a timer event has occurred. This is a level 6 interrupt timer event has occurred timer event has occurred. MOTOROLA for more information. MC68EZ328 USERÕS MANUAL Interrupt Controller 6-19 ...
Page 86
... MC68EZ328 system. With the special design circuitry inside, this pen interrupt supports both pen-down and pen-up interrupts. The polarity of the pen interrupt can be set by programming the POL5 bit of the interrupt control register. 6-20 Section 10.2.2 SPIM Control/Status MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 87
... RXD signal. In this case, the Òoutput enable from moduleÓ input is negated and the Òdata from moduleÓ signal is not used. The Òdata to moduleÓ signal is connected to the SPMRXD input signal. MOTOROLA PULL-UP PAD BUFFER ...
Page 88
... Register. At reset, the data lines are connected to the pins 0x0000 0xFFFFF400 AND 0x401 PU3 PU2 PU1 PU0 0xFF00 0xFFFFF402 MC68EZ328 USERÕS MANUAL RESERVED MOTOROLA ...
Page 89
... The Port B registers are general-purpose I/O registers. They consist of the following: ¥ Port B direction register (PBDIR) ¥ Port B data register (PBDATA) ¥ Port B pull-up enable register (PBPUEN) ¥ Port B select register (PBSEL) Port B is multiplexed with the signals in the following table. MOTOROLA BIT PORT DEDICATED FUNCTIONS FUNCTIONS ...
Page 90
... D7 D6 0x0000 0xFFFFF408 AND 0x409 PU3 PU2 PU1 PU0 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 0xFFFF 0xFFFFF40A AND 0x40B MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 91
... As on the other ports, each bit on Port C can be individually configured. Port C is primarily multiplexed with the LCD controllerÕs signals. These pins can be programmed as I/O when you are not using the LCD controller and they can be reclaimed as I/O ports. See for more information. MOTOROLA BIT PORT DEDICATED ...
Page 92
... D7 D6 0x0000 0xFFFFF410 AND 0x411 PD3 PD2 PD1 PD0 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 0xFFFF 0xFFFFF412 AND 0x413 MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 93
... Port D generates nine interrupt signals. Eight of these interrupts are generated by the bits of each port and one is the logical-OR of all eight bits. The individual interrupt bits can be masked on a bit-by-bit basis. You must enable or disable the OR interrupt in the KBEN bit of the PDKBEN register. You can configure the individual MOTOROLA PULL-UP IRQ EDGE 0 ...
Page 94
... DIR2 DIR1 DIR0 D7 D6 0xFFF0 0xFFFFF418 AND 0x419 PU3 PU2 PU1 PU0 SEL7 SEL6 0xFFF0 0xFFFFF41A AND 0x41B MC68EZ328 USERÕS MANUAL SEL5 SEL4 Ñ Ñ Ñ Ñ MOTOROLA ...
Page 95
... The Dx bits are reset to 0 when the DIRx bits are low. PUxÑPull-Up 7Ð0 These bits enable the pull-up resistors on the port. The pull-ups are enabled at reset Pull-up resistors are disabled Pull-up resistors are enabled. MOTOROLA ...
Page 96
... The keyboard interrupt is enabled. 7.2.5 Port E Registers The Port E registers are general-purpose I/O registers. They consist of the following: ¥ Port E direction register (PEDIR) ¥ Port E data register (PEDATA) ¥ Port E pull-up enable register (PEPUEN) ¥ Port E select register (PESEL) 7-10 MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 97
... PU4 RESET ADDR DIRxÑDirection 7Ð0 These bits control the direction of the pins. They reset to 0 and have no function when the SELx bits are low The pins are inputs The pins are outputs. MOTOROLA BIT PORT DEDICATED FUNCTIONS FUNCTIONS 0 Bit 0 SPMTXD ...
Page 98
... Port F is multiplexed with address lines A[20:23] and dedicated functions, as shown in the following table. Unused address pins can serve as parallel I/ bit-by-bit basis. 7-12 BIT PORT DEDICATED FUNCTIONS FUNCTIONS 0 Bit 0 LCONTRAST 1 Bit 1 IRQ5 2 Bit 2 CLKO 3 Bit 3 A20 4 Bit 4 A21 5 Bit 5 A22 6 Bit 6 A23 7 Bit 7 CSA1 MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 99
... These bits enable the pull-up resistors at reset on the port Pull-up resistors are disabled Pull-up resistors are enabled. PDxÑPull-Down 6Ð3 These bits enable the pull-down resistors at reset on the port Pull-down resistors are disabled Pull-down resistors are enabled. MOTOROLA ...
Page 100
... A0 can be used as I/O when the system is 16-bit and there is no pull-up after reset for this pin. 7-14 BIT PORT DEDICATED FUNCTION FUNCTIONS 0 Bit 0 BUSW/DTACK 1 Bit Bit 2 EMUIRQ 3 Bit 3 HIZ/P/D 4 Bit 4 EMUCS 5 Bit 5 EMUBRK 6 Bit 6 Ñ 7 Bit 7 Ñ MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 101
... The actual value on the pin is reported when these bits are read, regardless of whether they are input or output. The Dx bits reset to 0. PUxÑPull-Up 5Ð0 These bits enable the pull-up resistors at reset on the port Pull-up resistors are disabled Pull-up resistors are enabled. MOTOROLA Ñ ...
Page 102
... Parallel Ports SELxÑSelect 5Ð0 These bits allow you to select whether the internal chip function or I/O port signals are connected to the pins The internal chip function pins are connected The I/O port function pins are connected. 7-16 MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 103
... PERIOD field of the PWMP register is at its maximum value. So for 16kHz reconstruction, PCLK is 4.096MHz. For human voice quality sound, the reconstruction frequency is either 8 or 16kHz. Figure 8-2 illustrates how variable width pulses affect an audio waveform. MOTOROLA MPU INTERFACE 5-BYTE FIFO PCLK ...
Page 104
... PWMO signal. It produces a different DC level when you program the PWMS register. It then becomes a D/A converter. 8.2 PROGRAMMING MODEL 8.2.1 PWM Control Register The pulse-width modulator control register (PWMC) controls how the overall pulse-width modulator operates. You can also find out the status of the FIFO with this register. 8-2 MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 105
... The PWM interrupt is enabled. FIFOAVÑFIFO Available This bit indicates that the FIFO is available for at least one byte of sample data. Data bytes can be loaded into the FIFO as long as this bit is set. If the FIFO is loaded while this bit is cleared, the write will be ignored. MOTOROLA ...
Page 106
... This method will shift the carrier from an audible 8kHz to a less-sensitive 16kHz frequency. This feature can reduce CPU loading and software overhead on a higher reconstruction rate. 8-4 MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 107
... SAMPLE0 field. When used with single 8-bit samples, data must be written to this byte. 8.2.3 PWM Period Register The read/write pulse-width modulator period (PWMP) register controls the pulse-width modulator period. When the counter value matches PERIOD +1, the counter is reset to start MOTOROLA ...
Page 108
... PWM_buffer_size;// measured in words #define PWMIRQ0x00000080 #define PWM_IRQ_ENABLE 0x40 #define PWM_ENABLE 0x10 #define PWM32KHZ0x00 8 PERIOD 0xFE 0x(FF)FFF504 COUNT 0x0000 0x(FF)FFF505 MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 109
... PWM_IRQ_Service() { volatile charstatus; // read the PWMControl register to clear the IRQ status = *PWMControl; // load the next 4 sample bytes into the FIFO *PWMsample = *next_PWM_sample_pair++; if(--PWM_buffer_size == 0) *PWMControl = 0x00; *PWMsample = *next_PWM_sample_pair++; PWM_buffer_size = PWM_buffer_size -2; if(--PWM_buffer_size <= 0) *PWMControl = 0x00; } MOTOROLA MC68EZ328 USERÕS MANUAL Pulse-Width Modulator 8-7 ...
Page 110
... Pulse-Width Modulator 8-8 MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 111
... The prescaler can divide the input clock by a value between 1 and 256. While CLK32 is selected as the clock source, the timer operates even while the PLL is in sleep mode. MOTOROLA PCLK ¸ 16 ...
Page 112
... The timer control (TCTL) register controls the overall operation of the timer. TCTL BIT FIELD RESERVED RESET ADDR Bits 15Ð9ÑReserved These bits are reserved and read 0. 9 FRR CAP 0x0000 0x(FF)FFF600 MC68EZ328 USERÕS MANUAL IRQ OM CLKSOURCE TEN EN MOTOROLA ...
Page 113
... Stop count (clock disabled). 001 = SYSCLK to prescaler. 010 = SYSCLK divided prescaler. 011 = TIN to prescaler. 1xx = 32kHz clock to prescaler. TENÑTimer Enable This bit enables the general-purpose timer Timer is disabled (counter reset to 0x0000 Timer is enabled. MOTOROLA MC68EZ328 USERÕS MANUAL General-Purpose Timer 9-3 ...
Page 114
... TCR BIT FIELD RESET ADDR 9 0x0000 0x(FF)FFF602 COMPARE VALUE 0xFFFF 0x(FF)FFF604 CAPTURE VALUE 0x0000 0x(FF)FFF606 MC68EZ328 USERÕS MANUAL PRESCALER MOTOROLA ...
Page 115
... CAPTÑCapture Event This bit indicates when a capture event occurs capture event occurred capture event has occurred. COMPÑCompare Event This bit indicates when a compare event occurs compare event occurred compare event has occurred. MOTOROLA COUNT ...
Page 116
... General-Purpose Timer 9-6 MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 117
... It provides the clock for data transfer and can only function as a master device fully compatible with the serial peripheral interface on MotorolaÕs 6805 and 68HC11 microprocessors. Figure 10-1 illustrates the serial peripheral interface masterÕs block diagram. ...
Page 118
... The most-significant bit is output on the first rising SPMCLK edge. Polarity inverts SPMCLK, but does not change the edge-triggered events 10-2 SPMCLK n-1 n-2 n n-2 n-1 n-3 n Section 7.2.5 Port E Registers MC68EZ328 USERÕS MANUAL ... ... ... ... for more information. Section 6.6.3 MOTOROLA ...
Page 119
... MSB-justified. For example, if the exchange length is 10 bits, the first bit presented to the external device will be Bit 9, followed by the remaining bits. Note: Writes to this field are ignored while the ENABLE bit is clear or while the XCH bit is set. This field contains unknown data read while the XCH bit is set. MOTOROLA ...
Page 120
... The MSPI bit of the interrupt mask register must be cleared for the interrupt to be posted to the core. See Section 6.6.3 Interrupt Mask Register 10 ENABL RESERVED XCH IRQ IRQ EN E 0x0000 0x(FF)FFFFF802 for more information. This bit remains MC68EZ328 USERÕS MANUAL PHA POL BIT COUNT MOTOROLA 0 ...
Page 121
... PROGRAMMING EXAMPLE The following software code demonstrates a 10-bit exchange with the SPMCLK at 1MHz (SYSCLK = 16MHz). The interrupt bit is polled, which means no interrupt is posted to the processor. MOTOROLA MC68EZ328 USERÕS MANUAL Serial Peripheral Interface Master 10-5 ...
Page 122
... PHA=0, POL=0, 10-bit, divide by 16 clk enable SPIM module load data to be transmitted trigger the exchange poll the IRQ bit not set read it again clear the interrupt bit disable the SPIM read the data from the external device MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 123
... Serial data is transmitted and received at standard bit rates using the internal baud rate generator. For those applications that need other bit rates clock mode is available that allows you to provide a data-bit clock. Figure 11-1 illustrates a high-level block diagram of the UART module. MOTOROLA MC68EZ328 USERÕS MANUAL 11-1 ...
Page 124
... The polarity of transmitted pulses and expected receive pulses can be inverted so that 11-2 RX RECEIVER FIFO TX TRANSMITTER FIFO BAUD RATE MC68EZ328 USERÕS MANUAL RXD TXD UCLK CTS RTS bit-time pulses and ones remain MOTOROLA ...
Page 125
... This pin is then connected to the far-end transmitterÕs CTS pin. When the receiver FIFO is nearly full (four slots are remaining), which indicates a pending FIFO overrun, this pin is negated (high). When MOTOROLA Universal Asynchronous Receiver/Transmitter MC68EZ328 USERÕS MANUAL ...
Page 126
... The SENDBREAK bit of the UTX register is used to generate a Break character (continuous zeros). Use the following procedure to send the minimum number of valid Break characters. 1. Make sure the BUSY bit in the UTX register is set. 2. Wait until the BUSY bit goes low. 11-4 MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 127
... If the software has a longer latency time, the FIFO HALF interrupt of the URX register can be used. This interrupt is generated when no more than four empty bytes remain in the FIFO. If you do not need the FIFO, you should use the DATA READY MOTOROLA Universal Asynchronous Receiver/Transmitter MC68EZ328 USERÕS MANUAL ...
Page 128
... CLKM bit of the USTCNT register is high, CLK1 is directly sourced by the CLK16 signal. 11-6 INTEGER PRESCALER NON-INTEGER PRESCALER DIVIDE DIVIDER BY n (DIVIDE binary divider with eight tapsÑ 16, 32, 64, MC68EZ328 USERÕS MANUAL 0 1 IRCLK CLK16 1 0 CLK1 0 1 MOTOROLA n ...
Page 129
... With a 38.400kHz crystal, the baud clocks are generated with 0% error. Table 11-3 contains the values that you should use in the UBAUD register for these system frequencies. Table 11-3. Selected Baud Rate Settings BAUD RATE MOTOROLA Universal Asynchronous Receiver/Transmitter 115.200kHz bit time at any selected ...
Page 130
... PEN ODD STOP 8/7 ODEN CTSD 0x0000 0x(FF)FFF900 MC68EZ328 USERÕS MANUAL RXFE RXHE RXRE TXEE TXHE TXAE MOTOROLA ...
Page 131
... One stop bit is transmitted Two stop bits are transmitted. 8/7Ñ8- or 7-Bit This bit controls the character length. The transmitter ignores Data Bit 7 and the receiver sets 7-bit transmit-and-receive character length 8-bit transmit-and-receive character length. MOTOROLA Universal Asynchronous Receiver/Transmitter MC68EZ328 USERÕS MANUAL 11-9 ...
Page 132
... TXHEÑTransmitter Half Empty Enable When this bit is high, it enables an interrupt when the transmit FIFO is less than half full. When it is low, the TX HALF interrupt is disabled. This bit resets HALF interrupt is disabled HALF interrupt is enabled. 11-10 MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 133
... UCLK is an input UCLK is an output. BAUD SRCÑBaud Source This bit controls the clock source to the baud rate generator Baud rate generator source is a system clock Baud rate generator source is a UCLK pin (UCLKDIR must be set to 0). MOTOROLA Universal Asynchronous Receiver/Transmitter ...
Page 134
... This read-only bit indicates that the receiver FIFO is full and may generate an overrun. This bit generates a maskable interrupt Receiver FIFO is not full Receiver FIFO is full. 11- PARIT FRAM Y OVRU E BREAK N ERRO ERRO R R 0X0000 0x(FF)FFF904 MC68EZ328 USERÕS MANUAL DATA MOTOROLA ...
Page 135
... PARITY ERROR will also be set. This bit is updated and valid with each character read from the FIFO The character is not a break character The character is a break character. MOTOROLA Universal Asynchronous Receiver/Transmitter MC68EZ328 USERÕS MANUAL 11-13 ...
Page 136
... This read-only bit indicates that the transmitter FIFO has at least one slot available for data. This bit generates a maskable interrupt Transmitter does not need data Transmitter needs data. 11- CTS CTS BUSY CTS STAT DELTA 0x0000 0x(FF)FFF906 MC68EZ328 USERÕS MANUAL DATA MOTOROLA ...
Page 137
... This write-only field is the parallel transmit-data input. In 7-bit mode, Bit 7 is ignored and in 8-bit mode, all of the bits are used. Data is transmitted least-significant bit first. A new character is transmitted when this field is written and have passed through the FIFO. MOTOROLA Universal Asynchronous Receiver/Transmitter for a description of how to generate a break. ...
Page 138
... Normal receiver operation Internally connects the transmitter output to the receiver input. 11- BAUD IR RTS 0 0 RTS RESET TEST CONT 0x0000 0x(FF)FFF908 MC68EZ328 USERÕS MANUAL IRDA IRDA LOOP POL POL MOTOROLA ...
Page 139
... No infra-red loop Connect the infra-red transmitter to an infra-red receiver. RX POLÑReceive Polarity This bit controls the polarity of the received data Normal polarity (1 = idle Inverted polarity (0 = idle). MOTOROLA Universal Asynchronous Receiver/Transmitter MC68EZ328 USERÕS MANUAL 11-17 ...
Page 140
... Step = 1. 11- SELECT 0x0000 0x(FF)FFF90A 127 steps. 128 128 steps steps steps steps steps steps MC68EZ328 USERÕS MANUAL STEP VALUE MOTOROLA ...
Page 141
... Then you should round the nearest integer value and convert this value to the hex equivalent: 89 (decimal (hex) The actual divisor will be 5.390625, which will produce a frequency of 3.075823MHz (0.12% above the preferred frequency). MOTOROLA Universal Asynchronous Receiver/Transmitter MC68EZ328 USERÕS MANUAL 11-19 ...
Page 142
... Universal Asynchronous Receiver/Transmitter 11-20 MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 143
... The LCD controller consists of MPU interface registers, control logic, a screen DMA controller, line buffer, cursor logic, frame rate control, and an LCD panel interface. Figure 12-1 illustrates how these blocks are organized in the LCD controller. MOTOROLA MC68EZ328 USERÕS MANUAL 12-1 ...
Page 144
... LCD gray palette mapping register (LGPMR). 12-2 DMACLK PIXEL CLOCK MPU INTERFACE LCD CONTROLLER REGISTERS LCD INTERFACE CONTROL LOGIC FRAME RATE CONTROL SCREEN DMA CURSOR LOGIC LINE BUFFER PWM MC68EZ328 USERÕS MANUAL LCD DRIVER LCD BIAS VOLTAGE CONTROL MOTOROLA ...
Page 145
... LFLM signal marks the first line of the displayed page. The LCD controller is designed to support most monochrome LCD panels. Figure 12-2 illustrates the LCD interface timing for 1-, 2-, and 4-bit LCD data bus operation. The LLP MOTOROLA for more information. Section 12.2.10 LCD Polarity Configuration Register Section 12 ...
Page 146
... The best efficiency is achieved when the screen width is a multiple of the DMA controllerÕs 16-bit bus width. 12-4 LINE 3 LINE 4-BIT LCD DATA BUS (PBSIZ = 10) [4,0] [8,0] [76,0] [80,0] [5,0] [9,0] [77,0] [81,0] [6,0] [10,0] [78,0] [82,0] [7,0] [11,0] [79,0] [83,0] 2-BIT LCD DATA BUS (PBSIZ = 01) [2,0] [4,0] [38,0] [40,0] [3,0] [5,0] [39,0] [41,0] 1- BIT LCD DATA BUS (PBSIZ = 00) [1,0] [2,0] [19,0] [20,0] MC68EZ328 USERÕS MANUAL LINE N LINE 1 m-1 m [m-8,0] [m-4,0] [m-7,0] [m-3,0] [m-6,0] [m-2,0] [m-5,0] [m-1,0] [m-4,0] [m-2,0] [m-3,0] [m-1,0] [m-2,0] [m-1,0] MOTOROLA ...
Page 147
... BKEN bit in the LBLKC register to 1, which alternates the original signal and cursor periodically. You can control the speed at which the cursor blinks by selecting the BDx bit in the LBLKC register. The half-period may be as long as 2 seconds. MOTOROLA VIRTUAL PAGE WIDTH SCREENSTARTING ADDRESS SCREEN WIDTH ...
Page 148
... LCD panel by adjusting the density of ones and zeroes that appear over the frames. The LCD controller can generate sixteen simultaneous gray-scale levels out of 16 12-6 LCD DRIVERS (1,0) (2,0) (1,Y-1) (2,Y-1) 1-BIT PER PIXEL MODE (2,0) (3,0) (4,0) (X-6,Y-1) (X-5,Y-1) (X-4,Y-1) 2-BITS PER PIXEL MODE (1,0) (2,0) (X-3,Y-1) (X-2,Y-1) MC68EZ328 USERÕS MANUAL (X-1,0) (X-1,Y- (5,0) (6,0) (7,0) (X-3,Y-1) (X-2,Y-1) (X-1,Y- (3,0) (X-1,Y-1) MOTOROLA ...
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... The optimal offset values could vary among LCD panel models (even those by the same manufacturer) because of different inter-pixel cross-talk characteristics. However, the default value of the LFRCM register should work for most of the LCD panels on the market. MOTOROLA DENSITY 0000 0 ...
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... There are many issues involved in estimating bandwidth overhead to the data bus. Consider a typical scenario: Screen size: 320 x 240 pixels Bits per pixel: 2-bits per pixel Screen refresh rate: 60Hz System clock: 16.58MHz 12-8 MC68EZ328 USERÕS MANUAL MOTOROLA ...
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... ADDR BIT SSA1 SSA1 SSA1 SSA1 FIELD RESET ADDR Bit 31Ð29ÑReserved These bits are reserved and must be set to 0. MOTOROLA ´ ´ 2 clocks ´ 16.67MHz 16-bit bus SSA2 SSA2 SSA2 SSA2 SSA2 SSA2 7 ...
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... XMxÑWidth Maximum 9Ð4 These bits represent the width of the LCD panel in number of pixels. 12- VP6 VP5 VP4 0xFF 0x(FF)FFFA05 XM9 XM8 XM7 XM6 XM5 XM4 0x03F0 0x(FF)FFFA08 MC68EZ328 USERÕS MANUAL VP3 VP2 VP1 Ñ MOTOROLA ...
Page 153
... Transparent, cursor is disabled Full (black) cursor Reversed video Full (white) cursor. CXPxÑCursor X Position 9Ð0 These bits represent the cursorÕs horizontal starting position X in pixel count (from 0 to XMAX). MOTOROLA YM8 YM7 YM6 YM5 YM4 YM3 YM2 YM1 YM0 ...
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... Note: The cursor is disabled if the CWx or CHx bits are set to zero. 12- CYP8 CYP7 CYP6 0x0000 0x(FF)FFFA1A Ñ 0x0101 0x(FF)FFFA1C MC68EZ328 USERÕS MANUAL CYP5 CYP4 CYP3 CYP2 CYP1 CYP0 CH4 CH3 CH2 CH1 CH0 MOTOROLA ...
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... FIELD RESET ADDR PBSIZxÑPanel Bus Width 1Ð 1-bit 2-bit 4-bit Unused. GSxÑGray-Scale Mode Selection 1Ð Black and white mode Four level gray-scale mode Sixteen level gray-scale mode Reserved. MOTOROLA BD5 BD4 BD3 0x7F 0x(FF)FFFA1F Ñ PBSIZ1 0x00 0x(FF)FFFA20 MC68EZ328 USERÕ ...
Page 156
... The LCD alternate crystal direction rate control (LACDRC) register is used to control the alternate rates of the liquid crystal direction. LACDRC BIT 7 6 FIELD ACDSLT RESET 12- Ñ LCKPOL 0x00 0x(FF)FFFA21 Ñ ACD3 0x00 MC68EZ328 USERÕS MANUAL FLMPOL LPPOL PIXPOL ACD2 ACD1 ACD0 MOTOROLA ...
Page 157
... PIX clock will be used directly, thus bypassing the divider circuit. Refer to for more information. 12.2.13 LCD Clocking Control Register The LCD clocking control (LCKCON) register is used to enable the LCD controller and control the LCD memory cycle. LCKCON BIT 7 6 FIELD LCDON DWIDTH RESET ADDR MOTOROLA 0x(FF)FFFA23 PCD5 PCD4 PCD3 0x00 0x(FF)FFFA25 5 ...
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... RRAx = Hexadecimal value stored in the LRRA register. Width = Screen width in number of pixels. Height = Screen height in number of pixels. PCXD = Hexadecimal value stored in the LPXCD register. LCLK = Period in nanoseconds for LCLK. 12- RRA5 RRA4 RRA3 0xFF 0x(FF)FFFA29 MC68EZ328 USERÕS MANUAL RRA2 RRA1 RRA0 MOTOROLA ...
Page 159
... ADDR XMODxÑHorizontal Modulation 3Ð0 These bits modulate adjacent pixels at different time periods to avoid spatial flicker or jitter when frame rate control is used. These values must be optimized by manually fine-tuning the target LCD panel. See Section 12.1.2 Controlling the Display MOTOROLA Ñ POS3 ...
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... Pixel clock LCD clock Reserved. 12- G21 G20 G13 0x84 0x(FF)FFFA33 CCPE SCR1 SCR0 PW7 PW6 N 0x0000 0x(FF)FFFA36 MC68EZ328 USERÕS MANUAL for more information G12 G11 G10 PW5 PW4 PW3 PW2 PW1 PW0 MOTOROLA ...
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... MOTOROLA ;LCD horizontal size is 240 ;LCD vertical size is 160 ;4 level grey and 320 pixels wide image ;LCD panel data bus is 4 bits, 4 level grey ;pixel clock rate equal 1/4 of LCDCLK from PLL ...
Page 162
... LCD Controller 12-20 MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 163
... Sampling timer with interrupt ¥ Once-per-second and once-per-day interrupts ¥ 32.768kHz or 38.4kHz operation ¥ Two-second watchdog timer to prevent software hang-ups with programmable software resets or interrupts with system applications The real-time clock moduleÕs block diagram is illustrated in Figure 13-1. MOTOROLA MC68EZ328 USERÕS MANUAL 13-1 ...
Page 164
... PPS 1 PPM SECOND MINUTE PRESCALER ALARM COMPARATOR CLOCK CONTROL MINUTE SECOND LATCH LATCH INTERRUPT ENABLE INTERRUPT STATUS WATCHDOG TIMER EC000 BUS MINUTE STOPWATCH DECODE MC68EZ328 USERÕS MANUAL 1 PPH 1 PPD DAY HOUR HOUR LATCH MOTOROLA ...
Page 165
... The following table contains the sampling frequencies of the sampling timer when the primary (32.768kHz) or alternative (38.4kHz) reference clock is chosen. Table 13-1. Sampling Timer Frequencies SAMPLING FREQUENCY SAM7 SAM6 SAM5 SAM4 SAM3 SAM2 SAM1 SAM0 MOTOROLA 32.768KHZ REFERENCE CLOCK 512Hz 256Hz 128Hz 64Hz 32Hz 16Hz 8Hz 4Hz MC68EZ328 USERÕS MANUAL Real-Time Clock 38 ...
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... These bits indicate the current minute. They can be set to any value between 0 and 59. SECONDS These bits indicate the current second. They can be set to any value between 0 and 59. 13 HOURS RESERVED 0xXXXXXXXX 0x(FF)FFFB00 RESERVED 0xXXXXXXXX 0x(FF)FFFB00 MC68EZ328 USERÕS MANUAL MINUTES SECONDS MOTOROLA ...
Page 167
... These bits indicate the current setting of the alarmÕs second. They can be set to any value between 0 and 59. Default is 0. 13.2.3 Watchdog Timer Register The watchdog timer (WATCHDOG) register can be used to enable the watchdog timer and provide its status. WATCHDOG BIT FIELD RESERVED RESET ADDR MOTOROLA HOURS RESERVED 0x00000000 0x(FF)FFFB04 ...
Page 168
... The real-time clock control (RTCCTL) register is used to control the real-time clock. RTCCTL BIT FIELD RESERVED RESET ADDR Bits 15Ð8, 6, and 4Ð0ÑReserved These bits are reserved and should be set RES 0x0080 0x(FF)FFFB0C MC68EZ328 USERÕS MANUAL XTL RESERVED MOTOROLA ...
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... No SAM5 interrupt occurred SAM5 interrupt occurred. SAM4ÑSampling Timer Interrupt Flag at SAM4 Frequency SAM4 interrupt occurred SAM4 interrupt occurred. SAM3ÑSampling Timer Interrupt Flag at SAM3 Frequency SAM3 interrupt occurred SAM3 interrupt occurred. MOTOROLA RESERVED ...
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... You should know, however, that the alarm will reoccur ever 24 hours. If you want a single alarm, you should clear the interrupt enable in the interrupt service routine alarm interrupt occurred alarm interrupt has occurred. 13-8 MC68EZ328 USERÕS MANUAL MOTOROLA ...
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... This bit enables an interrupt at the SAM6 rate The SAM6 interrupt is disabled The SAM6 interrupt is enabled. SAM5ÑSampling Timer SAM5 Interrupt Enable This bit enables an interrupt at the SAM5 rate The SAM5 interrupt is disabled The SAM5 interrupt is enabled. MOTOROLA RESERVED ...
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... HRÑHour Interrupt Enable This bit enables an interrupt at a 1-hour rate The 1-hour interrupt id disabled The 1-hour interrupt is enabled. 1HZÑ1Hz Interrupt Enable This bit enables an interrupt at a 1Hz rate The 1Hz interrupt is disabled The 1Hz interrupt is enabled. 13-10 MC68EZ328 USERÕS MANUAL MOTOROLA ...
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... The stopwatch minutes (STPWCH) register contains the current stopwatch countdown value. STPWCH BIT FIELD RESET ADDR Bits 15Ð6ÑReserved These bits are reserved and should remain at their reset value. MOTOROLA RESERVED 0x003F 0x(FF)FFFB12 MC68EZ328 USERÕS MANUAL Real-Time Clock 5 ...
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... It can be read or written at any time. After a write, the current time assumes the new values. DAYALARM BIT FIELD RESERVED RESET ADDR 13- 0x0XXX 0x(FF)FFFB1A 0x0000 0x(FF)FFFB1C MC68EZ328 USERÕS MANUAL DAYS DAYSAL MOTOROLA ...
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... Bits 15Ð9ÑReserved These bits are reserved and should remain at their reset value. DAYSALÑDay Setting of the Alarm This field indicates the current setting of the alarmÕs day. It can be set to any value between 0 (default) and 511. MOTOROLA MC68EZ328 USERÕS MANUAL Real-Time Clock 13-13 ...
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... Real-Time Clock 13-14 MC68EZ328 USERÕS MANUAL MOTOROLA ...
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... DRAM is supported CLK32 SYSCLK ADDRESS DATA CONTROL CSD0 CSD1 PAGE ACCESS (FROM LCD) 8-BIT PORT (FROM SIM) A[31:1] Figure 14-1. DRAM Controller Block Diagram MOTOROLA MODE CONTROL REFRESH CONTROL DRAM SIGNAL CONTROL DTACK CONTROL DRAM ADDRESS CONTROL MC68EZ328 USERÕS MANUAL RAS0 ...
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... MD4 MD5 MD6 MD7 MC68EZ328 USERÕS MANUAL PA9, PA19, PA20, PA10, PA20 PA19 PA21 PA22 PA21, PA23 PA0, PA0, PA0, PA12* PA13* PA9 PA10 PA11 MD8 MD9 MD10 MD11 MD12 A9/ A10/ A11/ A12/ A13/ MD8 MD9 MD10 MD11 MD12 MOTOROLA ...
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... The DTACK signal is used to hold the LCD controller after the address changes on each word of an LCD transfer. If DTACK is asserted, the LCD controller will assume a fixed MOTOROLA MC68EZ328 USERÕS MANUAL DRAM Controller ...
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... For DRAMs without self-refresh mode, you should set the LPR bit in the DRAMC register for CAS-before-RAS refresh mode to continue while the processor is shut down and all other modules are disabled. 14-4 PAGE_ACCESS DTACK DRAM CONTROLLER ADDRESS DATA MC68EZ328 USERÕS MANUAL MD[12:0] EXTERNAL ADDRESS EXTERNAL DATA MOTOROLA ...
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... The external RESET signal is negated. 6. The internal RESET signal is negated. 7. The DRAM controller terminates the burst CAS-before-RAS refresh cycle. 8. The internal CPCRESET signal is generated for four clocks to reset the DRAM MOTOROLA MC68EZ328 USERÕS MANUAL DRAM Controller DRAM SYNC. WITH SYSTEM CLOCK ...
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... PA11 PA22 PA23 Not valid. ROW 11 This bit selects the row address bit for multiplexed address MD11 PA20 PA22. 14 ROW1 ROW1 ROW9 ROW8 COL10 COL9 1 0 0x0000 0x(FF)FFFC00 MC68EZ328 USERÕS MANUAL COL8 REF MOTOROLA ...
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... When CLK=0, 32KHz (or 34.8 KHz) is used for refresh control REF = 0, refresh rate =2 x 32kHz. REF = 1, refresh rate = 32 KHz REF = 2 to 15, refresh rate = 32KHz /(REF+1) When CLK=1, the system clock is used for refresh control Refresh rate = sysclk/[32 x (REF+1)] MOTOROLA MC68EZ328 USERÕS MANUAL DRAM Controller 14-7 ...
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... This bit selects the clock that is provided to the refresh timer 32kHz (Period A) is selected System clock(Period B) is selected. 14 CLK EDO PGSZ WS1 WS0 0x0000 0x(FF)FFFC02 MC68EZ328 USERÕS MANUAL MSW LSP SLW LPR RST DWE MOTOROLA ...
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... DRAM awake for extended periods of time. If this bit is clear, DRAM accesses will not occur when RM is set and attempts will cause the bus to time-out Self-refresh is interrupted only by clearing the RM bit Self-refresh is temporarily interrupted by the core or LCD controller accesses to DRAM. MOTOROLA MC68EZ328 USERÕS MANUAL DRAM Controller 14-9 ...
Page 186
... DWEÑDRAM Write Enable This bit is used to enable the DWE signal, which can be used when you are using a DRAM that needs an independent write-enable signal, rather than sharing one with the UWE signal Disable DWE Enable DWE. 14-10 MC68EZ328 USERÕS MANUAL MOTOROLA ...
Page 187
... One address signal comparator and one control signal comparator with masking to support single or multiple hardware execution/bus breakpoints ¥ One breakpoint instruction insertion unit Figure 15-1 illustrates the block diagram of the in-circuit emulation module. INTERNAL EC000 BUS Figure 15-1. In-Circuit Emulation Module Block Diagram MOTOROLA BREAKPOINT INSERTION UNIT BREAKPOINT BBIRG ...
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... A-line exception will occur. At this point, EMUBRK is asserted to stop the process and switch control to the emulation monitor (selected by the EMUCS signal). 15-2 Section 15.1.5 Using the A-Line Insertion MC68EZ328 USERÕS MANUAL Unit. When the MOTOROLA ...
Page 189
... When an A-line insertion occurs, the in-circuit emulation module will wait for an A-line exception to occur A-line exception occurs, a level 7 interrupt is generated to the signal that a program breakpoint hits. MOTOROLA MC68EZ328 USERÕS MANUAL In-Circuit Emulation 15-3 ...
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... MC68EZ328 USERÕS MANUAL AC21 AC20 AC19 AC18 AC17 AC16 AC5 AC4 AC3 AC2 AC1 AC0 AM21 AM20 AM19 AM18 AM17 AM16 AM5 AM4 AM3 AM2 AM1 AM0 MOTOROLA ...
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... This bit is used to select the break at a read cycle or write cycle. When a break at read cycle is selected, a breakpoint at the ROM location is possible Write cycle breakpoint Read cycle breakpoint. PDÑProgram/Data Cycle Selection This bit is used to select the break at a program or data cycle Data bus cycle Instruction bus cycle. MOTOROLA RESERVED ...
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... Disable level 7 interrupt generation on a bus breakpoint Enable level 7 interrupt generation on a bus breakpoint. 15 RESERVED 0x0 0x(FF)FFFFFD0A RESERVED 0x0 0x(FF)FFFFFD0C MC68EZ328 USERÕS MANUAL RWM PDM BBIEN HMDIS SB PBEN CEN MOTOROLA ...
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... Select a program break. CENÑCompare Enable This bit is used to activate the comparison logic. You should program the address compare and mask registers before setting this bit to valid Disable the breakpoint comparison logic Enable the breakpoint comparison logic. MOTOROLA ADDRESS HARD-CODE 0x0 0xFFFC 0x2 ...
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... MC68EZ328 pin-out extension to connect to the solder-on emulator pod. The entire MC68EZ328 bus should be buffered using level-shifting buffers when the emulator is designed in 5V and the processor is running at 3.3V. 15 RESERVED 0x0 0x(FF)FFFFFD0E MC68EZ328 USERÕS MANUAL BRK EMUE EMIRQ BBIRQ IRQ N MOTOROLA ...
Page 195
... PC host. The interface can be an RS-232 or printer parallel I/O. Your interface runs on the PC and it will translate your requests to low-level commands and send them to the emulatorÕs controller if there is one. MOTOROLA MOCLK CONTROL BUSW ...
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... CLKO signal, P/D signal, and DTACK signal to decide whether program or data fetch. 15.4 PLUG-IN EMULATOR DESIGN EXAMPLE The following example is a plug-in emulator design, as shown in Figure 15-3. The design is simple and low-cost, which creates a very basic debugging environment. 15-10 Section 15.1.4 Using the Interrupt Gate MC68EZ328 USERÕS MANUAL MOTOROLA ...
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... The entire emulation module only uses 29 pins, including a ground signal. This can be a built onto a very low-cost cable to ship with the software debugger package. These pins can remain on the production version of the system board for production testing, as well as diagnostic and failure analysis. MOTOROLA EMULATION MODULE HOST INTERFACE ...
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... A14 signals. The board also provides optional SRAM/ROM plug-in sockets for expansion. 15- 1N4148 DIS 0.47 µ THR CV 0.47 µ 0.1µ MC1455 RESET EMUCS A14 PAL A13 MC68EZ328 CPU CSxx D[15:0] MC68EZ328 USERÕS MANUAL RS-232 PC HOST INTERFACE 68HC681 AND ADI PORT DEBUG ROM/RAM ONBOARD MEMORY RAM/ROM D[15:0] D[15:0] MOTOROLA ...
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... EMUBRK signal low and perform a system reset. After reset, bootstrap reset vectors are internally generated for reset vector fetch cycles. Figure 16-1 illustrates bootstrap mode reset vector fetch timing.These two-long-word reset vectors are loaded to the stack pointer MOTOROLA MC68EZ328 USERÕS MANUAL 16-1 ...
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... RESET Figure 16-1. Bootstrap Mode Reset Timing Note: In bootstrap mode, the reset vector (0x0Ð0x7) and A-line exception vector (0x28Ð0x2b) spaces are reserved for Motorola use only. Any memory read to these locations will return incorrect data. 16.1.2 Bootstrap Record Format Bootstrap mode data transfers will only accept bootstrap records (b-records). Its format is shown in the table below ...