MC74HC154N Motorola, MC74HC154N Datasheet

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MC74HC154N

Manufacturer Part Number
MC74HC154N
Description
1-of-16 decoder, demultiplexer
Manufacturer
Motorola
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC74HC154N
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1-of-16 Decoder/Demultiplexer
High–Performance Silicon–Gate CMOS
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
active–low Chip Selects are provided to facilitate the chip–select, demulti-
plexing, and cascading functions. When either Chip Select is high, all
outputs are high. The demultiplexing function is accomplished by using the
Address inputs to select the desired device output. Then, while holding one
chip select input low, data can be applied to the other chip select input (see
Application Note).
routing applications.
10/95
SELECT
Motorola, Inc. 1995
INPUTS
The MC54/74HC154 is identical in pinout to the LS154. The device inputs
This device, when enabled, selects one of 16 active–low outputs. Two
The HC154 is primarily used for memory address decoding and data
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 192 FETs or 48 Equivalent Gates
CHIP
ADDRESS
BINARY
INPUTS
CS1
CS2
18
19
A0
A1
A2
A3
23
22
21
20
LOGIC DIAGRAM
10
11
13
14
15
16
17
1
2
3
4
5
6
7
8
9
PIN 24 = V CC
PIN 12 = GND
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
ACTIVE–LOW
OUTPUTS
1
REV 6
24
24
MC54/74HC154
1
1
24
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXDW
ORDERING INFORMATION
GND
Y10
1
PIN ASSIGNMENT
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
1
2
3
4
5
6
7
8
9
10
11
12
CERAMIC PACKAGE
PLASTIC PACKAGE
SOIC PACKAGE
CASE 751E–04
CASE 758–02
CASE 724–03
24
23
22
21
20
19
18
17
16
15
14
13
DW SUFFIX
Ceramic
Plastic
SOIC
N SUFFIX
J SUFFIX
V CC
A0
A1
A2
A3
CS2
CS1
Y15
Y14
Y13
Y12
Y11

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MC74HC154N Summary of contents

Page 1

... In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 192 FETs or 48 Equivalent Gates LOGIC DIAGRAM 23 A0 BINARY 22 A1 ADDRESS 21 A2 INPUTS 20 A3 CHIP 18 CS1 SELECT 19 CS2 INPUTS 10/95 Motorola, Inc. 1995 ACTIVE–LOW 9 Y8 OUTPUTS 10 Y9 ...

Page 2

... Current (per Package) Î Î Î Î Î Î Î Î Î Î Î Î Î NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). MOTOROLA Î Î Î Î Î Î Î Î Î ...

Page 3

... NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). ...

Page 4

... INPUT A t PLH t PHL OUTPUT Y 50% Figure STROBE CS1 CS2 DECODER SELECTED OUTPUT IS LOW MOTOROLA SWITCHING WAVEFORMS V CC 90% CS1 OR CS2 50% GND 10% OUTPUT Y TEST POINT OUTPUT DEVICE UNDER TEST * Includes all probe and jig capacitance Figure 3. Test Circuit ...

Page 5

... CS1 19 CS2 High–Speed CMOS Logic Data DL129 — Rev 6 EXPANDED LOGIC DIAGRAM 5 MC54/74HC154 Y10 13 Y11 14 Y12 15 Y13 16 Y14 17 Y15 MOTOROLA ...

Page 6

... 0.25 (0.010 –A– –T– SEATING PLANE 0.25 (0.010) MOTOROLA OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 758–02 ISSUE SEATING –T– K PLANE N SUFFIX PLASTIC PACKAGE CASE 724–03 ISSUE D – ...

Page 7

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “ ...

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