MCM63Z818TQ133 Motorola, MCM63Z818TQ133 Datasheet

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MCM63Z818TQ133

Manufacturer Part Number
MCM63Z818TQ133
Description
128K X 36 and 256K x 18 bit pipelined ZBT RAM synchronous fact static RAM
Manufacturer
Motorola
Datasheet

Specifications of MCM63Z818TQ133

Case
TQFP
Dc
00+
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
128K x 36 and 256K x 18 Bit
Pipelined ZBT
Synchronous Fast Static RAM
zero bus turnaround. The ZBT RAM allows 100% use of bus cycles during
back–to–back read/write and write/read cycles. The MCM63Z736 is organized
as 128K words of 36 bits each and the MCM63Z818 is organized as 256K words
of 18 bits each, fabricated with high performance silicon gate CMOS
technology. This device integrates input registers, an output register, a 2–bit
address counter, and high speed SRAM onto a single monolithic circuit for
reduced parts count in communication applications. Synchronous design
allows precise cycle control with the use of an external clock (CK). CMOS
circuitry reduces the overall power consumption of the integrated functions for
greater reliability.
(G) and linear burst order (LBO) are clock (CK) controlled through positive–
edge–triggered noninverting registers.
clock (CK) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
triggered output register and then released to the output buffers at the next rising
edge of clock (CK).
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by
Micron Technology, Inc. and Motorola, Inc.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 1
2/6/98
MOTOROLA FAST SRAM
Motorola, Inc. 1998
The ZBT RAM is a 4M–bit synchronous fast static RAM designed to provide
Addresses (SA), data inputs (DQ), and all control signals except output enable
Write cycles are internally self–timed and are initiated by the rising edge of the
For read cycles, pipelined SRAM output data is temporarily stored by an edge–
3.3 V LVTTL and LVCMOS Compatible
MCM63Z736/MCM63Z818–133 = 4.2 ns Access/7.5 ns Cycle (133 MHz)
MCM63Z736/MCM63Z818–100 = 5 ns Access/10 ns Cycle (100 MHz)
Selectable Burst Sequencing Order (Linear/Interleaved)
Internally Self–Timed Write Cycle
Two–Cycle Deselect
Byte Write Control
ADV Controlled Burst
100–Pin TQFP Package
RAM
MCM63Z736
MCM63Z818
MCM63Z736
Order this document
CASE 983A–01
TQ PACKAGE
by MCM63Z736/D
D
MCM63Z818
TQFP
1

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MCM63Z818TQ133 Summary of contents

Page 1

... TQFP Package ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology, Inc. and Motorola, Inc. This document contains information on a new product. Specifications and information herein are subject to change without notice. ...

Page 2

... DQb 78 DQb 77 V DDQ DQb DQb 74 73 DQb 72 DQb DDQ 69 DQb 68 DQb DQa 62 DQa 61 V DDQ DQa 58 DQa 57 DQa 56 DQa DDQ 53 DQa 52 DQa 51 DQa 50 MOTOROLA FAST SRAM ...

Page 3

... DQb DQb DDQ DQb DQb DQb DQb V DDQ V SS DQb DQb DQb DDQ MOTOROLA FAST SRAM PIN ASSIGNMENT 100 9695 ...

Page 4

... Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins Supply Core Power Supply. V DDQ Supply I/O Power Supply Supply Ground. NC — No Connection: There is no connection to the chip. Description MOTOROLA FAST SRAM ...

Page 5

... MOTOROLA FAST SRAM Symbol Type ADV Input Synchronous Load/Advance: Loads a new address into counter when low. RAM uses internally generated burst addresses when high. ...

Page 6

... SBc SBd (See Note 1) (See Note 1) SBb 4th Address (Internal X11 X00 X01 X10 4th Address (Internal X11 X10 X01 X00 MOTOROLA FAST SRAM ...

Page 7

... INPUT COMMAND CODE AND STATE NAME DEFINITION DIAGRAM INPUT COMMAND D B CODE DESELECT CK CKE E FALSE SA0 – SAx ADV SW SBX NOTE: Cycles are named for their control inputs, not for data I/O state. MOTOROLA FAST SRAM CONTINUE BURST NEW WRITE DESELECT WRITE TRUE TRUE VALID VALID VALID VALID B ...

Page 8

... Truth Table. 2. Hold (i.e., CKE sampled high) is not shown simply because CKE = 1 blocks clock input and therefore, blocks any state change. Figure 1. ZBT RAM State Diagram CURRENT NEXT STATE STATE B BURST WRITE NEW D R WRITE MOTOROLA FAST SRAM ...

Page 9

... INTERMEDIATE STATE ( CURRENT STATE (n) TRANSITION TRANSITION INPUT COMMAND CODE STATE CK COMMAND CODE DQ STATE NAME Figure 4. State Definitions for I/O State Diagrams MOTOROLA FAST SRAM INTERMEDIATE D B HIGH– INTERMEDIATE INTERMEDIATE INTERMEDIATE NEXT STATE ( NOTES: 1. Input command codes ( and B) represent control pin inputs as indicated in the Truth Table ...

Page 10

... V SS – 0 DDQ + 0 1 – – 125 C Symbol Single–Layer Board Four–Layer Board This device contains circuitry to protect the Max Unit Notes C C C/W 4 MOTOROLA FAST SRAM ...

Page 11

... V IH2 . TTL levels for other inputs are V in CAPACITANCE (f = 1.0 MHz 3 Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance Input/Output Capacitance MOTOROLA FAST SRAM 5 Unless Otherwise Noted) (Voltages Referenced Symbol Min ...

Page 12

... MHz Min Max Unit U i Notes N — 10 — ns — 4 — — 4 — 4.2 — 4.2 — — 1.5 — — 1.5 — — 0 — 3.5 — 3 3.5 1.5 3 — 2.2 — ns 2.2 2 2.2 2.2 2.2 — 0.5 — ns MOTOROLA FAST SRAM TBD ...

Page 13

... AVKH SA0 – SAx t WVKH SW t WVKH SBx t EVKH E t LVKH ADV t CVKH CKE Figure 7. AC Timing Parameter Definitions MOTOROLA FAST SRAM t KHKH t KHKL t KLKH t KHAX t KHWX t KHWX t KHEX t KHLX t KHCX t GLQX t GLQV Q t DVKH t KHDX D t KHQV t KHQX ...

Page 14

... D MCM63Z736 MCM63Z818 14 MOTOROLA FAST SRAM ...

Page 15

... MOTOROLA FAST SRAM D MCM63Z736 MCM63Z818 15 ...

Page 16

... D MCM63Z736 MCM63Z818 16 MOTOROLA FAST SRAM ...

Page 17

... MOTOROLA FAST SRAM D MCM63Z736 MCM63Z818 17 ...

Page 18

... Full Part Numbers — MCM63Z736TQ133 D MCM63Z736 MCM63Z818 18 ORDERING INFORMATION (Order by Full Part Number) 63Z736 MCM 63Z818 Blank = Trays Tape and Reel Speed (133 = 133 MHz, 100 = 100 MHz) Package (TQ = TQFP) MCM63Z736TQ100 MCM63Z736TQ133R MCM63Z736TQ100R MCM63Z818TQ133 MCM63Z818TQ100 MCM63Z818TQ133R MCM63Z818TQ100R MOTOROLA FAST SRAM ...

Page 19

... D1 TIPS 0.20 (0.008) C A–B A –H– –C– SEATING PLANE 0.05 (0.002 VIEW AB MOTOROLA FAST SRAM PACKAGE DIMENSIONS TQ PACKAGE 100–PIN TQFP CASE 983A– TIPS 0.20 (0.008) C A–B D –D– E/2 –B– E1 ...

Page 20

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

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