M65762FP MITSUBISHI, M65762FP Datasheet
![no-image](/images/manufacturer_photos/0/4/451/mitsubishi_sml.jpg)
M65762FP
Available stocks
Related parts for M65762FP
M65762FP Summary of contents
Page 1
... DESCRIPTION The M65762FP is a compression and decompression LSI conforming to the high efficiency encoding system (QM-Coder) in the International Standard, the JBIG/JPEG (ITU-T Recommenda- tions T.81 and T.82) for coding still images. It also conforms to the International Standard (ITU-T Recommendation T.85) for facsimile. The QM-Coder is an information dependent type which is capable ...
Page 2
... HWR 134 HCS 135 V DD 136 GND 137 HA0 138 HA1 139 HA2 140 HA3 141 TOUT1 142 TOUT2 143 V DD 144 M65762FP M65762FP Outline144P6Q-A M65762FP QM-CODER CD7 71 CD6 70 CD5 69 CD4 68 GND CD3 65 CD2 64 CD1 63 CD0 62 GND 61 ...
Page 3
... RAM. (8) Coding/decoding block This block performs arithmetic coding and decoding. It contains a ROM which contains a table capable of estimating 113 states and is capable of byte stuffing function ('OO' byte insertion/rejection) and is capable of end marker code control (Marker insertion/detection). M65762FP QM-CODER CD0-31 CDRQ 108 CDAK* 109 ...
Page 4
... CD22 92 V Power supply DD 93 GND Power supply 94 I/O CD23 95 I/O CD24 96 I/O CD25 97 I/O CD26 98 I/O CD27 99 Power supply V DD 100 M65762FP QM-CODER I/O Pin name Pin No. GND Power supply 101 I/O CD28 102 I/O CD29 103 I/O CD30 104 I/O CD31 105 V Power supply DD 106 GND Power supply 107 O ...
Page 5
... Transfer clock signal for image data (LSI internal loopback output signal of PXCK*) Image data input signal Image data output signal Master clock input signal Test input signal 0/1 (Should be connected to GND when used normally.) Power supply (+5V) Ground M65762FP QM-CODER (Asterisk "*" in signal name indicates negative logic.) Function ...
Page 6
... When a theoretical image is used to compare processing speeds in the worst case, the processing speed of existing product type is about 9.4M pixels/sec (1/compression ratio about 1), while the processing speed of the M65762FP is about 27.5M pixels/sec (1/compression ratio X ? and is about 31.2M pixels/sec (1/compression ratio 0.75) for decoding ...
Page 7
... Decoding of M65762FP 30 Coding of M65762FP 25 20 Coding/decoding of existing product type (M65760/1FP (Legend) Theoretical Decoding of M65762FP 5 Coding of M65762FP Coding/decoding of existing product type 0 0 0.25 Figure 3 Estimated Processing Speed Actual image image 0.5 0.75 1/compression ratio M65762FP QM-CODER 1.0 1.2 ...
Page 8
... Selects the typical prediction function. - Selects prohibition of line memory initialization Sets the terminal marker code in encoding (SDNORM/SDRST) - Reads a marker code in decoding. R (SDNORM, SDRST, ABORT, others) - Scale down in coding (1/2 scale-down of horizontal and vertical, horizontal OR processing) W/R - Scale-up at time of decoding (scale-up of horizontal and vertical by twice) M65762FP QM-CODER Content ...
Page 9
... M65762FP Selection of data bit swap of code data bus (0: MSB first, 1: LSB first) See Table 2. Selection of data byte swap of code data bus (0: low order byte first, 1: high order byte first) (Note effective only when the host bus selects 16-bit/32-bit bus ...
Page 10
... When the M65762FP QM-CODER When this bit is set to 1, data can be read/written on the code data bus. (This bit is equivalent to the CDRQ pin.) detected, 1: Detected) This bit is set to 1 when some marker code is detected at time of decoding ...
Page 11
... MPS MPS :Prediction value MPS (0/1) L14-0 :Low 15-bits of prediction unmatched probability LSZ M65762FP d7 LIN_REG_L: LINE_L LINE_H LIN_REG_H: (low byte 65535) (upper byte) The number of processed lines lines, coding/decoding/through processing stop temporary/end of processing. (Note)The number of lines in this process is cleared to 0 with the processing start command issued ...
Page 12
... Marker code read out register (R) (Address: C) d0-7(MDET) (For details, see 4. (6) MITSUBISHI SEMICONDUCTOR (LSI) M65762FP QM-CODER encoding/decoding of stripes. This LIO bit is effective only in the image data through mode (d1 = 1). (Notes) • LIO (d3, d2) = (1, 1) not allowed being set. • When selection of load/store of image data of line memory, temporary stop (d3 (JP command register) is not allowed to be set ...
Page 13
... Scale-up/scale-down setting Pixel setting Line count setting (Note) When H/W reset is written into the system setting register, written value is set in the system setting register Register Initial value Indefinite M65762FP QM-CODER ...
Page 14
... IENB_REG STAT_REG – – – – – – – (Error) CMD_REG M65762FP QM-CODER d0 ;H/W reset bit ON ;H/W reset bit OFF ;Initializes context table RAM ;Process end interrupt enable d0 ;Interrupt disable ;j = End of processing ...
Page 15
... N (Error) N (Coding) N (Marker not detected) (Error) mdet MDET_REG: MITSUBISHI SEMICONDUCTOR (LSI) M65762FP QM-CODER ;Cb Bit width of code data bus d0 ;Bs Code data bus bit, byte swap ;Pb Bit width of image data bus, I/F selection ;mm = operation mode (coding/decoding/through) ...
Page 16
... IENB_REG the line count set register). At time of decoding, (number of lines in output image data) = (value set in the line count set register). M65762FP QM-CODER ;Cb Bit width of code data bus ;Bs Code data bus bit, byte swap d0 ...
Page 17
... MDET_REG CMD_REG: CMD_REG M65762FP ;Set change in final AT pixel. (a"a",a"a"a"a"a") (Note) Template is not allowed to be changed. ;lset_l,lset_h = Number of processing lines (Note) Enter the number of processing lines ranging from restart of processing to the final line. ...
Page 18
... IENB_REG STAT_REG: – – – – – – – j (Error) M65762FP QM-CODER ;Cb Bit width of code data bus d0 ;Ds = Bit swap of image data bus ;Bs Code data bus bit, byte swap ;Pb Bit width of image data bus, I/F selection ...
Page 19
... After coding/decoding of stripe, save line memory and context table RAM for next stripe. [case 3] Plane 1 4 Plane 2 Stripe Plane 3 (Processes in numeric order) M65762FP QM-CODER N (Difference plane) [case3] Loading of image data of line memory, and loading of context table RAM [Processes (4) and (5)] ...
Page 20
... CDRD*/CDWR* CD0-31 (Note) For 32-bit bus, only the long word access (CD0-31) is allowed. (Description) CDRQ can be checked for being asserted (H) to assert (L) CDAK*. Asserting (L) CDAK* negates (L) CDRQ. Asserting (L) section of CDRD*/CDWR* must be included in the CDAK* asserting section (L). M65762FP Write access QM-CODER ...
Page 21
... PD0-31 (Note) For 32-bit bus, only the long word access (PD0-31) is allowed. (Description) PDRQ can be checked for being asserted (H) to assert (L) PDAK*. Asserting (L) PDAK* negates (H) PDRQ. Asserting (L) section of PDRD*/PDWR* must be included in the asserting section (L) of PDAK M65762FP QM-CODER 5 N ...
Page 22
... Image data file High speed communication with QM coding data QM-Coder (M65762FP) QM-Coder (M65762FP) Code memory Disk unit High speed communication by QM-Coder Printer (LBP) Reduction of memory capacity with real-time decoding Figure 6 Application Example to Printer M65762FP QM-CODER MPU DMAC Communi- cation control Recording ...
Page 23
... Y D ;FFh ;07h ;length in bytes of private comment ;contents of comment (Within the frame: LSI support range) ;Protected Stripe Coded Data =byte stuffed SCD(Stripe Code Data) ;FFh 1 ;normal terminate(02h) 1 ;/reset "state" for next SDE(03h) ;FFh ;04h ;FFh ;01h M65762FP QM-CODER ...
Page 24
... M65762FP QM-CODER LSZ NLPS NMPS 0x01a4 55 58 0x0160 56 59 0x0125 57 60 0x00f6 58 61 0x00cb 59 62 0x00ab 61 63 0x008f 61 32 0x5b12 65 65 0x4d04 ...
Page 25
... Host bus I/F RESET* t0 CS* A0-3 t3 RD* WR* t6 D0-7 2. Code data I/F CDRQ t20 CDAK* CDRD* CDWR* t26 CD0- t13 t7 Output t22 t21 t31 t24 t34 t27 t36 Output M65762FP Conditions:V = C=50pF Ta=0-70 C t12 t11 t15 t14 t16 t17 Input t32 t37 Input QM-CODER ...
Page 26
... CDAK* setup time to CDWR* assert t32 CDAK* hold time to CDWR* negate t34 CDWR* assert time t36 CD0-31 input setup time to CDWR* negate t37 CD0-31 input hold time to CDWR* negate Parameter Parameter M65762FP QM-CODER (Unit: ns) Timing conditions Max Min Typ 100 - - 15 - ...
Page 27
... PDRQ t60 PDAK* t61 PDRD* t64 PDWR* t66 Output PD0-31 4. Master clock input frequency (LSI operating frequency) Mx MCLK t45 t44 t43 t47 t49 t51 t57 t71 t62 t74 t76 t67 Mh Ml M65762FP QM-CODER t42 t48 N N t72 t77 Input ...
Page 28
... PD0-31 input hold time to PDWR* negate Table B. 4 Master Clock Frequencies Parameter MCLK cycle (Mx) MCLK high level time (Mh) MCLK low level time (Ml) Parameter (Unit: ns) Timing conditions Max frequency Max Min Typ 40MHz M65762FP QM-CODER (Unit: ns) Timing conditions Max Min Typ - - ...