HN29W25611T-50H HITACHI, HN29W25611T-50H Datasheet
HN29W25611T-50H
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HN29W25611T-50H Summary of contents
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... HN29W25611T-50H 256M AND type Flash Memory More than 16,057-sector (271,299,072-bit) Description The Hitachi HN29W25611T is a CMOS Flash Memory with AND type multi-level memory cells. It has fully automatic programming and erase capabilities with a single 3.3 V power supply. The functions are controlled by simple external commands. To fit the I/O card applications, the unit of programming and erase is as small as (2048 + 64) bytes ...
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... A (max) (Deep standby) SB3 The following architecture is required for data reliability. Error correction: more than 3-bit error correction per each sector read Spare sectors: 1.8% (290 sectors) within usable sectors Ordering Information Type No. Available sector HN29W25611T-50H More than 16,057 sectors 2 Package 2 12.0 18.40 mm 0.5 mm pitch ...
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... Function Input/output Chip enable Output enable Write enable Command data enable Power supply Ground Ready/Busy Reset Serial clock No connection HN29W25611T-50H CDE RES ...
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... HN29W25611T-50H Block Diagram • • I/O0 • to Multiplexer • I/O7 • • RDY/Busy Control WE signal SC buffer RES CDE 4 Sector X-decoder address buffer Data Input • • input data • • buffer control Y-address • counter • Read/Program/Erase control 2048 + 64 16384 ...
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... Control bytes I/O0 I/O1 I/O2 I/ A10 A11 A10 A11 HN29W25611T-50H 83FH Column address I/O4 I/O5 I/O6 I/ A12 A13 * referred ...
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... HN29W25611T-50H Pin Function CE used to select the device. The status returns to the standby at the rising edge the reading operation. However, the status does not return to the standby at the rising edge the busy state in programming and erase operation. OE: Memory data and status register data can be read, when WE: Commands and address are latched at the rising edge of WE ...
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... Write 2h* Write 4 Write 7 4 Write Write 2h* Write 1 Write 1 Write 4 Write HN29W25611T-50H Second bus cycle Data in Operation Data in mode 4 00H Write SA (1)* 4 00H Write SA (1)* 4 F0H Write SA (1)* 90H Read 01H Read 4 20H Write SA (1)* 4 10H Write ...
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... HN29W25611T-50H Command Read Serial read (1) (Without CA) 3 (With CA) Serial read (2) Read identifier codes Data recovery read Auto erase Single sector Auto program Program (1) (Without CA* (With CA* 10 Program (2)* Program (3) (Control bytes)* Program (4) (WithoutCA* (With CA* Reset Clear status register Data recovery write 8 Third bus cycle ...
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... Write 2h* Write 2h* Write HN29W25611T-50H Sixth bus cycle Data in Operation Data in mode (2)* Write 40H CA (2) Write 40H first time after the power up. IHR h 2048 + 64). *11, 12 *11 ...
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... HN29W25611T-50H Mode Description Read Serial Read (1): Memory data D0 to D2111 in the sector of address SA is sequentially read. Output data is not valid after the number of the SC pulse exceeds 2112. When CA is input, memory data D ( the sector of address SA is sequentially read. Then output data is not valid after the number of the SC pulse exceeds (2112 to m) ...
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... CDE V 16383 Sector address Memory array 0 0 2111 Column address Register Serial read (1) (With CA) Program (1) (With CA) and V , respectively HN29W25611T-50H 16383 Sector address Memory array 0 0 2111 2048 Register Serial read (2) Program ( the status IL 2111 11 ...
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... HN29W25611T-50H Data Recovery Read When the programming was an error, the program data can be read by using data recovery read. When an additional programming was an error, the data compounded of the program data and the origin data in the sector address SA can be read. Output data are not valid after the number of SA pulse exeeds 2112. The mode turns back to the standby mode at any time when are latched at a rising edge of WE pulse after the data recovery read command is written ...
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... Command/Address CDE WE Low SC Single Sector Erase Command/Address CDE SA (2) CA (1) CA (2) Data output CA (1) CA (2) Data output 00H/F0H SA (1) SA (2) 20H SA ( Low HN29W25611T-50H CA (1)' CA (2)' CA (1)' CA (2)' Data output Data output SA (2) B0H Erase start Data output Data output 13 ...
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... HN29W25611T-50H Program (1), (4) (With CA before SC) Command 10H/11H SA (1) SA (2) /Address CDE WE Low SC Program (1), (4) (With CA after SC) Command 10H/11H SA (1) SA (2) /Address CDE WE Low SC Program (1), (4) (Without CA) Command/Address 10H/11H CDE WE SC Low Program (2) Command/Address 1FH CDE WE SC Low 14 CA (1) CA (2) Data input ...
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... Data Recovery Read Mode Command/Address Data Recovery Write Mode Command/Address CDE SA (1) SA (2) 90H Low Manufacture code output 01H CDE WE SC Low 12H SA ( Low HN29W25611T-50H Data input Program start Device code Manufacture output code output Data output SA (2) 40H Program start 40H 15 ...
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... HN29W25611T-50H Status Transition V Deep CC Power off standby RES 00H/F0H FFH CE 90H FFH CE 20H FFH 10H CE Output /11H Program Standby disable (1)/(4) setup FFH 1FH /0FH Program (2)/(3) FFH Status register clear 2 CE* 2 FFH* OE Status register Notes: 1. (01H)/(12H) Data recovery read/write can be used only for Program (1), (2), (3), (4) errors. ...
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... Vin, Vout –0 Topr 0 to +70 Tstg –65 to +125 Tbias –10 to +80 20 ns. Symbol Min Typ Max Cin — — 6 Cout — — 12 HN29W25611T-50H Unit Notes ˚C ˚C 3 ˚C Unit Test conditions pF Vin = Vout = ...
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... HN29W25611T-50H DC Characteristics (V CC Parameter Input leakage current Output leakage current Standby V current CC Deep standby V current CC Operating V current CC Operating V current (Program Operating V current (Erase) CC Input voltage Input voltage (RES pin) Output voltage Notes min = –1.0 V for pulse width the read operation. ...
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... VRH 1 — — CESR 0 — — DFP — — 1 BSY 200 — — CPH 0 — — CWRS 0 — — CWRH HN29W25611T-50H Unit Test conditions ...
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... HN29W25611T-50H Parameter Symbol SC setup for hold time for ( (2) delay time t RDY/Busy setup for SC t Time to device busy on read t mode Busy time on reset mode t Notes time after which the I/O pins become open (min) is specified as a reference point only for SC ...
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... SPL t 0 — — SDS t 30 — — SDH t 50 — — — — SCS t 20 — — SCHW HN29W25611T-50H Unit Test conditions CDE = V ns ...
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... HN29W25611T-50H Parameter CE to output delay OE to output delay OE high to output float RES to WE setup time CDE setup time for WE CDE hold time for WE CDE setup time for SC CDE hold time for SC Next cycle ready time CDE to OE hold time CDE to output delay ...
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... CEH CESR RP CES BSY Ready High-Z level referred to DC characteristics at the rising and falling edges of V ILR level referred to DC characteristics while I/O7 outputs the V IHR level. OL HN29W25611T-50H t t CEH CESR t CWRH t t VRH DFP level in the OL 23 ...
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... HN29W25611T-50H Serial Read (1) (2) Timing Waveform CE t CES CWC CWC WPH WPH OEWS WE t CDS CDS CDE t CDH SCS DS AS I/O0 to I/O7 00H SA(1) /F0H RES t RP RDY /Busy Notes: 1. The status returns to the standby at the rising edge of CE. ...
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... CWC CWC OEPS t t WPH WPH CDS t CDH t t CDH SCHW SA(1) SA(2) B0H t DB HN29W25611T-50H cycle t 1 COH * t CPH t OER OES SOH SCC SCC * SAC AH SPL ...
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... HN29W25611T-50H Program (1) and Status Data Polling Timing Waveform CE t CES OEWS CWC CWC t t WPH WPH CDS WP CDS WP CDE t CDH SCS t AS I/O0 to I/O7 10H SA (1) RES t RP RDY /Busy Notes: 1. The programming operation is not guranteed when the number of the SC pulse exceeds 2112. ...
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... CDSH CDH CDH * t SPL SDH SDS 1 PD0 PD1 CA(1) CA(2) PD(k)* h 2048 + 64) HN29W25611T-50H 6 h–1 cycle* t CEH t OEPS CDSS SCC CDH CDH * SPL SCHW SDH ...
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... HN29W25611T-50H Program (2) and Status Data Polling Timing Waveform CE t CES OEWS CWC CWC t t WPH WPH CDS CDS WP CDE t CDH SCS t AS I/O0 to I/O7 1FH SA (1) RES t RP RDY /Busy Notes: 1. The programming operation is not guranteed when the number of the SC pulse exceeds 2112. ...
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... CDSS SCC t 1 CDH * t SPL SDH SDS SA (2) PD2048 PD2049 PD2111 High-Z HN29W25611T-50H t COS t t CEH CE t OEPS ASP t CDH t SCHW 40H I/ I/ RDY t CDS ...
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... HN29W25611T-50H Program (4) and Status Data Polling Timing Waveform CE t CES OEWS CWC CWC t t WPH WPH CDS WP CDS WP CDE t CDH SCS t AS I/O0 to I/O7 11H SA (1) RES t RP RDY /Busy Notes: 1. The programming operation is not guranteed when the number of the SC pulse exceeds 2112. ...
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... CDH * t t WSD SPL SDH SDS 1 PD0 PD1 CA(1) CA(2) PD(k)* t RBSY t RS High-Z h 2048 + 64) HN29W25611T-50H 6 h–1 cycle CEH CE t OEPS CDSS SCC CDH CDH t * SPL SCHW SDH t t ...
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... HN29W25611T-50H ID and Status Register Read Timing Waveform CE t CES OEWS OEPS CDS WP CDE t SCHW SCS DS I/O0 to I/O7 90H RES t RP RDY /Busy Note: 1. The status returns to the standby at the rising edge of CE CDH CDCH t t CDAC CDAC ...
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... CE turns to the CWHR t CDOS t OES SOH SCC SCC SPL SAC SAC SAC OEL SH SH D0out D1out level. HN29W25611T-50H CPH t COH t CDS SAC D2111out 2 * High High CEH CDH FFH 33 ...
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... HN29W25611T-50H Data Recovery Write Timing Waveform CE t CES OE t CWC t t WPH OEWS WE t CDS CDS CDE t CDH SCS DS AS I/O0 to I/O7 12H RES t RP High-Z RDY /Busy Notes: 1. Any commands,including reset command FFH, cannot be input while RDY/Busy ...
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... DS DH I/O0 to I/O7 50H RES High High-Z RDY /Busy Note 1. The status returns to the standby at the rising edge of CE. t CWH t WWH t CDS t CDH Next Command HN29W25611T-50H CPH t CES t OEWS t CDS t t CDH WP t SCS tDS tDH Next Command 35 ...
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... HN29W25611T-50H Function Description Status Register: The HN29W25611T outputs the operation status data as follows: I/O7 pin outputs a V indicate that the memory is in either erase or program operation. The level of I/O7 pin turns the operation finishes. I/O5 and I/O4 pins output V complete in a finite time, respectively. If these pins output V out ...
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... C7H START Sector number = 0 Read data No 2 Check data* Yes No Sector number = 16,383 Yes END 2. Bad sectors are installed in system. Indication of Unusable Sectors HN29W25611T-50H 823H 824H 825H 826H to 83FH 1CH 71H C7H FFH Column address = 820H to 825H 1 37 ...
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... HN29W25611T-50H Requirements for High System Reliability The device may fail during a program, erase or read operation due to write or erase cycles. The following architecture will enable high system reliability if a failure occurs. 1. For an error in read operation: An error correction more than 3-bit error correction per each sector read is required for data reliability ...
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... Check RDY/Busy No Check status Yes Clear status register Load data from external buffer Check status: Status register read END Spare Sectors in Program Error HN29W25611T-50H Data recovery read Data recovery write Set another Program start usable sector Check RDY/Busy Program end No Check status ...
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... HN29W25611T-50H Memory Structure Bit: Minimum unit of data. Byte: Input/output data unit in programming and reading. (1 byte = 8 bits) Sector: Page unit in erase, programming and reading. (1 sector = 2,112 bytes = 16,896 bits) Device: 1 device = 16,384 sectors. 40 bit 2,112 bytes (16,896 bits) sector byte (8 bits) ...
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... Package Dimensions HN29W25611T Series (TFP-48D) 12.00 12.40 Max 48 1 0.50 *0.22 0.08 0.08 0.20 0.06 0.45 Max 0.10 *Dimension including the plating thickness Base material dimension 20.00 0.20 Hitachi Code JEDEC EIAJ Mass (reference value) HN29W25611T-50H Unit: mm 0.80 0 – 5 0.50 0.10 TFP-48D Conforms Conforms 0. ...
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... HN29W25611T-50H Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document ...