M2V28S40ATP-7 MITSUBISHI, M2V28S40ATP-7 Datasheet
M2V28S40ATP-7
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M2V28S40ATP-7 Summary of contents
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... DESCRIPTION M2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40ATP is organized as 4-bank x 2,097,152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK. M2V28S20ATP,M2V28S30ATP,M2V28S40ATP achieves very high speed data rates up to 133MHz, and is suitable for main memory or graphic memory in computer systems ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L PIN CONFIGURATION (TOP VIEW) Vdd Vdd Vdd NC DQ0 DQ0 VddQ VddQ VddQ NC NC DQ1 DQ0 DQ1 DQ2 VssQ VssQ VssQ NC NC DQ3 NC DQ2 DQ4 VddQ VddQ VddQ NC NC DQ5 DQ1 DQ3 DQ6 VssQ ...
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... Cell Array Bank #0 Mode Register Address Buffer A0-11 Note : This figure shows the M2V28S30ATP. The M2V28S20ATP configration is 4096x2048x4 of cell array and DQ 0-3. The M2V28S40ATP configration is 4096x512x16 of cell array and DQ 0-15. Type Designation Code DQ0-7 I/O Buffer Memory Array Memory Array 4096 x1024 x8 ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L PIN FUNCTION CLK Input CKE Input /CS Input /RAS, /CAS, /WE Input A0-11 Input BA0,1 Input DQ0-7 Input / Output DQM Input Vdd, Vss Power Supply VddQ, VssQ Power Supply Master Clock: All other inputs are referenced to the rising edge of CLK. ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L BASIC FUNCTIONS The M2V28S30ATP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L COMMAND TRUTH TABLE COMMAND Deselect No Operation Row Address Entry & Bank Activate Single Bank Precharge Precharge All Banks Column Address Entry & Write Column Address Entry & Write with Auto-Precharge Column Address Entry & ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L FUNCTION TRUTH TABLE Current State /CS /RAS /CAS /WE Address IDLE ROW ACTIVE Command DESEL NOP ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address H X READ WRITE Command DESEL ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address H X READ with AUTO L H PRECHARGE WRITE with AUTO PRECHARGE ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address H X PRE - CHARGING ROW H X ACTIVATING Command DESEL ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address H X WRITE RECOVERING REFRESHING Command X X DESEL NOP ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address MODE H X REGISTER SETTING ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration NOTES: 1 ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L FUNCTION TRUTH TABLE for CKE CKE CKE Current State n SELF- REFRESH POWER DOWN ALL BANKS IDLE ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SIMPLIFIED STATE DIAGRAM MODE REGISTER SET CLK SUSPEND CKEL WRITE SUSPEND CKEH WRITEA CKEL WRITEA SUSPEND CKEH POWER APPLIED POWER ON REFS MRS IDLE CKEH ACT CKEL CKEH ROW ACTIVE WRITE WRITEA READA READ ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L POWER ON SEQUENCE Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs. ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L CLK Read Command Y Address DQ CL= 3 /CAS Latency BL= 4 Initial Address ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L OPERATIONAL DESCRIPTION BANK ACTIVATE The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank addresses (BA0,1). A row is indicated by the row addresses A0-11. The minimum activation interval between one bank and the other bank is tRRD. Maximum 2 ACT commands are allowed within tRC , although the number of banks which are active concurrently is not limited ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Multi Bank Interleaving READ (BL=4, CL=3) CLK Command ACT tRCD A0-9 Xa A10 Xa A11 Xa BA0 READ with Auto-Precharge (BL=4, CL=3) CLK Command ACT tRCD A0-9 Xa A10 Xa A11 Xa BA0 READ Auto-Precharge Timing (BL=4) CLK Command ACT CL=3 DQ CL=2 DQ READ ACT READ ...
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... M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L WRITE After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same cycle as the WRITE. Following (BL -1) data are written into the RAM, when the Burst Length is BL. The start address is specified by A0-A9,A11(x4), A0-9(X8), A0-8(X16) and the address sequence of burst data is defined by the Burst Type ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L BURST INTERRUPTION [ Read Interrupted by Read ] Burst read operation can be interrupted by new read of any bank. Random column access is allowed READ to READ interval is minimum 1 CLK.. Read Interrupted by Read (BL=4, CL=3) CLK READ READ Command Yi Yj A0-9 A10 0 0 A11 ...
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... M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L [ Read Interrupted by Precharge ] Burst read operation can be interrupted by precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency result, READ to PRE interval determines valid data length to be output. The figure below shows examples of BL=4 ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L [ Write Interrupted by Write ] Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. CLK Command Write Write A0 A10 0 0 A11 BA0 Dai0 Daj0 Daj1 Dbk0 [ Write Interrupted by Read ] Burst write operation can be interrupted by read of the same or the other bank ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L [ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank. Random column access is allowed. Write recovery time (tWR) is required from the last data to PRE command. Write Interrupted by Precharge (BL=4) CLK Write Command ...
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... M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 128Mbit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto-refresh, all banks must be in the idle state ...
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... M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-refresh is initiated maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input ,all other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved ...
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... M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L CLK SUSPEND CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. ...
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... M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L DQM CONTROL DQM is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQM masks input data word by word. DQM to write mask latency is 0. During reads, DQM forces output to Hi-Z word by word. DQM to output Hi-Z latency is 2. ...
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... Parameter CI(A) Input Capacitance, address pin Input Capacitance, contorl pin CI(C) CI(K) Input Capacitance, CLK pin CI/O Input Capacitance, I/O pin M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Conditions with respect to Vss with respect to VssQ with respect to Vss with respect to VssQ Ta = 25ºC Test Condition @ 1MHz 1.4V bias 200mV swing Vcc=3.3V ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L AVERAGE SUPPLY CURRENT from Vdd (Ta=0 – 70ºC, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted ) ITEM operating current tRC=min, tCLK =min, BL=1 , CL=3 precharge standby current in Non Power down mode /CS > Vcc -0.2V precharge standby current in Power down mode /CS > ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L AC TIMING REQUIREMENTS (Ta=0 – 70ºC, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted ) Input Pulse Levels: Input Timing Measurement Level: Parameter Symbol tCLK CLK cycle time tCH CLK High pulse width tCL CLK Low pulse width ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L SWITCHING CHARACTERISTICS (Ta=0 – 70ºC, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted ) Symbol Parameter tAC Access time from CLK Output Hold time from CLK tOH Delay time, output low- tOLZ impedance from CLK ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Burst Write (single bank) @BL CLK /CS /RAS tRCD /CAS /WE CKE DQM X A0-8 X A10 X A9,11 0 BA0 ACT tRC tRAS tRP tWR WRITE#0 PRE#0 MITSUBISHI ELECTRIC 128M Synchronous DRAM ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Burst Write (multi bank) @BL CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0 A10 X X A9, BA0 ACT#0 ACT tRC tRAS tWR WRITE#0 ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Burst Read (single bank) @BL=4 CL CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-8 X A10 X A9,11 X BA0 ACT tRC tRAS tRP DQM read latency = CL READ#0 PRE#0 READ to PRE ³BL allows full data out ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Burst Read (multiple bank) @BL=4 CL CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A10 X X A9,11 BA0 ACT#0 ACT tRC tRAS DQM read latency = CL=3 CL ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Burst Write (multi bank) with Auto-Precharge @BL CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0 A10 X X A9, BA0 ACT#0 ACT tRC BL-1+ tWR + tRP ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Burst Read (multiple bank) with Auto-Precharge @BL=4 CL CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A10 X X A9,11 BA0 ACT#0 ACT tRC BL+tRP DQM read latency = ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Page Mode Burst Write (multi bank) @BL CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0 A10 X X A9, BA0 ACT#0 ACT WRITE#0 ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Page Mode Burst Read (multi bank) @BL=4 CL CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0 A10 X X A9, BA0 ACT#0 ACT DQM read latency CL=3 CL READ#0 READ#0 ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Write Interrupted by Write / Read @BL CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A10 X X A9,11 BA0 ACT#0 WRITE#0 ACT#1 Burst Write can be interrupted by Write or Read of any active bank ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Read Interrupted by Read / Write @BL=4 CL CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A0 A10 X X A9, BA0 ACT#0 ACT#1 Burst Read can be interrupted by Read or Write of any active bank DQM read latency=2 ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Write Interrupted by Precharge @BL CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A10 X X A9,11 BA0 ACT#0 WRITE#0 ACT#1 Burst Write is not interrupted by Precharge of the other bank ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Read Interrupted by Precharge @BL=4 CL CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQM A10 X X A9, BA0,1 DQ ACT#0 ACT#1 Burst Read is not interrupted by Precharge of the other bank DQM read latency=2 ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Mode Register Setting CLK /CS /RAS /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ Auto-Ref (last of 8 cycles tRC M 0 Mode Register Setting MITSUBISHI ELECTRIC 128M Synchronous DRAM (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Auto-Refresh @BL CLK /CS /RAS /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ Auto-Refresh Before Auto-Refresh, all banks must be idle state tRC ACT#0 After tRC from Auto-Refresh, all banks are idle state. ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Self-Refresh CLK /CS /RAS /CAS /WE CKE CKE must be low to maintain Self-Refresh DQM A0-8 A10 A9,11 BA0,1 DQ Self-Refresh Entry Before Self-Refresh Entry, all banks must be idle state CLK can be stopped tSRX Self-Refresh Exit After tRC from Self-Refresh Exit, all banks are idle state ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L DQM Write Mask @BL CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-8 X A10 X A9, BA0,1 DQ ACT masked WRITE#0 WRITE#0 MITSUBISHI ELECTRIC 128M Synchronous DRAM (4-BANK x 8,388,608-WORD x 4-BIT) ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L DQM Read Mask @BL=4 CL CLK /CS /RAS tRCD /CAS /WE CKE DQM X A0-8 X A10 X A9,11 0 BA0,1 DQ ACT DQM read latency READ#0 READ#0 MITSUBISHI ELECTRIC 128M Synchronous DRAM ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Power Down CLK /CS /RAS /CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ Precharge All Standby Power Down CKE latency ACT#0 MITSUBISHI ELECTRIC 128M Synchronous DRAM (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) ...
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... SDRAM (Rev. 1.0E) M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L CLK Suspend @BL=4 CL CLK /CS /RAS tRCD /CAS /WE CKE CKE latency=1 DQM X A0-8 X A10 X A9,11 BA0 ACT#0 WRITE CKE latency READ#0 CLK suspended MITSUBISHI ELECTRIC 128M Synchronous DRAM ...
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... M2V28S20ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 M2V28S30ATP -6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage ...