M5M5V416BWG-70HI MITSUBISHI, M5M5V416BWG-70HI Datasheet
M5M5V416BWG-70HI
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M5M5V416BWG-70HI Summary of contents
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... The M5M5V416B is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv es. M5M5V416BWG is packaged in a CSP (chip scale package), with the outline of 7mm x 8.5mm, ball matrix (48pin) and ball pitch of 0.75mm. It giv es the best solution compaction of mounting area as well as f lexibility of wiring pattern of printed circuit boards ...
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... M5M5V416BWG FUNCTION The M5M5V416BWG is organized as 262,144-words by 16-bit. These dev ices operate on a single +2.7~3.6V power supply , and are directly TTL compatible to both input and output. Its f ully s t atic circuit needs no clocks and no ref resh, and makes it usef ul. The operation mode are determined by a combination of the dev ice control inputs BC1 , BC2 , S1 and OE ...
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... M5M5V416BWG ABSOLUTE MAXIMUM RATINGS Symbol Parameter V cc Supply v oltage V Input v oltage I V Output v oltage O P Power dissipation d Operating T a temperature Storage temperature T stg DC ELECTRICAL CHARACTERISTICS Symbol Parameter V High-lev el input v oltage IH V Low-lev el input v oltage IL V High-level output voltage 1 OH1 V High-level output voltage 2 ...
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... M5M5V416BWG AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS Supply v oltage Input pulse Input rise time and f all time Ref erence lev el Output loads (2) READ CYCLE Parameter Symbol t Read cy cle time CR t (A) Address access time a t (S1) Chip select 1 access time a t (S2) Chip select 2 access time ...
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... M5M5V416BWG (4)TIMING DIAGRAMS Read cycle A 0~17 BC1,BC2 (Note3) S1 (Note3) S2 (Note3) OE (Note3 "H" lev el DQ 1~16 Write cycle ( W control mode ) A 0~17 BC1,BC2 (Note3) S1 (Note3) S2 (Note3 1~16 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM ( (BC1) (BC2 (S1 (S2 (OE) ...
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... M5M5V416BWG Write cycle (BC control mode) A 0~17 BC1,BC2 S1 (Note3) S2 (Note3) (Note5) W (Note3) DQ 1~16 Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during S1 low, S2 high ov erlaps BC1 and/or BC2 low and W low. Note 5: When the f alling edge simultaneously or prior to the f alling edge of BC1 and/or BC2 or the f alling edge rising edge of S2, the outputs are maintained in the high impedance state ...
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... M5M5V416BWG Write cycle (S1 control mode) A 0~17 BC1,BC2 (Note3 (Note3) W (Note3) DQ 1~16 Write cycle (S2 control mode) A 0~17 BC1,BC2 (Note3 (Note3) W (Note3) DQ 1~16 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM (S1 (A) su (Note5) (Note4) t (D) su DATA IN STABLE (S2 (A) su (Note5) (Note4) ...
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... M5M5V416BWG POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Parameter Vcc Power down supply voltage (PD (BC) Byte control input BC1 & BC2 V I (S1) Chip select input (S2) Chip select input S2 Power down Icc (PD) supply c urrent (2) TIMING REQUIREMENTS Symbol Parameter t Power down set up time ...
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... M5M5V416BWG Revision History Revision No. History W01 The first edition W02 Font problem fixed W03 70ns version added 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM Date ' ' ' MITSUBISHI ELECTRIC MITSUBISHI LSIs PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change ...
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C 0.1 (8.3) 8.5TYP B C 0.2 ...