M38B59MFH-P113FP MITSUBISHI, M38B59MFH-P113FP Datasheet
M38B59MFH-P113FP
Related parts for M38B59MFH-P113FP
M38B59MFH-P113FP Summary of contents
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... MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES ADVANCED AND EVER ADVANCING 38B5 Group User’s Manual MITSUBISHI ELECTRIC MITSUBISHI ELECTRIC ...
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... Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials ...
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... Preface This user’s manual describes Mitsubishi’s CMOS 8- bit microcomputers 38B5 Group. After reading this manual, the user should have a through knowledge of the functions and features of the 38B5 Group, and should be able to fully utilize the product. The manual starts with specifications and ends with application examples. For details of software, refer to the “ ...
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BEFORE USING THIS USER’S MANUAL This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. 1. Organization CHAPTER 1 HARDWARE This chapter describes features of the ...
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Table of contents CHAPTER 1 HARDWARE DESCRIPTION ................................................................................................................................ 1-2 FEATURES .................................................................................................................................... 1-2 APPLICATION ................................................................................................................................ 1-2 PIN CONFIGURATION .................................................................................................................. 1-2 FUNCTIONAL BLOCK .................................................................................................................. 1-3 PIN DESCRIPTION ........................................................................................................................ 1-4 PART NUMBERING ....................................................................................................................... 1-6 GROUP EXPANSION .................................................................................................................... 1-7 Memory Type ............................................................................................................................ 1-7 Memory ...
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Table of contents 2.2.3 Timer application examples ........................................................................................ 2-19 2.3 Serial I/O ................................................................................................................................ 2-35 2.3.1 Memory map ................................................................................................................. 2-35 2.3.2 Relevant registers ........................................................................................................ 2-36 2.3.3 Serial I/O1 connection examples ............................................................................... 2-47 2.3.4 Serial I/O1’s modes ..................................................................................................... 2-49 2.3.5 Serial I/O1 ...
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CHAPTER 3 APPENDIX 3.1 Electrical characteristics ..................................................................................................... 3-2 3.1.1 Absolute maximum ratings ............................................................................................ 3-2 3.1.2 Recommended operating conditions ............................................................................ 3-3 3.1.3 Electrical characteristics ................................................................................................ 3-4 3.1.4 A-D converter characteristics ....................................................................................... 3-5 3.1.5 Timing requirements and switching characteristics ................................................... 3-6 3.2 ...
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List of figures CHAPTER 1 HARDWARE Fig. 1 Pin configuration of M38B5xMxH-XXXXFP ..................................................................... 1-2 Fig. 2 Functional block diagram ................................................................................................... 1-3 Fig. 3 Part numbering .................................................................................................................... 1-6 Fig. 4 Memory expansion plan ..................................................................................................... 1-7 Fig. 5 740 Family CPU register ...
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List of figures Fig. 46 Example of using FLD automatic display RAM in 16-timing•gradation display mode ........................................................................................................................................................ 1-45 Fig. 47 Example of using FLD automatic display RAM in 32-timing mode ......................... 1-46 Fig. 48 Structure of FLDRAM write disable register ...
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Fig. 2.2.2 Structure of Timer i (i= ....................................................................... 2-11 Fig. 2.2.3 Structure of Timer 2 .................................................................................................. 2-11 Fig. 2.2.4 Structure of Timer 6 PWM register ......................................................................... 2-11 Fig. 2.2.5 Structure of Timer 12 mode register ....................................................................... ...
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List of figures Fig. 2.3.22 Registers setting relevant to transmission side ................................................... 2-51 Fig. 2.3.23 Setting of transmission data ................................................................................... 2-51 Fig. 2.3.24 Control procedure..................................................................................................... 2-52 Fig. 2.3.25 Connection diagram ................................................................................................. 2-53 Fig. 2.3.26 Timing chart of serial data transmission/reception ...
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Fig. 2.4.17 Enlarged view of FLD Fig. 2.4.18 Setting of relevant registers ................................................................................... 2-94 Fig. 2.4.19 FLD digit allocation example .................................................................................. 2-97 Fig. 2.4.20 Control procedure..................................................................................................... 2-98 Fig. 2.4.21 Connection diagram ............................................................................................... 2-100 Fig. 2.4.22 Timing chart of key-scan using ...
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List of figures Fig. 2.7.8 Function block diagram ........................................................................................... 2-140 Fig. 2.7.9 Timing chart of data determination ........................................................................ 2-140 Fig. 2.7.10 Setting of relevant registers ................................................................................. 2-141 Fig. 2.7.11 Control procedure................................................................................................... 2-142 Fig. 2.7.12 Reception of remote-control data (timer 2 ...
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Fig. 3.3.9 Status flag at decimal calculations .......................................................................... 3-23 Fig. 3.3.10 Programming and testing of One Time PROM version ...................................... 3-23 Fig. 3.4.1 Selection of packages ............................................................................................... 3-26 Fig. 3.4.2 Wiring for the RESET pin ......................................................................................... 3-26 Fig. 3.4.3 Wiring ...
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List of figures Fig. 3.5.39 Structure of interrupt request register 2 ............................................................... 3-55 Fig. 3.5.40 Structure of interrupt control register 1 ................................................................ 3-56 Fig. 3.5.41 Structure of interrupt control register 2 ................................................................ 3-57 Fig. 3.5.42 Structure of pull-up control register ...
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List of tables CHAPTER 1 HARDWARE Table 1 Pin description (1) ........................................................................................................... 1-4 Table 2 Pin description (2) ........................................................................................................... 1-5 Table 3 List of supported products ............................................................................................. 1-7 Table 4 Push and pop instructions of accumulator or processor status register ...
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HARDWARE DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION FUNCTIONAL BLOCK PIN DESCRIPTION PART NUMBERING GROUP EXPANSION FUNCTIONAL DESCRIPTION NOTES ON PROGRAMMING NOTES ON USE ...
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HARDWARE DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION DESCRIPTION The 38B5 group is the 8-bit microcomputer based on the 740 family core technology. The 38B5 group has six 8-bit timers, a 16-bit timer, a fluorescent dis- play automatic display circuit, 12-channel 10-bit A-D converter, a ...
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FUNCTIONAL BLOCK Fig. 2 Functional block diagram 38B5 Group User’s Manual HARDWARE FUNCTIONAL BLOCK 1-3 ...
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HARDWARE PIN DESCRIPTION PIN DESCRIPTION Table 1 Pin description (1) Pin Name Power source • Apply voltage of 4.0–5 Pull-down • Apply voltage supplied to pull-down resistors of ports P0, P1, ...
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Table 2 Pin description (2) Pin Name I/O port P5 • 8-bit CMOS I/O port with the same function as port P0. 0 IN1 • CMOS compatible input level. 1 OUT1 ...
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HARDWARE PART NUMBERING PART NUMBERING Product M38B5 XXXX FP Fig. 3 Part numbering 1-6 Package type FP : 80P6N-A package FS : 80D0 package ROM number Omitted in One Time PROM version shipped in blank ...
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... RAM size (bytes) 1024 1024 2048 2048 2048 2048 38B5 Group User’s Manual HARDWARE GROUP EXPANSION Mass product M38B59EF M38B59MFH New product 1,536 2,048 As of Nov. 1998 Package Remarks Mask ROM version 80P6N-A Corresponded to mask option 80P6N-A Mask ROM version ...
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HARDWARE FUNCTIONAL DESCRIPTION FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 38B5 group uses the standard 740 Family instruction set. Re- fer to the table of 740 Series addressing modes and machine instructions or the 740 Series Software Manual for details ...
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...
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HARDWARE FUNCTIONAL DESCRIPTION [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch opera- tions ...
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Mode Register (CPUM)] 003B The CPU mode register contains the stack page selection bit and the internal system clock selection bit etc. The CPU mode register is allocated at address 003B b7 b0 CPU mode register ( CPUM: address ...
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HARDWARE FUNCTIONAL DESCRIPTION Memory Special function register (SFR) area The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of ...
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Port P0 (P0) 16 Port P0 direction register (P0D) 0001 16 Port P1 (P1) 0002 16 0003 16 Port P2 (P2) 0004 16 Port P2 direction register (P2D) 0005 16 Port P3 (P3) 0006 16 0007 16 Port P4 ...
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HARDWARE FUNCTIONAL DESCRIPTION I/O Ports [Direction Registers] PiD The 38B5 group has 55 programmable I/O pins arranged in eight individual I/O ports (P0, P2, P4 –P4 , and P5–P9). The I/O ports 0 6 have direction registers which determine the ...
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Table 6 List of I/O port functions (1) Pin Name Input/Output P0 /FLD – Port P0 Input/output, CMOS compatible input level FLD automatic display function FLDC mode register /FLD individual bits High-breakdown voltage channel ...
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HARDWARE FUNCTIONAL DESCRIPTION Table 7 List of I/O port functions (2) Pin Name Input/Output P8 /FLD – Port P8 Input/output /FLD individual bits /FLD /RTP / 5 0 FLD , 37 ...
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Ports P0, P2 – FLD/Port switch register Dimmer signal (Note 1) Direction register Local data bus Port latch Data bus (3) Port P2 0 FLD/Port switch register Dimmer signal (Note 1) Local data Direction register ...
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HARDWARE FUNCTIONAL DESCRIPTION (8) Port P4 7 Data bus INT interrupt 2 input (10) Ports P5 – P-channel output disable signal (P5 Output OFF control signal Serial I/O2 mode selection bit Direction register ...
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Ports Dimmer output control bit (P6 Direction register Data bus Port latch Dimmer signal output (P6 A-D conversion input (16) Port pin control bit 5 STB1 Direction register Data bus Port ...
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HARDWARE FUNCTIONAL DESCRIPTION Interrupts Interrupts occur by twenty one sources: five external, fifteen internal, and one software. (1) Interrupt Control Each interrupt except the BRK instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is ...
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Table 8 Interrupt vector addresses and priority Vector Addresses (Note 1) Interrupt Source Priority High Reset (Note 2) 1 FFFD 16 INT 2 FFFB 0 16 INT 3 FFF9 1 16 INT 4 FFF7 2 16 Remote control/ counter overflow ...
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HARDWARE FUNCTIONAL DESCRIPTION Interrupt request bit Interrupt enable bit Fig. 14 Interrupt control b7 b0 Interrupt source switch register (IFR : address 0039 INT /serial I/O2 transmit interrupt switch bit (Note INT interrupt ...
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Timers 8-Bit Timer The 38B5 group has six built-in timers : Timer 1, Timer 2, Timer 3, Timer 4, Timer 5, and Timer 6. Each timer has the 8-bit timer latch. All timers are down-counters. When the timer reaches “00 ...
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HARDWARE FUNCTIONAL DESCRIPTION X CIN 1OUT P6 /CNTR /CNTR /T3 6 OUT P6 /CNTR 0 1 (Note) P4 /PWM 4 1 Fig. 17 Block diagram of timer 1-24 1/2 Timer 1 ...
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Timer 6 count source Timer 6 PWM mode Timer 6 interrupt request Fig. 18 Timing chart of timer 6 PWM mode (n+m) ts Note: PWM waveform (duty : n/( and period ...
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HARDWARE FUNCTIONAL DESCRIPTION 16-Bit Timer Timer 16-bit timer that can be selected in one of four modes by the Timer X mode registers 1, 2 and can be controlled the timer X write and the real time ...
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Real time port control bit “1” “0” P8 direction 5 register P8 latch 5 Real time port “1” control bit P8 6 “0” P8 direction 6 register P8 latch 6 X CIN 1/2 Internal system clock @“1” selection ...
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HARDWARE FUNCTIONAL DESCRIPTION Serial I/O Serial I/O1 Serial I/O1 is used as the clock synchronous serial I/O and has an ordinary mode and an automatic transfer mode. In the automatic transfer mode, serial transfer is performed through the serial I/O ...
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Fig. 22 Structure of serial I/O1 control registers Serial I/O1 control register 1 (SIO1CON1 (SC11): address 0019 ) 16 Serial transfer selection bits 00: Serial I/O disabled (pins P6 ,P6 , 01: ...
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HARDWARE FUNCTIONAL DESCRIPTION (1) Serial I/O1 Operation Either the internal synchronous clock or external synchronous clock can be selected by the serial I/O1 synchronous clock selection bits (b2 and b3 of address 0019 ) of serial I/O1 control register 1 ...
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Serial I/O Mode Address 001B is assigned to the serial I/O1 register. 16 When the internal synchronous clock is selected, a serial transfer of the 8-bit serial I/O is started by a write signal to the serial I/O1 ...
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HARDWARE FUNCTIONAL DESCRIPTION Automatic transfer data pointer 52 16 Fig. 25 Automatic transfer serial I/O operation 1-32 Automatic transfer RAM FFF 16 F52 16 F51 16 F50 16 F4F 16 F4E 16 F00 16 S IN1 Serial I/O1 register 38B5 ...
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Handshake Signal 1. S output signal STB1 The S output is a signal to inform an end of transmission/re- STB1 ception to the serial transfer destination . The S can be used only when the internal synchronous clock is ...
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HARDWARE FUNCTIONAL DESCRIPTION When the internal synchronous clock is selected, in the 8-bit serial I/O mode and the automatic transfer serial I/O mode (S put function outputs in 1-byte units), the S and the S output goes to “H” before ...
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S output signal RDY1 The S output is a transmit/receive enable signal which informs RDY1 the serial transfer destination that transmit/receive is ready. In the initial status, when the serial I/O initialization bit (b4) is reset to “0,” the ...
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HARDWARE FUNCTIONAL DESCRIPTION S CLK1 S RDY1 S BUSY1 A: Internal synchronous clock selection Fig. 34 Handshake operation at serial I/O1 mutual connecting (1) S CLK1 S RDY1 S BUSY1 A: Internal synchronous clock selection Fig. 35 Handshake operation at ...
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Serial I/O2 Serial I/O2 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation during serial I/O2 operation. (1) Clock Synchronous Serial I/O Mode ...
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HARDWARE FUNCTIONAL DESCRIPTION (2) Asynchronous Serial I/O (UART) Mode The asynchronous serial I/O (UART) mode can be selected by clear- ing the serial I/O2 mode selection bit (b6) of the serial I/O2 control register (address 001D ) to “0.” Eight ...
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I/O2 Control Register] SIO2CON (001D The serial I/O2 control register contains eight control bits for serial I/O2 functions. [UART Control Register] UARTCON (0017 This bit register containing four control bits, which are valid when UART is ...
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HARDWARE FUNCTIONAL DESCRIPTION FLD Controller The 38B5 group has fluorescent display (FLD) drive and control cir- cuits. The FLD controller consists of the following components: •40 pins for FLD control pins •FLDC mode register •FLD data pointer •FLD data pointer ...
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Mode Register] FLDM The FLDC mode register is a 8-bit register respectively which is used to control the FLD automatic display and to set the blanking time Tscan for key-scan. b7 Notes 1: When a gradation display mode is ...
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HARDWARE FUNCTIONAL DESCRIPTION FLD automatic display pins When the automatic display control bits of the FLDC mode register (address 0EF4 ) are set to “1,” the ports of P0, P1, P2, P3 and P8 16 are used as FLD automatic ...
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FLD automatic display RAM The FLD automatic display RAM uses the 160 bytes of addresses 0F60 to 0FFF . For FLD, the 3 modes of 16-timing ordinary mode 16-timing•gradation display mode and 32-timing mode are available depending on ...
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HARDWARE FUNCTIONAL DESCRIPTION Data setup (1) 16-timing•Ordinary Mode The area of addresses 0FB0 16 FLD automatic display RAM. When data is stored in the FLD automatic display RAM, the last data of FLD port P2 is stored at address 0FB0 ...
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Number of FLD segments: 25 Number of timing: 15 (FLD data pointer reload register = 14) Bit Address 0FB0 16 0FB1 16 0FB2 16 0FB3 16 0FB4 16 0FB5 16 0FB6 16 0FB7 ...
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HARDWARE FUNCTIONAL DESCRIPTION Number of FLD segments: 18 Number of timing: 20 (FLD data pointer reload register = 19) Bit Address 0FB0 16 0FB1 16 0FB2 16 0FB3 16 0FB4 16 0FB5 16 ...
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Digit data protect function The FLD automatic display RAM is provided with a data protect function that disables the RAM area data to be rewritten as digit data. This function can disable data from being written in optional bits in ...
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HARDWARE FUNCTIONAL DESCRIPTION Setting method when using the grid scan type FLD When using the grid scan type FLD, set “1” in the RAM area corre- sponding to the digit ports that output “1” at each timing. Set “0” in ...
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Timing setting Each timing is set by the FLDC mode register, Tdisp time set regis- ter, Toff1 time set register, and Toff2 time set register. •Tdisp time setting Set the Tdisp time by the Tdisp counter count source selection bit ...
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HARDWARE FUNCTIONAL DESCRIPTION Segment Digit output FLD digit interrupt request occurs at the rising edge of digit (each timing). Segment Digit Segment Digit Fig. 51 FLDC timing 1-50 Repeat synchronous Tdisp Tn Tn-1 Tn FLD blanking ...
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FLD output reverse function are provided with a function to reverse the polarity of the 4 7 FLD output. This function is useful in adjusting the polarity when using an externally installed ...
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HARDWARE FUNCTIONAL DESCRIPTION A-D Converter The 38B5 group has a 10-bit A-D converter. The A-D converter per- forms successive approximation conversion. [A-D Conversion Register] AD One of these registers is a high-order register, and the other is a low- order ...
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Pulse Width Modulation (PWM) The 38B5 group has a PWM function with a 14-bit resolution. When the oscillation frequency MHz, the minimum resolution bit IN width is 250 ns and the cycle period is 4096 µs. The ...
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HARDWARE FUNCTIONAL DESCRIPTION 1. Data setup The PWM output pin also function as port P8 PWM output pin by setting bit 0 of the PWM control register (address 0026 ) to “1.” The high-order 8 bits of output data are ...
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Fig. 58 Structure of PWM control register Data 6A stored at address 0014 16 PWM register 59 16 (high-order) Data 24 stored at address 0015 16 PWM register 13 (low-order) 16 PWM latch 1653 16 (14-bit ...
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HARDWARE FUNCTIONAL DESCRIPTION Interrupt Interval Determination Function The 38B5 group has an interrupt interval determination circuit. This interrupt interval determination circuit has an 8-bit binary up counter. Using this counter, it determines a duration of time from the rising edge ...
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Fig. 61 Structure of interrupt interval determination control register (When IIDCON = “0”) 4 Noise filter sampling clock INT pin 2 Acceptance of interrupt Counter sampling clock 8-bit binary up counter value Interrupt interval determination register value Remote control ...
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HARDWARE FUNCTIONAL DESCRIPTION Watchdog Timer The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software runaway). The watchdog timer consists of an 8-bit ...
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Buzzer Output Circuit The 38B5 group has a buzzer output circuit. One of 1 kHz, 2 kHz and 4 kHz ( 4.19 MHz) frequencies can be selected by the buzzer IN output control register (address 0EFD ). Either ...
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HARDWARE FUNCTIONAL DESCRIPTION Reset Circuit ______ To reset the microcomputer, RESET pin should be held at an “L” ______ level for 2 µs or more. Then the RESET pin is returned to an “H” level (the power source voltage should ...
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Port P0 (2) Port P0 direction register (3) Port P1 (4) Port P2 (5) Port P2 direction register Port P3 (6) (7) Port P4 (8) Port P4 direction register (9) Port P5 (10) Port P5 direction register (11) Port ...
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HARDWARE FUNCTIONAL DESCRIPTION Clock Generating Circuit The 38B5 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between and X ). Use the circuit constants in accordance with OUT CIN ...
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X X COUT CIN “1” Reset Interrupt disable flag l Interrupt request Notes 1: When low-speed mode is selected, set the port Xc switch bit (b4) to “1.” 2: Refer to the structure of ...
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HARDWARE FUNCTIONAL DESCRIPTION Reset Middle-speed mode MHz) “1” CM =0(4 MHz selected =1(middle-speed =0(X oscillating =0(32 kHz stopped) 4 Middle-speed mode ( =1 MHz) “1” CM =0(4 MHz selected) 7 ...
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NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1.” After a reset, initialize flags which affect program execution. In particular, ...
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HARDWARE DATA REQUIRED FOR MASK ORDERS/DATA REQUIRED FOR ROM WRITING ORDERS/ROM PROGRAMMING METHOD DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc- tion: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) ...
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MASK OPTION OF PULL-DOWN RESISTOR (object product: M38B5XMXH-XXXFP) Whether built-in pull-down resistors are connected or not to high- breakdown voltage ports and ordering mask ROM. The option type can be specified from among ...
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HARDWARE MASK OPTION OF PULL-DOWN RESISTOR Power Dissipation Calculating example 2 (when 2 or more digit is turned ON at same time) Fixed number depending on microcomputer’s standard • V output fall voltage of high-breakdown port (max.); ...
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FUNCTIONAL DESCRIPTION SUPPLEMENT Interrupt 38B5 group permits interrupts on the basis of 21 sources vector interrupts with a fixed priority system. Accordingly, when two or more interrupt requests occur during the same sampling, the Table 13 Interrupt sources, ...
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HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT Timing After Interrupt The interrupt processing routine begins with the machine cycle fol- lowing the completion of the instruction that is currently in execution. Figure 78 shows a timing chart after an interrupt occurs, and Figure ...
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A-D Converter A-D conversion is started by setting AD conversion completion bit to “0.” During A-D conversion, internal operations are performed as fol- lows. 1. After the start of A-D conversion, A-D conversion register goes to “00 .” ...
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HARDWARE FUNCTIONAL DESCRIPTION SUPPLEMENT Figures 80 shows the A-D conversion equivalent circuit, and Figure 81 shows the A-D conversion timing chart ...
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APPLICATION 2.1 I/O port 2.2 Timer 2.3 Serial I/O 2.4 FLD controller 2.5 A-D converter 2.6 PWM 2.7 Interrupt interval determination function 2.8 Watchdog timer ...
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APPLICATION 2.1 I/O port 2.1 I/O port This paragraph describes the setting method of I/O port relevant registers, notes etc. 2.1.1 Memory assignment Address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 ...
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Relevant registers Port Fig. 2.1.2 Structure of port Port Fig. ...
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APPLICATION 2.1 I/O port Port Pi direction register Fig. 2.1.5 Structure of port direction register Port P6 direction register ...
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Port P9 direction register Fig. 2.1.7 Structure of port P9 direction register Pull-up control register Fig. 2.1.8 Structure of pull-up control register 1 ...
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APPLICATION 2.1 I/O port Pull-up control register Fig. 2.1.9 Structure of pull-up control register 2 2.1.3 Terminate unused pins Table 2.1.1 Termination of unused pins Pins P1, P3 Open at “H” ...
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Notes on use (1) Notes in standby state 1 In standby state for low-power dissipation, do not make input levels of an input port and an I/O port “undefined”, especially for I/O ports of the P-channel open-drain and the ...
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APPLICATION 2.1 I/O port (3) Modifying port latch of I/O port with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction unspecified bit may be changed. Reason The bit managing instructions ...
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Termination remarks Input ports and I/O ports : Do not open in the input mode. Reason • The power source current may increase depending on the first-stage circuit. • An effect due to noise may be easily produced as ...
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APPLICATION 2.2 Timer 2.2 Timer This paragraph explains the registers setting method and the notes relevant to the timers. 2.2.1 Memory map ...
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Relevant registers (1) 8-bit timer Timer Fig. 2.2.2 Structure of Timer i (i= Timer Fig. 2.2.3 Structure ...
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APPLICATION 2.2 Timer Timer 12 mode register Fig. 2.2.5 Structure of Timer 12 mode register Timer 34 mode register Fig. 2.2.6 Structure of Timer ...
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Timer 56 mode register Fig. 2.2.7 Structure of Timer 56 mode register (2) 16-bit timer Timer X (low-order, high-order Fig. 2.2.8 Structure of Timer ...
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APPLICATION 2.2 Timer Timer X mode register Fig. 2.2.9 Structure of Timer X mode register 1 2-14 Timer X mode register 1 (TXM1: address Name Functions Timer ...
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Timer X mode register Fig. 2.2.10 Structure of Timer X mode register 2 Timer X mode register 2 (TXM2: address Name Functions 0 Real time port control ...
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APPLICATION 2.2 Timer (3) 8-bit timer, 16-bit timer Interrupt request register Fig. 2.2.11 Structure of Interrupt request register 1 2-16 Interrupt request register 1 (IREQ1 : address ...
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Interrupt request register Fig. 2.2.12 Structure of Interrupt request register 2 Interrupt request register 2 (IREQ2 : address Name Functions Timer 4 interrupt ...
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APPLICATION 2.2 Timer Interrupt control register Fig. 2.2.13 Structure of Interrupt control register 1 Interrupt control register Fig. 2.2.14 Structure of ...
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Timer application examples (1) Basic functions and uses [Function 1] Control of event interval (Timer 1 to Timer 6, Timer X: timer mode) When a certain time, by setting a count value to each timer, has passed, the timer ...
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APPLICATION 2.2 Timer (2) Timer application example 1: Clock function (measurement Outline: The input clock is divided by the timer so that the clock can count intervals. Specifications: •The clock f(X •The timer ...
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APPLICATION 2.2 Timer ...
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Timer application example 2: Piezoelectric buzzer output Outline: The rectangular waveform output function of the timer is applied for a piezoelectric buzzer output. Specifications: •The rectangular waveform, dividing the clock f(X 2 kHz (2048 Hz), is output from the ...
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APPLICATION 2.2 Timer ...
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Timer application example 3: Frequency measurement Outline: The following two values are compared to judge whether the frequency is within a valid range. •A value by counting pulses input to P6 •A reference value Specifications: •The pulse is input ...
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APPLICATION 2.2 Timer ...
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...
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APPLICATION 2.2 Timer (5) Timer application example 4: Measurement of FG pulse width for motor Outline: The timer X counts the “H” level width of the pulses input to the P6 underflow is detected by the timer X interrupt and ...
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...
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APPLICATION 2.2 Timer ...
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...
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APPLICATION 2.2 Timer (6) Timer application example 5: Control of stepping motor Outline: The rotating of stepping motor is controlled by using real time output ports. Specifications: •The motor is controlled by using 2 real time output ports. •The count ...
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...
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APPLICATION 2.2 Timer ...
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Serial I/O This paragraph explains the registers setting method and the notes relevant to the serial I/O. 2.3.1 Memory map ...
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APPLICATION 2.3 Serial I/O 2.3.2 Relevant registers (1) Serial I/O1 Serial I/O1 automatic transfer data pointer Fig. 2.3.2 Structure of Serial I/O1 automatic transfer data pointer 2-36 Serial I/O1 automatic transfer data ...
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Serial I/O1 control register Fig. 2.3.3 Structure of Serial I/O1 control register 1 Serial I/O1 control register 1 (SIO1CON1•SC11: address Name Functions 0 b1b0 Serial transfer 0 ...
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APPLICATION 2.3 Serial I/O Serial I/O1 control register Fig. 2.3.4 Structure of Serial I/O1 control register 2 2-38 Serial I/O1 control register 2 (SIO1CON2 • SC12: address ...
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Serial I/O1 register/Transfer counter Fig. 2.3.5 Structure of Serial I/O1 register/Transfer counter Serial I/O1 register/Transfer counter (SIO1: address Name Functions •At function as serial I/O1 •In 8-bit serial ...
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APPLICATION 2.3 Serial I/O Serial I/O1 control register Fig. 2.3.6 Structure of Serial I/O1 control register 3 2-40 Serial I/O1 control register 3 (SIO1CON3 • SC13: address ...
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Serial I/O2 Baud rate generator Fig. 2.3.7 Structure of Baud rate generator UART control register Fig. 2.3.8 Structure of UART control register Baud ...
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APPLICATION 2.3 Serial I/O Serial I/O2 control register Fig. 2.3.9 Structure of Serial I/O2 control register 2-42 Serial I/O2 control register (SIO2CON: address Name Functions 0 0: f(X ...
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Serial I/O2 status register Fig. 2.3.10 Structure of Serial I/O2 status register Serial I/O2 transmit/receive buffer register Fig. 2.3.11 Structure of Serial I/O2 transmit/receive ...
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APPLICATION 2.3 Serial I/O (3) Serial I/O1 and Serial I/O2 Interrupt source switch register Fig. 2.3.12 Structure of Interrupt source switch register Interrupt request register ...
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Interrupt request register Fig. 2.3.14 Structure of Interrupt request register 2 Interrupt request register 2 (IREQ2 : address Name Functions 0 : Timer 4 interrupt No interrupt ...
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APPLICATION 2.3 Serial I/O Interrupt control register Fig. 2.3.15 Structure of Interrupt control register 1 Interrupt control register Fig. 2.3.16 Structure ...
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Serial I/O1 connection examples (1) Control of peripheral IC equipped with CS pin Figure 2.3.17 shows connection examples with peripheral ICs equipped with the CS pin. All examples can use the automatic transfer function ...
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APPLICATION 2.3 Serial I/O (2) Connection with microcomputer Figure 2.3.18 shows connection examples with another microcomputer ...
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Serial I/O1’s modes Figure 2.3.19 shows the serial I/O1’s modes ...
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APPLICATION 2.3 Serial I/O 2.3.5 Serial I/O1 application examples (1) Output of serial data (control of peripheral IC) Outline : Serial communication is performed, connecting ports with the CS pin of a peripheral IC. Figure 2.3.20 shows a connection diagram, ...
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Figure 2.3.22 shows the registers setting relevant to the transmission side, and Figure 2.3.23 shows the setting of transmission data ...
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APPLICATION 2.3 Serial I/O Control procedure: When the registers are set as shown in Figure 2.3.22, the serial I/O1 can transmit 1-byte data by writing data to the serial I/O1 register. Thus, after setting the CS signal to “L”, write ...
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Transmission/Reception using automatic transfer Outline: Serial transmission/reception control is performed, using the serial automatic transfer function. Figure 2.3.25 shows a connection diagram, and Figure 2.3.26 shows a timing chart of serial data transmission/reception. Fig. 2.3.25 Connection diagram Specifications: • ...
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APPLICATION 2.3 Serial I ...
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APPLICATION 2.3 Serial I/O 2.3.6 Serial I/O2 connection examples (1) Control of peripheral IC equipped with CS pin Figure 2.3.29 shows connection examples with peripheral ICs equipped with the CS pin ...
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Connection with microcomputer Figure 2.3.30 shows connection examples with another microcomputer ...
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APPLICATION 2.3 Serial I/O 2.3.7 Serial I/O2’s modes A clock synchronous or clock asynchronous (UART) can be selected for the serial I/O2. Figure 2.3.31 shows the serial I/O2’s modes, and Figure 2.3.32 shows the serial I/O2 transfer data format. S ...
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Serial I/O2 application examples (1) Communication (transmission/reception) using clock synchronous serial I/O Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O. The S signal is used for communication control. RDY2 Figure 2.3.33 shows a ...
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APPLICATION 2.3 Serial I/O Figure 2.3.35 shows the registers setting relevant to the transmission side, and Figure 2.3.36 shows the registers setting relevant to the reception side ...
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APPLICATION 2.3 Serial I/O Figure 2.3.37 shows a control procedure of the transmission side, and Figure 2.3.38 shows a control procedure of the reception side ...
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APPLICATION 2.3 Serial I/O (2) Output of serial data (control of peripheral IC) Outline : Serial communication is performed, connecting port P5 Figure 2.3.39 shows a connection diagram, and Figure 2.3.40 shows a timing chart ...
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Figure 2.3.41 shows the relevant registers setting and Figure 2.3.42 shows the setting of transmission data ...
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APPLICATION 2.3 Serial I/O Figure 2.3.43 shows a control procedure ...
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Cyclic transmission or reception of block data (data of specified number of bytes) between two microcomputers Outline : When the clock synchronous serial I/O is used for communication, synchronization of the clock and the data between the transmitting and ...
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APPLICATION 2.3 Serial I/O The communication is performed according to the timing shown in Figure 2.3.45. In the slave unit, when a synchronous clock is not input within a certain time (heading adjusment time), the next clock input is processed ...
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Fig. 2.3.47 Relevant registers setting in slave unit ...
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APPLICATION 2.3 Serial I/O Control procedure by software: Control in the master unit After setting the relevant registers shown in Figure 2.3.46, the master unit starts transmission or reception of 1-byte data by writing transmission data to the serial I/O2 ...
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Control in the slave unit After setting the relevant registers as shown in Figure 2.3.47, the slave unit becomes the state where a synchronous clock can be received at any time, and the serial I/O2 receive interrupt request bit is ...
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APPLICATION 2.3 Serial I/O (4) Communication (transmission/reception) using asynchronous serial I/O (UART) Outline : 2-byte data is transmitted and received, using the asynchronous serial I/O. Port P5 is used for communication control. 6 Figure 2.3.50 shows a connection diagram, and ...
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Table 2.3.1 shows setting examples of the baud rate generator (BRG) values and transfer bit rate values. Table 2.3.1 Setting examples of baud rate generator values and transfer bit rate values f(X Transfer bit rate BRG count (Note 1) source ...
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APPLICATION 2.3 Serial I/O Figure 2.3.52 shows the registers setting relevant to the transmission side; Figure 2.3.53 shows the registers setting relevant to the reception side. Transmission side Serial I/O2 status register (address 001E b7 SIO2STS Serial I/O2 control register ...
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Reception side Serial I/O2 status register (address 001E b7 SIO2STS Serial I/O2 control register (address 001D SIO2CON UART control register (address 0017 b7 UARTCON 0 Baud rate generator (address 0016 b7 BRG 05 Fig. 2.3.53 ...
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APPLICATION 2.3 Serial I/O Figure 2.3.54 shows a control procedure of the transmission side, and Figure 2.3.55 shows a control procedure of the reception side. RESET Initialization (address 001D SIO2CON UARTCON (address 0017 BRG (address 0016 P5 (address 000A (address ...
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RESET Initialization SIO2CON (address 001D UARTCON (address 0017 BRG (address 0016 P5D (address 000B SIO2STS (address 001E Read out a reception data from TB/RB (address 001F SIO2STS (address 001E SIO2STS (address 001E Read out a reception data from TB/RB (address ...
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APPLICATION 2.3 Serial I/O 2.3.9 Notes on serial I/O1 (1) Clock Using internal clock After setting the synchronous clock to an internal clock, clear the serial I/O interrupt request bit before perform the normal serial I/O transfer or the serial ...
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When using the S output, regardless of the contents of the S STB1 selection bit, this transfer interval for each 1-byte data becomes 2 cycles longer than the value set by the automatic transfer interval set bits of serial I/O1 ...
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APPLICATION 2.3 Serial I/O 2.3.10 Notes on serial I/O2 (1) Notes when selecting clock synchronous serial I/O Stop of transmission operation As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART) serial ...
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Notes when selecting clock asynchronous serial I/O Stop of transmission operation As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear the transmit enable bit to “0” (transmit ...
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APPLICATION 2.3 Serial I/O (5) Data transmission control with referring to transmit shift register completion flag The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is ...
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FLD controller This paragraph describes the setting method of FLD controller relevant registers, notes etc. 2.4.1 Memory assignment Address 003D 16 003F 16 0EF2 16 0EF3 16 0EF4 16 0EF5 16 0EF6 16 0EF7 16 0EF8 16 0EF9 16 ...
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APPLICATION 2.4 FLD controller 2.4.2 Relevant registers P1FLDRAM write disable register Fig. 2.4.2 Structure of P1FLDRAM write disable register 2-84 P1FLDRAM write disable register (P1FLDRAM: address 0EF2 ) 16 b Name Functions ...
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P3FLDRAM write disable register Fig. 2.4.3 Structure of P3FLDRAM write disable register P3FLDRAM write disable register (P3FLDRAM: address 0EF3 ) 16 b Name Functions 0 FLDRAM corre- 0: Operating normally sponding to ...
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APPLICATION 2.4 FLD controller FLDC mode register Fig. 2.4.4 Structure of FLD mode register 2-86 FLDC mode register (FLDM: address 0EF4 ) 16 b Name Functions Automatic display General-purpose ...
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Tdisp time set register Fig. 2.4.5 Structure of Tdisp time set register Tdisp time set register (TDISP: address 0EF5 ) 16 b Functions 0 •Set the Tdisp time. •When a value n ...
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APPLICATION 2.4 FLD controller Toff1 time set register Fig. 2.4.6 Structure of Toff1 time set register Toff2 time set register Fig. 2.4.7 Structure of ...
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FLD data pointer/FLD data pointer reload register Fig. 2.4.8 Structure of FLD data pointer/FLD data pointer reload register Port P0FLD/port switch register Fig. 2.4.9 ...
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APPLICATION 2.4 FLD controller Port P2FLD/port switch register Fig. 2.4.10 Structure of port P2FLD/port switch register Port P8FLD/port switch register Fig. 2.4.11 Structure of ...
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Port P8FLD output control register Fig. 2.4.12 Structure of port P8FLD output control register Interrupt request register Fig. 2.4.13 Structure of interrupt request ...
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APPLICATION 2.4 FLD controller Interrupt control register Fig. 2.4.14 Structure of interrupt control register 2 2-92 Interrupt control register 2 (ICON2 : address Name Functions Timer ...
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FLD controller application examples (1) Key-scan using FLD automatic display and segments Outline: Key read-in with segment pins is performed by software using the FLD automatic display mode – ...
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APPLICATION 2.4 FLD controller Figure 2.4.18 shows the setting of relevant registers ...
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APPLICATION 2.4 FLD controller Setting of FLD automatic display RAM: Table 2.4.1 FLD automatic display RAM map ...
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Fig. 2.4.19 FLD digit allocation example Table 2.4.2 FLD automatic display RAM map example 1 t ...
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APPLICATION 2.4 FLD controller Control procedure ...
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APPLICATION 2.4 FLD controller (2) Key-scan using FLD automatic display and digits Outline: Key read-in with digit output waveforms is performed by software using the FLD automatic display mode ...
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Figure 2.4.22 shows the timing chart of key-scan ...
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APPLICATION 2.4 FLD controller Figure 2.4.23 shows the setting of relevant registers ...
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APPLICATION 2.4 FLD controller Setting of FLD automatic display RAM: Table 2.4.3 FLD automatic display RAM map ...
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Fig. 2.4.24 FLD digit allocation example Table 2.4.4 FLD automatic display RAM map example 1 t ...
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APPLICATION 2.4 FLD controller Control procedure ...
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APPLICATION 2.4 FLD controller (3) FLD display by software (example of not used FLD controller) Outline: FLD display and key read-in is performed, using a timer interrupt – ...
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Figure 2.4.29 shows the setting of relevant registers ...
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APPLICATION 2.4 FLD controller Fig. 2.4.30 FLD digit allocation example Table 2.4.5 FLD automatic display RAM map example A d ...
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Control procedure ...
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APPLICATION 2.4 FLD controller (4) Display by combination with digit expander (M35501FP*) (basic combination example) * For M35501FP, refer to section “3.12 M35501FP”. Outline: The fluorescent display which has many display numbers (36 segments displayed by using the digit expander ...