PEB3065N Infineon Technologies AG, PEB3065N Datasheet
PEB3065N
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ICs for Communications Signal Processing Subscriber Line Interface Codec Filter ® SLICOFI PEB 3065 Version 3.2 PEF 3065 Version 3.2 Data Sheet 01. ...
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PEB 3065 PEF 3065 Revision History: Previous Version: Page Page (in previous (in current Version) Version) Edition 01.98 Published by Siemens AG, HL TS, Balanstraße 73, 81541 München © Siemens AG 1997. All Rights Reserved. Attention please! As far as ...
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Table of Contents 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 9.3 DC-Feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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General Description The Signal Processing (PEB 3065/PEF 3065 logic continuation of the well established family of the SIEMENS PCM-Codec-Filter-IC’s with the vertical integration of all DC-feeding, Supervision and Meterpulse Injection features on chip as well. Fabricated in ...
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Signal Processing Subscriber Line Interface Codec Filter ® SLICOFI Data Sheet for the Version 3.2 1.1 Features • Single chip CODEC and FILTER including all LOW VOLTAGE SLIC functions • Only few external components required • No trimming or adjustments ...
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Polarity reversal (programmable soft or hard) • Integrated (balanced) Ringing Generation with zero crossing injection – Programmable frequency between 16.6 and 70 Hz (up to 300 Hz for test) – Programmable amplitude up to 2.125 Vrms (85 Vrms at ...
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Pin Configuration REXT CAP ID-L ID DDA ID-H RES RESERVED I1 O1 Figure 1 Semiconductor Group SLICOFI R 34 PEB ...
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Pin Definition and Functions The following tables group the pins according to their functions. They include pin number, pin name, type, a brief description of the function, and cross-references referring to the sections in which the pin functions are ...
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Table 3 Interface to HV-SLIC (cont’d) Pin No. Name Type LINE LINE 2 Table 4 IO Pins Pin No. Name Type 7 IO1 ...
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Table 6 Pins not Used Pin No. Name 13 RESERVED 37 RESERVED O 14 N.C. 16 N.C. 17 N.C. 18 N.C. Semiconductor Group Type Function Reserved (not connected) Reserved test pin, mustn’t be connected Not connected (not used) Not connected ...
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SLICOFI Principles Five Oversampling AD/DA converters are necessary for data conversion to gain the aspired programmability in the DSP. Generally the SLICOFI can be divided between the AC-Loop which is handling the voice and additionally teletax and the ...
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DSP-machine. The up sampling interpolation steps are again processed by fast hardware structures to reduce the DSP-workload. The upsampled 1-bit data stream is then converted to an analog equivalent which is smoothed by a ...
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Teletax pulses the necessary drop at the line can be calculated and taken into account as well. The outgoing DC-feeding value - superposed with the ...
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SLICOFI Signal Block Diagram R IOM -2 Figure 4 Semiconductor Group Control 15 PEB 3065 PEF 3065 ® SLICOFI Principles HV- Interface ITB10171 01.98 ...
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IOM -2 Interface The IOM-2 interface consists of two data lines and two clock lines. DU (data upstream) carries data from the SLICOFI to a master device. DD (data downstream) carries data from the master device to the ...
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FSC DCL 4096 kHz DD TS0 DU TS0 Detail B Detail B FSC DCL DD/DU Bit n ® Figure 6 IOM -2 Interface Timing (DCL = 4096 kHz, SEL24 = 1, per 8 kHz frame) FSC DCL 2048 kHz DD ...
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IOM -2 Time Slot Assignment An assignment of 8 time slots is possible for each voice-channel. The IOM-2 operating mode and time slot selection is set completely by pin-strapping. Table 7 SEL24 TS2 TS1 ...
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Programming the SLICOFI With the appropriate commands, the SLICOFI can be programmed and verified very flexible via the IOM-2 Interface monitor channel. Data transfer to the SLICOFI starts with a SLICOFI-specific address byte (81 With the second byte one ...
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Transfer configuration registers: 1 Coefficient RAM: ® 5.2 SLICOFI Programming Procedure (DD Data Downstream, DU … SOP– Write Commands Bit Address ...
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TOP – Write Commands no write command possible; reading only. COP – Write Commands Bit Address COP-Write 8 Bytes Coeff Coeff. ...
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Bit Address SOP-Read 8 Bytes TOP – Read Commands Bit Address ...
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COP – Read Commands Bit Address COP-Read 8 Bytes Example for a Mixed Command ...
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Bit Address TOP-Read 1 Byte Semiconductor Group Idle Idle Idle Idle Idle Idle Idle Idle ...
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SOP Command To modify or evaluate the SLICOFI status, the contents configuration registers SCR1, SCR8 may be transferred to (incl. SCR0) from the SLICOFI. This is … done by a SOP-Command ...
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SCR0 Configuration Register 0 Configuration Register SCR0 can be read only. It gives a mirror of the SOP-Command itself to control its contents and represents the reset value as defined below. Bit Reset value: 54 (if ...
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SCR1 Configuration Register 1 Configuration register SCR1 defines the basic feeding modes of the SLICOFI and enables/disables test features: Bit N/BB Reset value SLICOFI is set either in Power Down or Power Denial mode ...
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SCR2 Configuration Register 2 Configuration register SCR2 defines some testmode output results, some special SLMA-mode requirements and the possibility to program 2 I/O-ports. Bit 7 6 MVA OKTON Reset value: 00 (then as measured) H MVA Internal measurement results shown ...
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SCR3 Configuration Register 3 Configuration register SCR3 defines the meterpulse settings and the Data Upstream Persistency Counter. Bit 7 6 TTXNO TTX12 Reset value TTXNO Meterpulses are represented by teletax (TTX) with kHz or with ...
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STCR3 Test Configuration Register 3 Bit SCR3-5 (SOREV PDADIS The automatic HV-SLIC Power Down - Active switching (see chapter 6.4) can be switched off PDADIS = 0 use automatic Power Down-Active switching PDADIS ...
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SCR4 Configuration Register 4 Configuration register SCR4 defines the basic SLICOFI settings which enable / disable the programmable digital filters and the second tone generator. Bit Reset value Set transhybrid Balancing Filter – ...
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SCR5 Configuration Register 5 Configuration register SCR5 defines various different features. Bit 7 6 DHP-R LAW Reset value DHP-R Disable Receive Highpass for test reasons (see chapter 10.3) DHP DHP LAW PCM - law ...
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SCR6 Configuration Register 6 Configuration register SCR6 defines various test features and test loops. Bit 7 6 COT8 COT16 Reset value COT8 Cut Off Transmit Path at 8 kHz for test reasons (Input of Compression) COT8 = 0 ...
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SCR7 Configuration Register 7 Configuration register SCR7 is the Mask register. With it each bit of TCR1 (Signalling register) can be masked; that means changes of such a “masked bit” are not causing a change of the SLCX - bit ...
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SCR8 Configuration Register 8 Configuration register SCR8 defines some Test Mode Settings and the Ground Key/External Indication Data Upstream Persistency Counter. Bit 7 6 DCANAL CHOPACT Reset value DCANAL Test bit to shorten internally the IT with the ...
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TOP Command If no status modification of the SLICOFI is required (there is no TOP-write operation) a transfer operation byte TOP may be transferred. Bit Read Information: Enables reading from the SLICOFI RW = ...
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VB/2 Half battery voltage across the HV-SLIC is detected ( V /2) BIM interrupt masked in Power Denial and Ringing State VB VB ICON Current limitation information interrupt masked in Power Denial and Ringing State ICON ...
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Reset Reg = 0, counter ready, no INT No Chng Yes Yes Mask No set DUP CFAIL Counter No Start Counter diff. betw. No Inp. and Outp. Signaling reg. Reset INT_REQ Read Only TCR1 Yes Yes INT No Transfer Transfer ...
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TCR2 and TCR3 Configuration Registers 2 and 3 TCR2 and TCR3 are the checksum of all the Coefficient bytes written into the Coefficient RAM (CRAM) of the SLICOFI by the COP-Command. TCR2 Bit 7 6 TCR3 Bit 7 6 OKCS ...
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TCR4 to TCR18: Configuration Register These 15 bytes are the possible design information bytes which are described in chapter 10.2 more detailed for the extended I0M-2 Channel Identification Command using an external ASIC. TCR4 Bit 7 6 ...
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COP Command With a COP Command coefficients for the programmable filters can be written to the SLICOFI Coefficient RAM or read from the Coefficient RAM via the IOM-2 interface for verification. (Filter optimizing to different applications is supported by ...
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IOM -2 Interface Command / Indication Byte The Command/Indication (C/I) channel is used to communicate real time status information and for fast controlling of the SLICOFI. Data on the C/I channel is continuously transmitted in each frame until ...
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IO2 Value for the programmable Input/Output Pin IO2 (Pin 8) if programmed as an output pin. IO2 = 0 IO2 = 1 O1 Value for the fixed Output Pin O1 (Pin 39 SLICOFI is set to a ...
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IO2 Logical state of the programmable Input/Output Pin IO2 (Pin 8) - even if not programmed as an input pin. IO2 = 0 IO2 = 1 I1 Logical state of the programmable Input Pin I1 (Pin 38 ...
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Operating Modes The SLICOFI supports 4 different Operating Modes: Power Denial (PDen), Power Down (PDown), Active and Ringing which are controlled via the upper 3 bits of the Data Downstream C/I channel byte (CIDD). Table 9 RiING-(CIDD7) CONV-(CIDD6) TIM-(CIDD5) ...
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PDADIS = 1 or PDADIS = 0 and Onhook Rev. Pol. Meterpulse 010 011 TTXNO = 1 Active 010 011 TTXNO = 0 TTX Burst on Ring, Conv and Tim bits (e.g. Figure 9 Semiconductor Group R HV-SLIC HV-SLIC Pdown ...
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Reset Behavior The SLICOFI has 3 different reset sources that are all internally connected. The Reset pin RES (pin 36), which works totally asynchronous to the external clocks. The Reset bit (Within SOP - command, bit 4). The reset ...
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Table 10 DC Parameter Values Unit Const I 26 RFS 2 150 V 10 drop f 25 Ring ARing 1.7 PDen 1.45 Offhook 8 DC-Lowpass 0.3/5 Levelmeter DUP 10 DUPGNK 20 Boosted Battery is reset to normal feeding Reverse Polarity ...
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Table 11 AC (cont’d) Parameter Values Unit Test Condition/Result f 16 kHz TTX SOREV TG1 1008 Hz TG2 2000 Hz 6.3 Power Denial (PDen) After a Reset (including the Power On Reset) the SLICOFI is set to Power Denial State. ...
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Table 12 CIDD7 RING PDNH - Loop open 0 (Iab < PDNR 0 PDown 0 PDown (with Hi-a) 0 PDown (with Hi-b) 0 b-line high 0 impedance (Ground Start) 6.5 Active Mode (Act) In Active Mode (“Conversation State”) ...
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TTXNO (SCR3-7). If bit TTXNO is set to 1, then the meterpulse is reversal. In this case the Timing bit is linked to POLNR (SOP- EXOR gate. If bit TTXNO ...
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Unbalanced (external) Ringing The sine wave for ringing is generated by an external ring generator. To coordinate with the SLICOFI following settings must be done: 1. IO1 set as an output 2. SCR5-2 (REXTEN RING-(CIDD7 ...
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SLIC Interface 2 Wire Output Voltage ( V The output voltage pin (26) represents the sum for AC- and DC-loop together with 2W Teletax info or Ring Burst at the receive path. The buffer is designed for a load ...
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Table 13 VOL C1 (PIN 9) VOZ VOH BB - Boosted battery RP - Reverse Polarity NP - Normal Polarity HI-b - High Impedance b-leg HI-a - High Impedance a-leg PDNH - Power Denial High Impedance PDNR - Power ...
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Transmission Characteristics The target figures in this specification are based on the subscriber-line board requirements. The proper adjustment of the programmable filters (transhybrid balancing, impedance matching, frequency-response correction) needs a complete knowledge of the SLICOFI’s analog environment. Unless otherwise ...
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Table 14 Parameter Symbol Gain absolute G transmit X receive G R IMAN-Loop G IMAN G TTX-injection TTX Total Harmonic distortion transmit THD T receive THD R Ringing injection THD Rng TTX injection THD TTX Idle channel noise N transmit ...
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Frequency Response Receive: reference frequency 1 kHz, signal level 0 dBm0 1.4 1 0.9 0.65 0.45 0.25 0 -0. 0.2 0.3 Figure 11 Transmit: reference frequency 1 kHz, signal level 0 dBm0 ...
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Group Delay Maximum delays when the SLICOFI is operating with H including delay through A/D- and D/A converters. Specific filter programming may cause additional group delays. Group Delay deviations stay within the limits in the figures below. Group Delay ...
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Out-of-Band Signals at Analog Output (receive) With a 0 dBm0 sine wave with frequency the level of any resulting out-of-band signal at the analog output will stay at least X dB below a 0 dBm0, 1 kHz sine wave ...
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Out-of-Band Signals at Analog Input (transmit) With a 0 dBm0 out-of-band sine wave signal with frequency 100 kHz) applied to the analog input, the level of any resulting frequency component at the digital output will stay at least X ...
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Overload Compression Transmit: measured with sine wave 10 dBm0 0.25 0 -0. Figure 15 Semiconductor Group f = 1004 Hz 3 Fundamental Input Power ...
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Gain Tracking (receive or transmit) The gain deviations stay within the limits in the figures below. Receive: measured with sine wave reference level 1.4 1 0.5 0.25 0 -0.25 -0.5 ...
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Total Distortion The signal to distortion ratio exceeds the limits in the following figure: Receive: measured with sine wave psophometrically weighted for A-law S -60 Figure ...
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S -60 Figure Table 17 Parameter Symbol SD Signal to Distortion att_T at full gain SD Signal to Distortion IMAN in IMAN Loop Semiconductor Group -50 ...
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Transhybrid Loss The quality of Transhybrid-Balancing is very sensitive to deviations in gain and group delay – deviations inherent to the SLICOFI A/D- and D/A-converters as well as to all external components used on a line card (HV-SLIC). Measurement ...
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Electrical Characteristics 9.1 Absolute Maximum Ratings Table 20 Parameter V referred to GNDA DDA V referred to GNDD DDD V referred to GNDA SS GNDA with respect to GNDD V with respect to V DDA DDD V referred to ...
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Operating Range 5%; GNDD = GNDA = Table 21 Parameter Symbol 1) V supply current DD Power Denial IDD Power Down IDD ...
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Digital Interface 5%; GNDD = GNDA = Table 22 Parameter For all input pins (including IO-Pins): Low-input pos.-going Low-input neg.-going Low-input Hysteresis ...
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V OUT Figure 20 Semiconductor Group PEB 3065 PEF 3065 Electrical Characteristics V IN ITD10168 01.98 ...
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DC-Feeding 9.3.1 DC-Feeding ( 5%; GNDD = GNDA = Table 23 Parameter Symbol “Line Current” Measurement: V Transmit IT offset V IT ...
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Table 24 (cont’d) Parameter Symbol “Line Voltage” Feeding: V Receive 2W offset V 2W gain V 2W THD V Receive Boosted 2W offset V 2W gain V 2W THD 9.4 HV-SLIC Interface ...
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Table 25 (cont’d) Parameter Symbol Output voltage: HV-SLIC-Interface Pins 9, 10 (C1, C2) V High level OHHV V Zero level OMHV V Low level OLHV I Current drained OTLo I from pin 9 (C1) OTHi in all 3 states External ...
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Table 26 Switching Characteristics Parameter Period DCL “slow” mode 2) Period DCL “fast” mode DCL Duty Cycle Period FSC FSC set-up time FSC hold time DD data in set-up time DD data in hold time DU data out delay (intrinsic) ...
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IOM -2 Command/Indication Interface Timing (DCL = 4096 kHz) DCL 4 MHz DD Command OUT All Outputs. Last Monitor DD One Frame Later Command OUT All Outputs. High Imp. Command OUT All Outputs. Last Monitor ...
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IOM -2 Command/Indication Interface Timing (DCL = 2048 kHz) DCL 2 MHz DD Command OUT All Outputs. Last Monitor DD One Frame Later Command OUT All Outputs. High Imp. Command OUT All Outputs. Last Monitor ...
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External Masterclock MCLK Figure 24 Table 29 Switching Characteristics Parameter Period MCLK MCLK Duty Cycle Semiconductor Group t MCLK t MCLKh Symbol Limit Values min. t MCLK t 40 MCLKh 76 PEB 3065 PEF 3065 Electrical Characteristics ITT10180 typ. ...
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Appendix ® 10.1 IOM -2 Interface Monitor Transfer Protocol Monitor Channel Operation The monitor channel is used for the transfer of maintenance information between two functional blocks. Using two monitor control bits (MR and MX) per direction, the data ...
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Monitor Handshake Procedure The monitor channel works in 3 states Idle state A pair of inactive (set to ‘1’) MR- and MX-bits during two or more consecutive frames: End of Message (EOM) Sending state MX-bit is activated (set to ‘0’) ...
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Idle RQT 1st Byte RQT nth Byte ACK Wait for ACK Figure 26 State Diagram of the SLICOFI Monitor Transmitter MR ...
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Idle 1st Byte REC Byte Valid New Byte Figure 27 State Diagram of the SLICOFI Monitor Receiver MR MR ...
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Address Byte Messages to and from the SLICOFI are started with the following byte: Bit Thus providing information for only one analog line, the SLICOFI is one device on one IOM-2 time slot. Monitor data for ...
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ASIC Figure 28 Solution 1 (“Normal” Channel Identification Command): The input of the 3 pin interface (ID-H, ID-L, ID-M) is transferred to the 4 bit CONF information using the following truth-table: Table 30 SLICOFI Ports ID-H ID ...
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This possible individual line card design information or an address pointer for the system to get more basic information. The information is read through the IOM-2 monitor channel with the CIC command. Solution 2 (Extended Channel Identification ...
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Detail A FSC DCL ...
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Expected Input of the ASIC (via for example - the SLICOFI has the time slot 6 (TSx = 110, see chapter 4, page 16, too), the ...
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Table 32 (cont’ SCR1-5 SCR2-3 SCR6 Testregister (STCR1 Summary The Testregisters (accessed by the SOP-command with LSEL ...
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To use an external masterclock of 16 MHz following steps must be done: 1) IO1 must be set to input and becomes the input-pin of the masterclock 2) Enable the testregisters (Configuration Register 5: SCR5-1 (ENTR) =1) 3) The testregisterblock ...
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ALB_ADC (Analog loop with ADC and DAC) This testloop feasibles the test of AC analog parts including ADC and DAC. Initializing the testloop: Reset Active Mode Disable Impedance matching filter (OPIMAN (SCR6_5 OPIM4M (SCR6_4 (SCR4_6) ...
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DLB_4M (Digital loop MHz) This testloop feasibles the test of AC digital parts including DSP. Initializing the testloop: Reset Store owns coefficients (generated by SLICOS) Active Mode Select programmed coefficients (FIXC (SCR5_5 Open Impedance matching ...
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DLB_PCM (Digital loop only PCM-interface) This testloop is the basic setting after Reset and the NOT Active Mode. It releases a shortcut between DD and DU. In Active Mode this loop can be programmed. Initializing the testloop: Reset or in ...
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DC_ALB (DC analog loop) This testloop feasibles the test of the analog DC parts (max. frequency of the testsignal 4 kHz). Initializing the testloop: Reset Active Mode Open analog loop (OPIMAN (SCR6_5 ACDACDIS (STCR2_2 Testloop IT ...
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RVP (Ringer voltage present) This testloop feasibles the test of the ringer burst level. Initializing the testloop: Reset Store owns coefficients and voltage level for measurement (generated by SLICOS) Select programmed coefficients (FIXC (SCR5_5 Open analog loop (OPIMAN ...
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TVP (Teletax voltage present) This testloop feasibles the test of the teletax burst level which includes the test of TTX adaptation and basic functions of HV-SLIC. Initializing the testloop: Reset Store owns coefficients and voltage level for measurement (generated by ...
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LC (Loop current measurement) This testloop feasibles a DC test of the line (shortcut, resistance, operating point) and basic function of the HV-SLIC. Initializing the testloop: Reset Store owns coefficients (generated by SLICOS) Select programmed coefficients (FIXC (SCR5_5 ...
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RC (Ringer capacitance measurement) This testloop feasibles the test of the line concerning the ringer. Initializing the testloop: Reset Store owns coefficients (generated by SLICOS) Select programmed coefficients (FIXC (SCR5_5 Open analog loop (OPIMAN (SCR6_5 ACDACDIS ...
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ILT (Longitudinal current measurement) This testloop feasibles the test of the line. Initializing the testloop: Reset Store owns coefficients (generated by SLICOS) Select programmed coefficients (FIXC (SCR5_5 Open analog loop (OPIMAN (SCR6_5 ACDACDIS (STCR2_2 ...
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DC_THRU (DC loop) This testloop feasibles the test of the DC parts. Initializing the testloop: Reset PDown Mode (AC-Loop disactivated) Testloop DCX ITAC AC LOOP V2W DCR Figure 40 Semiconductor Group MEAN RECT VAL. ...
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List of Abbreviations Act Active Mode ADC Analog Digital Converter AGDCR Attenuation DC Receive AGDCX Attenuation DC Transmit AGR Attenuation Receive AGX Attenuation Transmit AGTTX Attenuation Teletax AR Attenuation Receive ASIC Application Specific Integrated Circuit AX Attenuation Transmit BB ...
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DHP_R Disable Receive Highpass (SCR5_7) DHP_X Disable Transmit Highpass (SCR1_1) DSP Digital Signal Processor DU Data Upstream DUP Data Upstream Persistency Counter DUPGNK Data Upstream Persistency Counter for GNK EXP Expander FRR Frequency Response Receive Filter FRX Frequency Response Transmit ...
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LP03 Low Pass 0.3 Hz LP5 Low Pass 5 Hz LSSGR Local Requirements MEAN VAL. Mean Value (Testloops, Levelmetering) MR Monitor Receive MX Monitor Transmit O1 Fixed Output Pin PCM Pulse Code Modulation PDen Power Denial PDN Power Down PDN ...
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TCR Transfer Configuration Register TE 1-3 Test Pin TG Tone Generator TH Transhybrid Balancing THFIX Transhybrid Balancing Filter (fixed) THRESH Threshhold (Testloops, Levelmetering) TOP Transfer Operation TS Time Slot TS 0-2 Time Slot selection Pin TTX Teletax TTXFI Teletax Adaptation ...
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Package Outlines P-LCC-44 (SMD) (Plastic Leaded Chip Carrier) Figure 41 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Semiconductor Group 102 PEB 3065 PEF 3065 ...