M5M4V4265CTP-6 MITSUBISHI, M5M4V4265CTP-6 Datasheet

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M5M4V4265CTP-6

Manufacturer Part Number
M5M4V4265CTP-6
Description
M5M4V4265CTP-6EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Manufacturer
MITSUBISHI
Datasheet

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Part Number:
M5M4V4265CTP-6S
Manufacturer:
FUJI
Quantity:
1 000
Part Number:
M5M4V4265CTP-6S
Manufacturer:
MIT
Quantity:
20 000
1
FEATURES
XX=TP,J
DESCRIPTION
M5M4V4265CJ,TP-5,-5S:under development
This is a family of 262144-word by 16-bit dynamic RAMs with EDO
mode fuction, fabricated with the high performance CMOS
process, and is ideal for the buffer memory systems of personal
computer graphics and HDD where high speed, low power
dissipation, and low costs are essential. The use of double-layer
metalization process technology and a single-transistor dynamic
storage stacked capacitor cell provide high circuit density at
reduced costs. The lower supply (3.3V) operation, due to the
optimization of transistor structure, provides low power dissipation
while maintaining high speed operation. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is low enough for
battery back-up application. This device has 2CAS and 1W
terminals with a refresh cycle of 512 cycles every 8.2ms.
PIN DESCRIPTION
APPLICATION
Microcomputer memory, Refresh memory for CRT, Frame buffer
memory for CRT
Standard 40 pin SOJ, 44 pin TSOP (II)
M5M4V4265CXX-5,-5S
M5M4V4265CXX-6,-6S
M5M4V4265CXX-7,-7S
Single 3.3±0.3V supply
Low stand-by power dissipation
Operating power dissipation
Self refresh capability *
Extended refresh capability
EDO mode (512-column random access), Read-modify-write, RAS-
only refresh, CAS before RAS refresh, Hidden refresh capabilities.
Early-write mode, OE and W to control output buffer impedance
512 refresh cycles every 8.2ms (A
512 refresh cycles every 128ms (A
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M4V4265CJ,TP-5S,-6S,
A
DQ
RAS
LCAS
UCAS
W
OE
V
V
Pin name
0
CC
SS
Type name
~A
CMOS Input level
CMOS Input level
M5M4V4265CXX-5,-5S
M5M4V4265CXX-6,-6S
M5M4V4265CXX-7,-7S
Extended refresh current
Self refresh current
-7S : option) only
1
~DQ
8
16
Lower byte control
column address strobe input
Address inputs
Data inputs / outputs
Row address strobe input
Upper byte control
column address strobe input
Write control input
Output enable input
Power supply (+3.3V)
Ground (0V)
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
(max.ns)
access
RAS
time
50
60
70
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Function
(max.ns)
access
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
CAS
time
13
15
20
0
Address
(max.ns)
0
~A
access
~A
time
25
30
35
8
8
)
) *
(max.ns)
access
time
13
15
20
OE
(min.ns)
Cycle
110
130
time
486mW (Max)
432mW (Max)
396mW (Max)
90
1.8mW (Max)
360µW (Max) *
100µA (Max)
100µA (Max)
(typ.mW)
dissipa-
Power
408
363
333
tion
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
PIN CONFIGURATION (TOP VIEW)
Outline 44P3W-R (400mil TSOP Nomal Bend)
(3.3V)V
(3.3V)V
(3.3V)V
(3.3V)V
(3.3V)V
(3.3V)V
Outline 40P0K (400mil SOJ)
RAS
RAS
DQ4
DQ4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
NC
NC
NC
NC
NC
NC
CC
CC
CC
CC
CC
CC
A
A
A
A
A
A
A
A
W
W
1
2
3
5
6
7
8
0
1
2
3
1
2
3
5
6
7
8
0
1
2
3
13
14
15
16
10
11
12
15
16
17
18
19
20
10
13
14
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
MITSUBISHI LSIs
40
39
38
37
36
35
34
33
32
31
30
27
26
25
24
23
22
21
44
43
42
41
40
39
38
37
36
35
32
29
28
27
26
25
24
23
29
28
31
30
MITSUBISHI LSIs
NC : NO CONNECTION
V
DQ
DQ
DQ
DQ
V
DQ
DQ
DQ
DQ
NC
LCAS
UCAS
OE
A
A
A
A
A
V
V
DQ
DQ
DQ
DQ
V
DQ
DQ
DQ
DQ
NC
LCAS
UCAS
OE
A
A
A
A
A
V
S
SS
8
7
6
5
4
SS
S
SS
8
7
6
5
4
SS
S(0V)
S(0V)
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
(0V)
(0V)
(0V)
(0V)

Related parts for M5M4V4265CTP-6

M5M4V4265CTP-6 Summary of contents

Page 1

... MITSUBISHI LSIs MITSUBISHI LSIs (3.3V DQ4 5 36 (3.3V ...

Page 2

... DNC DNC DNC DNC CLOCK GENERATOR CIRCUIT COLUMN DECODER SENSE REFRESH AMPLIFIER & CONTROL MEMORY CELL ROW (4,194,304 BITS) DECODER A 8 MITSUBISHI LSIs Input/Output DQ ~ OUT OPN D OUT D IN DNC D IN OPN D OUT OPN OPN ...

Page 3

... 0.8 V (Note 2) Limits Typ Min 2 OUT output open IH -0. -0.2V CC -0.2V CC -0.2V CC -0.2V CC -0.2V ~1µs RAS min MITSUBISHI LSIs Unit ˚C ˚C Unit Max 0.4 V µA 5 µA 5 135 mA 120 110 2 mA 0.5 0.1 * 125 mA 110 95 125 mA 110 95 115 ...

Page 4

... The reference levels for measuring of output signals are OUT MITSUBISHI LSIs Unit Max Unit Max ...

Page 5

... MITSUBISHI LSIs Unit Max 8 128 access time is RCD(max CAC Unit ...

Page 6

... DQ pins WCS WCS(min and RWD RWD(min) AWD AWD(min) CPWD ) is indeterminate. IH MITSUBISHI LSIs Unit Max ns ns 10000 ns 10000 Unit Max ns ns 10000 ns 10000 ns ns ...

Page 7

... Parameter M5M4V4265C-5,-5S Min 10 17 Parameter M5M4V4265C-5,-5S Min 100 90 -50 MITSUBISHI LSIs Limits M5M4V4265C-6,-6S M5M4V4265C-7,-7S Max Min Max Min 100000 77 100000 100000 ...

Page 8

... Indicates the invalid output RPC t CSH t RSH t CAS t RAL t CAL Hi CAC REZ t OHR t OEA DATA VALID t OEA t OCH t ORH IH(max) IL(min) IN IL(max) MITSUBISHI LSIs CRP t ASR ROW ADDRESS t RRH t RCH t CDD t WEZ t OFF t OHC Hi-Z t OEZ t ODD ...

Page 9

... M5M4V4265CJ,TP-5,-5S:under development M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S t RAS t CSH t RCD t RAD t RAH t t ASC CAH ROW COLUMN ADDRESS t RCS t DZC t CAC CLZ Hi-Z t RAC t DZO MITSUBISHI LSIs RPC t RSH t CAS t RAL t CAL t RRH Hi-Z Hi-Z t REZ t OHR DATA VALID t OEA t OCH t ORH CRP t CPN ...

Page 10

... ~ (OUTPUTS M5M4V4265CJ,TP-5,-5S:under development M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S t RAS t CSH t RCD t t RAH CAH t ASC ROW COLUMN ADDRESS t WCS DATA VALID RPC t RSH t CAS WCH Hi-Z MITSUBISHI LSIs CRP t ASR ROW ADDRESS ...

Page 11

... V OH ( (OUTPUTS M5M4V4265CJ,TP-5,-5S:under development M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S t RAS t CSH t RCD t t RAH CAH t ASC COLUMN ROW ADDRESS t WCS t Hi DATA VALID RPC t RSH t CAS WCH Hi-Z MITSUBISHI LSIs CRP t ASR ROW ADDRESS ...

Page 12

... M5M4V4265CJ,TP-5,-5S:under development M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S t CSH t RCD CRP t RAH t ASC ROW COLUMN ADDRESS ADDRESS t RCS t DZC Hi-Z t CLZ Hi-Z t DZO RAS t RSH t CAS t CAH t CWL t RWL WCH DATA VALID Hi-Z t OEH t OEZ t ODD MITSUBISHI LSIs RPC t CRP t ASR ROW ADDRESS ...

Page 13

... IL 13 M5M4V4265CJ,TP-5,-5S:under development M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S t CSH t RCD t RAH t ASC ROW COLUMN ADDRESS ADDRESS t RCS Hi-Z t DZC Hi-Z t CLZ Hi-Z t DZO RAS t RPC t RSH t CAS t CAH t CWL t RWL WCH DATA VALID Hi-Z t OEH t OEZ t ODD MITSUBISHI LSIs CRP t ASR ROW ADDRESS ...

Page 14

... CAH t ASC COLUMN ROW ADDRESS ADDRESS t AWD t CWD t RCS t RWD t DZC Hi-Z t CAC CLZ Hi-Z VALID t RAC t t OEA DZO t RWC t RSH t CAS t CWL t RWL DATA VALID Hi-Z DATA t ODD t OEH t OEZ MITSUBISHI LSIs RPC t CRP t ASR ROW ADDRESS ...

Page 15

... CAH t ASC ROW COLUMN ADDRESS ADDRESS t AWD t CWD t RCS t RWD Hi-Z t DZC Hi-Z t CAC CLZ Hi-Z DATA VALID t RAC t t DZO OEA MITSUBISHI LSIs t RWC RPC t RSH t CAS t CWL t RWL DATA VALID Hi-Z t ODD t OEH t OEZ t CRP t ASR ROW ADDRESS ...

Page 16

... ASC CAH CAH COLUMN-3 COLUMN-2 t RAL t t CAL CAL Hi CAC CAC DOH DOH DATA VALID CPA CPA MITSUBISHI LSIs ASR ROW ADDRESS t RRH t RCH t WEZ t RDD t CDD t REZ t OHR t OFF t OHC DATA VALID-3 t OEZ t ODD ...

Page 17

... ASC t CAH CAH COLUMN-3 COLUMN-2 t RAL t t CAL CAL Hi-Z t CAC t AA DATA VALID-2 t CLZ t CPA Hi-Z t CAC DOH DATA VALID-1 t CPA MITSUBISHI LSIs CRP t ASR ROW ADDRESS t RRH t RCH t REZ t OHR t RDD t CDD t WEZ t OFF t OHC DATA VALID-3 t OEZ t ODD ...

Page 18

... WCS WCH DATA VALID-1 RAS t t HPC RSH CAS CAS t t CAL CAL ASC CAH CAH COLUMN-3 COLUMN WCH WCH WCS DATA DATA VALID-2 VALID-3 Hi-Z MITSUBISHI LSIs CRP t ASR ROW ADDRESS ...

Page 19

... WCS WCH DATA VALID RAS t t HPC RSH CAS CAS CAL CAL t t CAH CAH t ASC COLUMN-2 COLUMN WCH WCS WCH DATA VALID-3 Hi DATA VALID-2 Hi-Z MITSUBISHI LSIs CRP t ASR ROW ADDRESS ...

Page 20

... CAH CWL ASC COLUMN-2 t AWD t CWL t CWD t RCS CPWD DZC Hi-Z DATA VALID-1 VALID-2 t CAC CLZ Hi-Z DATA VALID-2 t CPA t ODD t t DZO t OEZ t OEA MITSUBISHI LSIs RWL t CRP t ASR ROW ADDRESS DATA Hi-Z OEH ...

Page 21

... CWL t t CWD RCS t RWD t t DZC DS Hi-Z DATA VALID-1 t CAC CLZ Hi-Z DATA VALID-1 t RAC t ODD t t OEA DZO t OEZ MITSUBISHI LSIs t RWL t HPRWC t t CAS CAH CWL ASC COLUMN-2 t AWD t CWD t RCS CPWD Hi ...

Page 22

... ASC t CAH CAH COLUMN-3 t CPWD t WCH t AWD t t CAL CWD t t DZC DATA DATA VALID-2 VALID CAC t CLZ DATA VALID-3 t CPA OEA OEZ DZO t ODD MITSUBISHI LSIs RWL t CRP t CWL t ASR ROW ADDRESS OEH ...

Page 23

... CAL RCH t WCS t HCWD t HAWD t t HPWD DS Hi-Z t CAC CPA WEZ DATA VALID-1 t HCOD t OEZ t HAOD t t HPOD MITSUBISHI LSIs t CAS t t CAH ASC COLUMN-2 COLUMN-3 t CAL t WCH DZC DATA VALID CPA t CLZ Hi-Z t DZC ODD t CAH Hi-Z t CAC ...

Page 24

... CAH CAH COLUMN-2 COLUMN-3 t RAL Hi CAC CAC DOH t CLZ Hi-Z DATA DATA VALID-1 VALID-2 t CPA t CPA t CHOL t OEZ t OEPE MITSUBISHI LSIs CRP t ASR ROW ADDRESS t RRH t RCH t WEZ t RDD t CDD t REZ t OHR t OFF t OHC DATA VALID-3 t OEZ t ODD ...

Page 25

... CAH COLUMN-2 COLUMN-3 t RAL t RCH t RCS t WPE Hi CAC CAC DOH WEZ t CLZ Hi-Z DATA VALID CPA CPA MITSUBISHI LSIs CRP t ASR ROW ADDRESS t RRH t RCH t WEZ t RDD t CDD t REZ t OHR t OFF t OHC DATA VALID-3 t OEZ t ODD ...

Page 26

... V IH LCAS/UCAS ASR ADDRESS ~ (INPUTS ~ (OUTPUTS M5M4V4265CJ,TP-5,-5S:under development M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S t RAS t RAH ROW Hi-Z MITSUBISHI LSIs RPC t t CRP ASR ROW ADDRESS ...

Page 27

... REZ t OHR t OFF t OHC (OUTPUTS OEZ M5M4V4265CJ,TP-5,-5S:under development M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,- RAS t RPC t CSR t CHR RAS CSR t RPC CHR Hi-Z MITSUBISHI LSIs t CRP t ASR ROW COLUMN ADDRESS ADDRESS t RCS ...

Page 28

... COLUMN ADDRESS t RCS t RAL t DZC t CAC CLZ Hi-Z t RAC t t DZO OEA t ORH Timing requirements and output state are the same as that of each cycle shown above. MITSUBISHI LSIs RAS t CHR t RRH Hi-Z DATA VALID ASR ROW ADDRESS t CDD t RDD t ...

Page 29

... RCH RDD t CDD V DQ ~ (INPUTS REZ t OHR t OFF t OHC ~ (OUTPUTS OEZ t ODD M5M4V4265CJ,TP-5,-5S:under development M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S t RASS t CSR MITSUBISHI LSIs t RPS t RPC t CRP t CHS t ASR ROW ADDRESS Hi-Z t RCS ...

Page 30

... Switching from self refresh operation to read/write operation. The time interval t end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within 16µs. MITSUBISHI LSIs Read / Write Cycle t SND first refresh cycle ...

Page 31

... Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period should be set within t MITSUBISHI LSIs Read / Write t SNB refresh cycles ...

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