MAX3945ETE+ Maxim Integrated Products, MAX3945ETE+ Datasheet

no-image

MAX3945ETE+

Manufacturer Part Number
MAX3945ETE+
Description
IC AMP LIMITING 3.3V LP 16TQFN
Manufacturer
Maxim Integrated Products
Type
Limiting Amplifierr
Datasheet

Specifications of MAX3945ETE+

Applications
Optical Networks
Mounting Type
Surface Mount
Package / Case
16-WQFN Exposed Pad, 16-DQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
19-5144; Rev 0; 2/10
The MAX3945 is a +3.3V, multirate, low-power limiting
amplifier optimized for Fibre Channel and Ethernet trans-
mission systems at data rates up to 11.3Gbps. The high-
sensitivity limiting amplifier limits the signal generated by
a transimpedance amplifier into a CML-level differential
output signal. All differential inputs and outputs (I/O) are
optimally back terminated for 50I transmission line PCB
design. The MAX3945’s dual-path limiting amplifier has
programmable filtering to optimize sensitivity for differ-
ent data rates and to suppress relaxation oscillations
that could occur in some optical systems. The MAX3945
incorporates two loss-of-signal (LOS) circuits and a pro-
grammable time mask for the LOS output.
A 3-wire digital interface reduces the pin count and
enables control of LOS threshold, LOS polarity, LOS
mode, CML output level, input offset correction, receive
(Rx) polarity, Rx input filter, and Rx deemphasis without
the need for external components.
The MAX3945 is packaged in a 3mm x 3mm, 16-pin
TQFN package.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Typical Application Circuit appears at end of data sheet.
MAX3945ETE+
PART
1x/2x/4x/8x SFF/SFP/SFP+ MSA Fibre-Channel
Optical Transceiver
10GBASE-SR/LR SFP+ Optical Transceiver
10G PON ONU
_______________________________________________________________ Maxim Integrated Products 1
-40NC to +85NC
TEMP RANGE
Ordering Information
General Description
SFP+ Dual-Path Limiting Amplifier
Applications
PIN-PACKAGE
16 TQFN-EP*
1.0625Gbps to 11.3Gbps,
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
130mW Power Dissipation Enables < 1W SFP+
Modules
Enables Single-Module Design Compliance
with 1000BASE-SX/LX and 10GBASE-SR/LR
Specifications
-25.3dBm Optical Sensitivity at 1.25Gbps Using a
10.32Gbps ROSA
Selectable 1GHz/2.1GHz/2.5GHz/3GHz Input Filters
at RATE_SEL = 0 Setting
Supports SFF-8431 SFP+ MSA and SFF-8472
Digital Diagnostic
Total Power Dissipation of 130mW at 3.3V Power
Supply with RSSI Monitor-Based LOS
Total Power Dissipation of 154mW at 3.3V Power
Supply with Rx Input-Based LOS
4mV
4ps
4ps
5ps
BW1 = 1, BW0 = 1
9.0ps
BW1 = 0, BW0 = 0
26ps Rise and Fall Time with RATE_SEL = 1
52ps Rise and Fall Time with RATE_SEL = 0
CML Output with Level Adjustment and Squelch
Mode
Programmable CML Output Deemphasis
CML Output Polarity Select
LOS Polarity Select
Programmable Masking Time for the LOS Output
LOS Assert/Deassert Level Adjustment
Choice of Rx Input-Based LOS or RSSI Monitor-
Based LOS
3-Wire Digital Interface Compatible with Maxim’s
SFP+ Family of Products
P-P
P-P
P-P
P-P
P-P
DJ at 11.3Gbps with RATE_SEL = 1
DJ at 8.5Gbps with RATE_SEL = 1
DJ at 4.25Gbps with RATE_SEL = 0,
Input Sensitivity at 11.3Gbps
DJ at 1.25Gbps with RATE_SEL = 0,
Features

Related parts for MAX3945ETE+

MAX3945ETE+ Summary of contents

Page 1

... Optical Transceiver 10GBASE-SR/LR SFP+ Optical Transceiver 10G PON ONU Ordering Information PART TEMP RANGE MAX3945ETE+ -40NC to +85NC +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Typical Application Circuit appears at end of data sheet. _______________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’ ...

Page 2

SFP+ Dual-Path Limiting Amplifier ABSOLUTE MAXIMUM RATINGS V .......................................................................-0.3V to +4.0V CC Voltage Range at SDA, SCL, CSEL, LOS, CAZ, RPMIN ................................. -0. Voltage Range at ROUT+, ROUT- ........(V Voltage Range at RIN+, RIN- ........ ...

Page 3

SFP+ Dual-Path Limiting Amplifier ELECTRICAL CHARACTERISTICS (continued 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100I load are set to default values, unless otherwise noted. Typical values are at V PARAMETER SYMBOL External RPMIN ...

Page 4

SFP+ Dual-Path Limiting Amplifier ELECTRICAL CHARACTERISTICS (continued 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100I load are set to default values, unless otherwise noted. Typical values are at V PARAMETER ...

Page 5

SFP+ Dual-Path Limiting Amplifier ELECTRICAL CHARACTERISTICS (continued 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100I load are set to default values, unless otherwise noted. Typical values are at V PARAMETER SYMBOL OUTPUT LEVEL ...

Page 6

SFP+ Dual-Path Limiting Amplifier ELECTRICAL CHARACTERISTICS (continued 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100I load are set to default values, unless otherwise noted. Typical values are at V PARAMETER ...

Page 7

T = +25NC, unless otherwise noted. Registers are set to default values, unless otherwise noted, and the 3-wire interface static during measurements.) RECEIVE OUTPUT FROM OPTICAL SYSTEM, 10.32Gbps, OPTICAL INPUT -10dBm, RXDE1 = 1, ...

Page 8

SFP+ Dual-Path Limiting Amplifier (V = 3.3V +25NC, unless otherwise noted. Registers are set to default values, unless otherwise noted, and the 3-wire interface static during measurements.) DIFFERENTIAL OUTPUT SIGNAL LEVEL vs. ...

Page 9

SFP+ Dual-Path Limiting Amplifier (V = 3.3V +25NC, unless otherwise noted. Registers are set to default values, unless otherwise noted, and the 3-wire interface static during measurements.) INPUT RETURN GAIN (SDD11) (INPUT POWER OF 0dBm, ...

Page 10

SFP+ Dual-Path Limiting Amplifier PIN NAME Offset-Correction Loop Capacitor. A capacitor connected between this pin and the adjacent V 1 CAZ the time constant of the offset-correction loop. The offset correction can be disabled through the digital ...

Page 11

SFP+ Dual-Path Limiting Amplifier Detailed Description The MAX3945 is designed to operate from 1.0625Gbps to 11.3Gbps. It consists of a dual-path limiter, offset- correction circuitry, CML output stage, and LOS circuitry. The characteristics of the MAX3945 can be controlled through ...

Page 12

SFP+ Dual-Path Limiting Amplifier V CCR RIN+ 50 Ω CCR 50 Ω RIN- V EER LOS 376 Ω CLAMP V EET V CCR 2kΩ RPMIN Figure 1. Simplified Input/Output Structures 12 _____________________________________________________________________________________ V CCR ...

Page 13

SFP+ Dual-Path Limiting Amplifier V MAX3945 CCR RIN+ RIN- RPMIN V CCR R PULL SDA SCL CSEL R R PULL PULL Figure 2. Functional Diagram CML Output Deemphasis The CML output stage is ...

Page 14

SFP+ Dual-Path Limiting Amplifier Table 5. Output Signal Deemphasis Control RXCTRL2[1] RXCTRL1[7:6] RXDE_EN RXDE1 Table 6. CML Output Amplitude Range (Typical) RXCTRL1[1] RXCTRL2[1] RATE_SEL RXDE_EN 0 X ...

Page 15

SFP+ Dual-Path Limiting Amplifier Table 8. LOS Control LOS2_EN LOS1_EN 50mV/div 2mV/div 400µs/div Figure 3. LOS Response to a Short Burst of Input Signal 50mV/div 2mV/div 400µs/div Figure 4. LOS Response to a Short ...

Page 16

SFP+ Dual-Path Limiting Amplifier Table 9. Digital Communication Word Structure Register Address Table 10. Register Descriptions and Addresses ADDRESS H0x00 H0x01 H0x02 H0x03 H0x04 H0x0E MODECTRL H0x12 SET_LOSTIMER 3-Wire Digital Communication The ...

Page 17

SFP+ Dual-Path Limiting Amplifier WRITE MODE CSEL SCL SDA READ MODE CSEL SCL SDA A6 ...

Page 18

SFP+ Dual-Path Limiting Amplifier Bit # 7 6 Name LOS2_EN LOS1_EN Default Value 0 1 Bit 7: LOS2_EN. Enables or disables the RSSI monitor-based LOS circuitry, in combination with the LOS1_EN bit. The below table shows when ...

Page 19

SFP+ Dual-Path Limiting Amplifier Bit # 7 6 Name X X Default Value X X Bit 1: POR_2d. When the V supply voltage is below 2.3V, the POR circuitry sets POR_2d high. When the supply CC voltage is above 2.75V, ...

Page 20

SFP+ Dual-Path Limiting Amplifier Bit # 7 6 MODECTRL[7] Name MODECTRL[6] (MSB) Default 0 0 Value Bits MODECTRL[7:0]. The MODECTRL register enables a switch between normal and setup modes. The setup mode is achieved ...

Page 21

SFP+ Dual-Path Limiting Amplifier Table 12. Register Map (continued) REGISTER REGISTER NORMAL FUNCTION/ NAME MODE ADDRESS Receiver Control Register 2 RXCTRL2 Address = H0x01 Receiver Status Register RXSTAT Address = H0x02 ______________________________________________________________________________________ 1.0625Gbps to 11.3Gbps, SETUP BIT NUMBER/ MODE TYPE ...

Page 22

SFP+ Dual-Path Limiting Amplifier Table 12. Register Map (continued) REGISTER REGISTER NORMAL FUNCTION/ NAME MODE ADDRESS CML Output Level Setting SET_CML Register Address = H0x03 LOS Threshold Assert Level Setting SET_LOS Register Address = H0x04 General Control ...

Page 23

SFP+ Dual-Path Limiting Amplifier Design Procedure Programming CML Output Levels See Tables 13 and 14. For each value of the bits RXDE1 and RXDE0 in Table 13, the value of deempha- sis does vary with the SET_CML[7:0] setting. In Table ...

Page 24

... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 24 2010 Maxim Integrated Products © ...

Related keywords