MAX3945ETE+ Maxim Integrated Products, MAX3945ETE+ Datasheet - Page 13

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MAX3945ETE+

Manufacturer Part Number
MAX3945ETE+
Description
IC AMP LIMITING 3.3V LP 16TQFN
Manufacturer
Maxim Integrated Products
Type
Limiting Amplifierr
Datasheet

Specifications of MAX3945ETE+

Applications
Optical Networks
Mounting Type
Surface Mount
Package / Case
16-WQFN Exposed Pad, 16-DQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The CML output stage is optimized for differential 100I
transmission lines on a standard FR4 board. The RXDE1
and RXDE0 bits add programmable analog output
deemphasis to compensate for FR4 board losses and
SFP connector losses. Table 5 describes the deempha-
sis control settings.
Figure 2. Functional Diagram
RPMIN
CSEL
V
RIN+
RIN-
SDA
SCL
CCR
R
IN
V
______________________________________________________________________________________
CCR
R
R
- 1V
PULL
PULL
R
IN
MAX3945
R
PULL
CML Output Deemphasis
SFP+ Dual-Path Limiting Amplifier
V
CCR
INTERFACE
3-WIRE
BW1
LPF
BW0
DIGITAL OFFSET CORRECTION
4G
10G
INTERNAL
REGISTER
RATE_SEL
0 MX
1
CAZ
1.0625Gbps to 11.3Gbps,
LOS_POL
V
1
0
The 8-bit SET_CML register controls the amplitude of the
CML output stage. The maximum programmable output
level depends on the operational mode of the MAX3945.
These output levels (which assume an ideal 100I dif-
ferential load) and their corresponding control bits are
described in Table 6. Table 7 shows the output DAC
resolution dependency.
EE
LOSS OF SIGNAL
CONTROL
AZ_EN
LOGIC
RX_POL
LOS2/1_EN
RX_EN
SQ_EN
Programmable CML Output Amplitude
6b DAC SET_LOS
7b DAC SET_LOSTIMER
RXDE1
RXDE0
CTRL LOGIC
8b DAC SET_CML
OUTPUT
R
OUT
DEEMPHASIS
V
CCR
R
OUT
ROUT+
ROUT-
LOS
13

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