MPC9315 Motorola, MPC9315 Datasheet

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MPC9315

Manufacturer Part Number
MPC9315
Description
Manufacturer
Motorola
Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
2.5V and 3.3V CMOS PLL
Clock Generator and Driver
generator designed for low-skew clock distribution in low-voltage
mid-range to high-performance telecom, networking and computing
applications. The MPC9315 offers 8 low-skew outputs and 2 selectable
inputs for clock redundancy. The outputs are configurable and support
1:1, 2:1, 4:1, 1:2 and 1:4 output to input frequency ratios. In addition, a
selectable output 180
schemes with inverted clock signals. The MPC9315 is specified for the
extended temperature range of –40 to +85 C.
Features
Functional Description
requires a connection of one of the device outputs to the selected feedback (FB0 or FB1) input to close the PLL feedback path.
The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected
to match the VCO frequency range. With available output dividers of divide-by-1, divide-by-2 and divide-by-4 the internal VCO of
the MPC9315 is running at either 1x, 2x or 4x of the reference clock frequency. The frequency of the QA, QB, QC output groups is
either the equal, one half or one fourth of the selected VCO frequency and can be configured for each output bank using the
FSELA, FSELB and FSELC pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and 1:4. The
REF_SEL pin selects one of the two available LVCMOS compatible reference input (CLK0 and CLK1) supporting clock
redundant applications. The selectable feedback input pin allows the user to select different feedback configurations and input to
output frequency ratios. The MPC9315 also provides a static test mode when the PLL supply pin (V CCA ) is pulled to logic low
state (GND). In test mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test
mode is intended for system diagnostics, test and debug purpose. This test mode is fully static and the minimum clock frequency
specification does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting
OE causes the PLL to lose lock due to no feedback signal presence at FB0 or FB1. Asserting OE will enable the outputs and
close the phase locked loop, also enabling the PLL to recover to normal operation. The MPC9315 is fully 2.5V and 3.3V
compatible and requires no external loop filter components. All inputs accept LVCMOS signals while the outputs provide
LVCMOS compatible levels with the capability to drive terminated 50
lines, each of the MPC9315 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is
packaged in a 7x7 mm 2 32-lead LQFP package.
zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between
the outputs and the reference signal.
Configurable 8 outputs LVCMOS PLL clock generator
Compatible to various microprocessor such as PowerQuicc I and II
Wide range output clock frequency of 18.75 to 160 MHz
2.5V and 3.3V CMOS compatible
Designed for mid-range to high-performance telecom, networking and
computer applications
Fully integrated PLL supports spread spectrum clocking
Supports applications requiring clock redundancy
Max. output skew of 120 ps (80 ps within one bank)
Selectable output configurations (1:1, 2:1, 4:1, 1:2, 1:4 frequency ratios)
2 selectable LVCMOS clock inputs
External PLL feedback path and selectable feedback configuration
Tristable outputs
32 ld LQFP package
Ambient operating temperature range of –40 to +85 C
The MPC9315 is a 2.5V and 3.3V compatible, PLL based clock
The MPC9315 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation
The fully integrated PLL of the MPC9315 allows the low skew outputs to lock onto a clock input and distribute it with essentially
Motorola, Inc. 2002
phase control supports advanced clocking
1
transmission lines. For series terminated transmission
CLOCK GENERATOR
2.5V AND 3.3V PLL
MPC9315
LOW VOLTAGE
LQFP PACKAGE
CASE 873A–02
FA SUFFIX
Order Number: MPC9315/D
Rev 2, 02/2002

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MPC9315 Summary of contents

Page 1

... VCO frequency range. With available output dividers of divide-by-1, divide-by-2 and divide-by-4 the internal VCO of the MPC9315 is running at either 1x the reference clock frequency. The frequency of the QA, QB, QC output groups is either the equal, one half or one fourth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB and FSELC pins, respectively ...

Page 2

... FB0 0 (pulldown) FB1 1 (pulldown) FB_SEL (pulldown) FSELA (pulldown) PSELA (pullup) FSELB (pullup) FSELC (pulldown) OE The MPC9315 requires an external RC filter for the analog power supply pin VCCA. Please see application section for details. 25 GND 26 QA1 27 QA0 28 VCC 29 FSELC 30 FSELB 31 FSELA 32 GND Figure 2. Pinout: 32–Lead Package Pinout (Top View) ...

Page 3

... QC0, QC1 = VCO clock frequency 180 (QA0, QA1 inverted) VCCA = 3.3 or 2.5V, PLL enabled Reset (VCO clamped to min. range) Outputs disabled (tristate), open PLL loop Min -0.3 -0.3 -0.3 -55 Min Typ 200 2000 200 10 4.0 3 MPC9315 Function Max Unit Condition 125 C ...

Page 4

... I CCQ Maximum Quiescent Supply Current a. The MPC9315 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage Alternatively, the device drives up to two 50 series terminated transmission lines. b. Inputs have pull–up or pull–down resistors affecting the input current. ...

Page 5

... AC characteristics apply for parallel output termination I/O jitter depends on VCO frequency. Please see application section for I/O jitter versus VCO frequency characteristics feedback is not available for 2.5V operation. Please see next revision of the MPC9315 for the 1 feedback option at 2.5V supply. TIMING SOLUTIONS 5 – ...

Page 6

... Table 1, Table 2 and Table 3 illustrate the various output configurations and frequency ratios supported by the MPC9315. PSELA controls the output phase of the QA0 and QA1 outputs, allowing the user to generate inverted clock signals synchronous to non-inverted clock signals. See also “ ...

Page 7

... FB1 QB2 FBSEL QB3 FSELA QC0 FSELB QC1 FSELC PSELA MPC9315 80 MHz (Feedback) MPC9315 default configuration (feedback of QB3 = 100 MHz). All control pins are left open. Frequency range Min Input 37.50 MHz QA outputs 75.00 MHz QB outputs 37.50 MHz QC outputs 18.75 MHz Figure 5. MPC9315 180 Phase Inversion Configuration ...

Page 8

... Above equation uses the maximum I/O jitter number shown in the AC characteristic table for V CC =3.3V (10 ps RMS). I/O jitter is frequency dependant with a maximum at the lowest VCO frequency (160 MHz for the MPC9315). Applications using a higher VCO frequency exhibit less I/O jitter than the AC characteristic limit. The I/O jitter characteristics in Figure 8 ...

Page 9

... Line Termination Waveforms” show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9315 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs ...

Page 10

... Figure 12. Single versus Dual Waveforms Pulse Generator Figure 14. CLK0, CLK1 MPC9315 AC test reference MOTOROLA Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 13. “ ...

Page 11

... Figure 17. Output–to–output Skew t SK( The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 19. Period Jitter t F Figure 21. Output Transition Time Test Reference 11 MPC9315 GND ...

Page 12

... MPC9315 –T– DETAIL –Z– –AB– SEATING –AC– PLANE 0.10 (0.004 DETAIL AD MOTOROLA OUTLINE DIMENSIONS FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A 4X 0.20 (0.008) AB T– –U– ...

Page 13

... TIMING SOLUTIONS NOTES 13 MPC9315 MOTOROLA ...

Page 14

... MPC9315 MOTOROLA NOTES 14 TIMING SOLUTIONS ...

Page 15

... TIMING SOLUTIONS NOTES 15 MPC9315 MOTOROLA ...

Page 16

... JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334 Technical Information Center: 1–800–521–6274 HOME PAGE: http://www.motorola.com/semiconductors/ MOTOROLA 16 MPC9315/D TIMING SOLUTIONS ...

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