M5M5W816WG-70HI MITSUBISHI, M5M5W816WG-70HI Datasheet
M5M5W816WG-70HI
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M5M5W816WG-70HI Summary of contents
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... The M5M5W816 is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv es. M5M5W816WG is packaged in a CSP (chip scale package), with the outline of 7.5mm x 8.5mm, ball matrix (48ball) and ball pitch of 0.75mm. ...
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... Ver. 3.1 M5M5W816WG - 70HI, 85HI FUNCTION The M5M5W816WG is organized as 524288-words by 16-bit. These dev ices operate on a single +2.7~3.0V power supply , and are directly TTL compatible to both input and output. Its f ully static circuit needs no clocks and no ref resh, and makes it usef ul. ...
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... Ver. 3.1 M5M5W816WG - 70HI, 85HI ABSOLUTE MAXIMUM RATINGS Symbol Parameter V cc Supply v oltage V Input v oltage I V Output v oltage O P Power dissipation d Operating T a temperature T Storage temperature stg DC ELECTRICAL CHARACTERISTICS Symbol Parameter V High-lev el input v oltage IH Low-lev el input v oltage High-lev el output v oltage ...
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... Ver. 3.1 M5M5W816WG - 70HI, 85HI AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS Supply v oltage Input pulse Input rise time and f all time Ref erence lev el Output loads (2) READ CYCLE Symbol t Read cy cle time CR t Address access time ( Chip select 1 access time (S1 (S2) ...
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... Ver. 3.1 M5M5W816WG - 70HI, 85HI (4)TIMING DIAGRAMS Read cycle A 0~18 BC1#,BC2# (Note3) S1# (Note3) S2 (Note3) OE# (Note3 "H" lev el DQ 1~16 Write cycle ( W# control mode ) A 0~18 BC1#,BC2# (Note3) S1# (Note3) S2 (Note3) OE 1~16 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM ( (BC1) t (BC2 ...
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... Ver. 3.1 M5M5W816WG - 70HI, 85HI Write cycle (BC# control mode) A 0~18 BC1#,BC2# S1# (Note3) S2 (Note3) (Note5) W# (Note3) DQ 1~16 Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during S1# low, S2 high overlaps BC1# and/or BC2# low and W# low. Note 5: When the falling edge simultaneously or prior to the falling edge of BC1# and/or BC2# or the falling edge of S1# or rising edge of S2, the outputs are maintained in the high impedance state ...
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... Ver. 3.1 M5M5W816WG - 70HI, 85HI Write cycle (S1# control mode) A 0~18 BC1#,BC2# (Note3) S1# S2 (Note3) W# (Note3) DQ 1~16 Write cycle (S2 control mode) A 0~18 BC1#,BC2# (Note3) S1# S2 (Note3) W# (Note3) DQ 1~16 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM (S1 (A) su (Note5) (Note4) t (D) su DATA IN STABLE t CW ...
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... Ver. 3.1 M5M5W816WG - 70HI, 85HI POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Parameter Vcc Power down supply voltage (PD (BC#) Byte control input BC1# & BC2# V Chip select input S1# I (S1#) V Chip select input S2 I (S2) Power down Icc (PD) supply c urrent (2) TIMING REQUIREMENTS ...
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... All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein ...
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... MITSUBISHI ELECTRIC 48FBGA for 8MSRAM 7.5 TYP (7. 1.2MAX 0.35±0. 0.2 Code: Date: 15th.Dec.2000 0.75 x 5=3.75 0.75(TYP 48-ø0.45±0.05 ø0.08 M Page ...