PEB20256E Infineon Technologies AG, PEB20256E Datasheet
PEB20256E
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PEB20256E Summary of contents
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ICs for Communications Multichannel Network Interface Controller for HDLC/PPP with 256 Channels MUNICH256 PEB 20256 E Version 2.1 PEF 20256 E Version 2.1 Preliminary Data Sheet 08.99 DS1 ...
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... Components used in life-support devices or systems must be expressly authorized for such purpose! 1 Critical components of the Infineon Technologies AG, may only be used in life-support devices or systems the express written approval of the Infineon Technologies AG critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system affect its safety or effectiveness of that device or system ...
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Preface The Multichannel Network Interface Controller for HDLC is a Multichannel Protocol Controller for a wide area of telecommunication and and data communication applications. Organization of this Document This Preliminary Data Sheet is divided into ten chapters organized ...
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Preliminary Data Sheet 4 PEB 20256 E PEF 20256 E 08.99 ...
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Table of Contents 1 MUNICH256 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Bit Synchronous PPP with HDLC Framing Structure . . . . . . . . . . . . . . . 70 4.5.3 Octet Synchronous PPP . . . . . . . . . . . . ...
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PCI Slave Register Set (Direct Access .119 8.1.3 PCI and Local Bus Register Set (Direct ...
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Preliminary Data Sheet 8 PEB 20256 E PEF 20256 E 08.99 ...
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List of Figures Figure 1-1 MUNICH256 16-port Mode Logic Symbol . . . . . . . . . . . . . . . . . . . . . . .15 Figure 1-2 MUNICH256 28-port Mode Logic Symbol ...
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List of Figures Figure 9-9 Intel Write Cycle Timing (Master Mode, LRDY controlled .205 Figure 9-10 Intel Read Cycle Timing (Master Mode, Wait state controlled .206 Figure ...
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List of Tables Table 4-1 Interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Preliminary Data Sheet 12 PEB 20256 E PEF 20256 E Page 08.99 ...
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Multichannel Network Interface Controller for HDLC/ PPP MUNICH256 Version 2.1 1 MUNICH256 Overview The MUNICH256 is a highly integrated protocol controller that implements HDLC, PPP and transparent (TMA) protocol processing for 256 channels. An on- chip data management unit is ...
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System interface is a PCI 32 bit, 66 MHz Rev. 2.1 compliant bus interface, which supports configuration of subsystem ID / subsystem vendor ID via a serial EEPROM interface • Integrates a local microprocessor master and slave interface (demultiplexed ...
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Logic Symbol • AD[31:0] C/BE[3:0] FRAME TRDY IRDY STOP DEVSEL IDSEL PAR PCI REQ GNT CLK RST PERR SERR INTA SPCLK SPCS TM SPI SPI SPO SPLOAD Figure 1-1 MUNICH256 16-port Mode Logic Symbol Preliminary Data Sheet Test and ...
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AD[31:0] C/BE[3:0] FRAME TRDY IRDY STOP DEVSEL IDSEL PAR PCI REQ GNT CLK RST PERR SERR INTA SPCLK SPCS TM SPI SPI SPO SPLOAD Figure 1-2 MUNICH256 28-port Mode Logic Symbol Preliminary Data Sheet Test and Serial Reference interface ...
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General System Integration The MUNICH256 provides the HDLC/PPP or transparent (TMA) protocol handling for channelized or unchannelized applications with links. Protocol data is transferred to the packet RAM via the PCI bus and handled (e.g. for ...
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Pin Description Signal Type Definitions: The following signal type definitions are partly taken from the PCI Specification Rev Input is a standard input- only signal. Totem Pole Output is a standard active driver. O t/s, I/O ...
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PCI Bus Interface • Pin No. Symbol T3, T4, U1, U3, AD(31:0) V2, W1, W2, V4, AA2, W4, AC1, AB2, Y3, Y4, AD1, AC2, AC8, AE6, AD8, AF6, AC9, AE8, AF7, AD10, AC11, AF8, AF10, AD11, AC12, AE11, AD12, ...
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Pin No. Symbol V3, AA4, AD7, C/BE(3:0) AE9 AF4 PAR Preliminary Data Sheet Input (I) Output (O) t/s Command/Byte Enable During the transaction, C/BE(3:0) define the bus command. During the data phase, C/ BE(3:0) are used as byte enable lines. ...
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Pin No. Symbol AB3 FRAME AC6 IRDY Preliminary Data Sheet Input (I) Output (O) s/t/s Frame FRAME indicates the beginning and end of an access. FRAME is asserted to indicate a bus transaction is beginning. While FRAME is asserted, data ...
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Pin No. Symbol AD5 TRDY AF3 STOP AA1 IDSEL Preliminary Data Sheet Input (I) Output (O) s/t/s Target Ready TRDY indicates a slave’s ability to complete the current data phase of the transaction. indicates that valid data is present on ...
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Pin No. Symbol AE4 DEVSEL AC7 PERR AE5 SERR T2 REQ Preliminary Data Sheet Input (I) Output (O) s/t/s Device Select When activated by a slave, it indicates to the current bus master that the slave has decoded its address ...
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Pin No. Symbol T1 GNT R4 CLK R3 RST AC13 INTA Preliminary Data Sheet Input (I) Output (O) I Grant This signal is asserted by the arbiter to grant control MUNICH256 in response to a bus request via REQ. After ...
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SPI Interface • Pin No. Symbol P2 SPI P1 SPO N4 SPCLK N3 SPCS P4 SPLOAD Preliminary Data Sheet Input (I) Function Output (O) I SPI Serial Input SPI is a data input pin, where data coming from an ...
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Local Microprocessor Interface • Pin No. Symbol W24 LMODE Y24 LCLK AE13, AF13, LA(12:0) AF14, AE14, AF16, AC14, AD15, AE16, AF17, AC15, AD16, AF19, AE18 AC16, AD17, LD(15:0) AF20, AE19, AF21, AC18, AD19, AE21, AD20, AC19, AF23, AE24, AF25, ...
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Pin No. Symbol AC24 LRD or LDS AB24 LWR or LRDWR AA23 LRDY or DTACK Preliminary Data Sheet Input (I) Output (O) I/O Read (Intel Bus Mode) This active low signal selects a read transaction. I/O Data strobe (Motorola Bus ...
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Pin No. Symbol AC26 LINT AC25, W23 LCS2, LCS1 AD13 LBHE or LSIZE0 AA25 LHOLD or LBR Preliminary Data Sheet Input (I) Output (O) I/od Interrupt Request This line indicates general interrupt requests of the mailbox. The interrupt sources can ...
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Pin No. Symbol AB25 LHLDA or LBG V23 LBGACK Preliminary Data Sheet Input (I) Output (O) I Hold (Intel Bus Mode) LHLDA indicates processor has released control of the local bus. I Bus Grant (Motorola Bus Mode) LBG indicates that ...
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Serial Interface 16-port mode • Pin No. Symbol M24 TRD C15 TCLKO or TRCLK B5 TRSP N26 TTCLK C12 TTD C5 TTSP Preliminary Data Sheet Input (I) Function Output (O) O Test Receive Data In serial test mode the ...
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Pin No. Symbol R23, V25, U26, TCLK(15:0) R24, T25, P24, T26, P25, P26, N25, N23, L26, B14, C14, D14, A16 K26, M23, L25, TD(15:0) H26, L23, D20, B22, A23, C20, D19, B21, C19, A21, C16, B16, D15 N1, M3, L2, ...
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Pin No. Symbol N2, M4, L1, L4, RSP(15:0) H4, G3, G4, D1, D6, A6, C7, D8, B8, D9, B9, A10 B5, C5, D5, A4, RES1..16 B4, C4, E3, D2, RES20..21 H3, H2, J4, H1, J2, K4, K3, K1, D12, A11 ...
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Serial Interface 28-port mode • Pin No. Symbol C15 TCLKO or TRCLK M24 TRD N26 TTCLK C12 TTD K1, K3, K4, J2, TCLK(27:0) H1, J4, H2, H3, D2, E3, C4, B4, A4, D5, C5, B5, B8, A8, D9, C9, ...
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Pin No. Symbol R23, V25, U26, TD(27:0) R24, T25, P24, T26, P25, P26, N25, N23, L26, K26, M23, L25, H26, L23, D20, B22, A23, C20, D19, B21, C19, A21, C16, B16, D15 N2, M4, L1, L4, RCLK(27:0) H4, G3, G4, ...
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Test Interface • Pin No. Symbol C25 TCK F23 TMS A24 TDI D24 TDO B26 TRST E24 SCAN Preliminary Data Sheet Input (I) Function Output (O) I JTAG Test Clock This pin is connected with an internal pull- up ...
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Power Supply and No-connect Pins • Pin No. AF1, AE7, AF9, AE12, AE15, AF18, AE20, AF26, AD3, AD24, AD26, Y2, Y25, V1, V26, R2, T12, T11, R12, R11, T14, T13, R14, R13, T16, T15, R16, R15, R25, P12, P11, ...
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Pin No. AC4, AD6, AD9, AC10, AD14, AD18, AC17, AD21, AC23, AA3, AA24, W3, U4, V24, U23, P3, P23, N24, L24, J3, K23, J24, H23, F3, F24, D4, C6, D10, C13, D17, C18, C21, D23 E4, C1, B1, C2, A3, ...
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General Overview 3.1 Functional Overview The MUNICH256 is a highly integrated WAN protocol controller that performs HDLC, PPP and transparent (TMA) protocol processing on 256 full duplex serial channels and a configurable port mode with links. ...
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ID and the subsystem vendor ID via a SPI interface into the PCI configuration space. 3.2 Block Diagram • JTAG interface Interrupt controller Initiator bus TM SPI Interface Figure 3-1 MUNICH256 Block Diagram 3.3 Internal Interface ...
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The chip’s core functions are all operated with the PCI clock. Transfers between clocking regions (serial clocks and system clock) are implemented only in the serial port interface. 3.4 Block Description The following section gives a brief overview to the ...
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Data management units The data management units provide direct data transfer between the system memory and the ...
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JTAG Boundary Scan logic according to IEEE 1149.1. Preliminary Data Sheet 42 PEB 20256 E PEF 20256 E General Overview 08.99 ...
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Functional Description 4.1 Port Handler The port handler is the interface between the serial ports and the chip internal protocol functions. It converts incoming serial data into parallel data for further internal processing and in the outgoing direction it ...
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Interface configuration in 16-port mode TSP TCLK TD RSP RCLK RD b) Interface configuration in 28-port mode TCLK TD RCLK RD Figure 4-1 Port Configuration 4.1.2 External Timing Mode Each transmit port is clocked using the external timing ...
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Local Port Loop A local port loop can be closed in the port interface. It mirrors the outgoing bit stream of one port to the receive part of the same port. This allows to prepare data in system memory, ...
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RCLK(x) RSP(x) RD(x) TD(x) TSP(x) TCLK(x) Figure 4-3 Remote Payload Loop 4.1.5 Remote Channel Loopback A remote channel loop can be switched for one logical channel at a time. Incoming serial data located in the receive payload of one ...
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RCLK(x) RSP(x) RD(x) TD(x) TSP(x) TCLK(x) Figure 4-4 Remote Channel Loop Preliminary Data Sheet Receive Timeslot Port Assigner Loop Buffer Transmit Timeslot + Port Assigner 47 PEB 20256 E PEF 20256 E Functional Description Protocol To Machine PCI Protocol ...
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Test Breakout The test breakout function provides the capability to multiplex one of the incoming 16 (28) receive links to the outgoing test receive port, that is the incoming receive clock signal RCLK(x) is mapped to the test receive ...
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Time slot Handler 4.2.1 Channelized Modes The time slot handler assigns any combination of time slots of ports configured E1, 4.096 MHz or 8.192 MHz mode to logical channels. The assigned time slots are connected internally ...
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Frame Timeslot Timeslot Mask Example configuration: Port three in mode E1. Timeslot 2 and 3 are assigned to channel 5. Bit 0 of ...
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Data Management Unit Each packet or part of a packet is referenced by a descriptor. The descriptors form a link list, thus connecting all packets together. Packet data as well as descriptors are located in system memory. Both the ...
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Linked list in system memory in little endian mode Next Descriptor Pointer Data Pointer Next Descriptor Pointer Data Pointer ...
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Table 4-2 Receive Descriptor Structure DWORD ADDR HOLD RHI ...
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RHI Receive Host Initiated Interrupt This bit indicates that the MUNICH256 shall generate a ’Receive Host Initiated’ interrupt vector after it has finished processing the descriptor. 0 Data management unit does not generate an interrupt vector after it has processed ...
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NextReceiveDescriptorPointer This pointer contains the start address of the next valid receive descriptor. After completion of the current receive descriptor the data management unit branches to the next receive descriptor to continue data reception. System CPU can force the MUNICH256 ...
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When the MUNICH256 completes a data section, which included the end of a frame (C bit and FE bit are set), or when the MUNICH256 branches to a new linked list due to a ’Receive Abort/Branch’ command the status information ...
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In case that the requested transfer length from the receive buffer fits into the provided data section the data management unit ...
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Discard’ interrupt vector with the bits HRAB and RAB set is generated. If the current data section was filled and does contain the end of frame a ’Frame End’ interrupt vector is ...
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Therefore all information in the next descriptor must be valid when the data management unit branches to a descriptor. The last DWORD of a transmit descriptor optionally is written by the MUNICH256 when processing ...
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The channel can be reactivated by issuing a ’Transmit Hold Reset’ command or by providing a new linked list via the ’Transmit ...
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TransmitDataPointer This 32-bit pointer contains the start address of the transmit data section. Although the data management unit works DWORD oriented possible to begin transmit data section at byte addresses. CEN Complete Enable This bit is set by ...
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Depending on the bit field NO in the transmit descriptor several read accesses must be performed by the data management unit. ...
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If the HOLD bit is detected in a descriptor and the frame end bit is not set, the data management unit will transfer all data of the belonging data section to the transmit buffer. Afterwards it generates a ’Hold Caused ...
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Table 4-4 Example for little/big Endian with BNO = 3 BNO Little Endian 3 - Byte 2 Table 4-5 Example for little big Endian with BNO = 7 BNO Little Endian 7 Byte3 Byte 2 - Byte 6 4.3.7 Transmission ...
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Buffer Management 4.4.1 Internal Receive Buffer The internal receive buffer provides buffering of frame data and status between the protocol handler and the receive data management units. Internal buffers are essential to avoid data loss due to the PCI ...
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Example A: Normal operation Figure 4-8 Receive Buffer Thresholds For performance monitoring the receive buffer provides the capability to monitor the receive ...
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A programmable transmit buffer size and two programmable threshold are configurable by the host CPU for each channel. Note: The sum of both thresholds must be smaller than the transmit ...
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As long as the amount of data stored in the transmit buffer is below the transmit refill threshold the data management unit will keep filling the buffer by initiating PCI burst transfers. Note: Since there is a delay between ...
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Protocol Description The protocol machines provide protocol handling for up to 256 channels. The protocol machines implement 4 modes, which can be programmed independently for each channel: HDLC, bit-synchronous PPP, octet-synchronous PPP and transparent mode A. The configuration of ...
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CRC 1+x+x Optionally CRC transfer and check can be disabled. 4.5.2 Bit Synchronous PPP with HDLC Framing Structure • Flag Address 0111 1110 1111 1111 Figure 4-11 Bit Synchronous PPP with HDLC Framing Structure Same as HDLC. ...
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If in the transmit direction a data underrun occurs during transmission of a frame and the frame has not finished, an abort sequence is automatically sent (escape character followed by a flag) and an underrun interrupt vector will generated. If ...
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Mailbox The MUNICH256 contains a mailbox to allow communication between two intelligent peripherals connected to the PCI bus and the local microprocessor bus. The mailbox is organized in two pages of eight registers. The first page is used to ...
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MBE2P1 through MBE2P7 and then it writes status information to the mailbox status register MBE2P0. This causes a system interrupt vector to be written to the PCI host system, indicating that valid data is contained in the mailbox data registers. ...
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Interrupt Controller All layer two interrupts (channel, port, system and command interrupts) are handled via an internal interrupt controller which forwards those interrupts to external interrupt queues. This interrupt controller is connected to the PCI interrupt pin INTA. Mailbox ...
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Int. vector setup: CONF1, CONF2 System interrupts 1 Interrupt status: GISTA, GMASK Interrupt queue setup: IQIA, IQBA, IQL, IQMASK FFFFFFFF H System memory Interrupt queue IQBA 00000000 H Figure 4-13 Layer Two Interrupts (Channel, command, port and system interrupts ...
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In this case the interrupt pin INTA is not asserted, but the interrupt vector is still written into the assigned interrupt queue. An interrupt queues is a reserved memory locations in system memory. The ...
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TYPE Interrupt type The interrupt vectors are divided into four basic groups, where TYPE determines the interrupt group. A further classification of interrupts is done with the subtype indication. 00 Command interrupts B 01 Channel interrupts B 10 Port interrupts ...
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System Interrupts • • MB Mailbox The ’Mailbox’ interrupt vector is generated, in case that the local microprocessor has written data to the mailbox status register MBE2P0. The ...
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Port Interrupts Port interrupt vectors indicate the synchronous or asynchronous state of a port. Immediately after enabling both, the port and the port interrupts, port interrupts are generated indicating the synchronous or asynchronous state of a port. After this ...
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Receive Interrupts • • PORT Port Number This bit field identifies the port for which the information in the interrupt vector is valid. SYN ...
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Channel Interrupts Channel interrupt are divided into two subtypes: • Receive Interrupt I and Transmit Interrupt I • Receive Interrupt II and Transmit Interrupt II Subtype I contains interrupts which indicate the general status of a channel. These interrupts ...
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SFD Small Frames Dropped The ’Small Frames Dropped’ interrupt vector is generated, when the receiver discarded N small frames. The length of small frames is defined in CONF3.MINFL and the threshold value N is defined in register SFDT. CHAN Channel ...
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Receive Interrupt II • RHI RAB FE HRAB MFL RFOD CRC ILEN • CHAN Channel Number This bit field identifies the channel for which the ...
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MFL Maximum Frame Length Exceeded The ’Maximum Frame Length Exceeded’ interrupt vector is generated, when the length of a received data packet exceeded the frame length defined in CONF1.MFL. RFOD Receive Frame Overflow DMA The ’Receive Frame Overflow DMA’ interrupt ...
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HTAB Hold Caused Transmit Abort The ’Hold Caused Transmit Abort’ interrupt vector is generated, when data management unit retrieved a transmit descriptor where HOLD was set and FE equals 0. The interrupt will be generated after the data section was ...
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Command Interrupts Command interrupts are written to the command interrupt queue (interrupt queue eight). Transmit Interrupts • 0010 • TCF Transmit Command Failed The ’Transmit Command Failed’ interrupt ...
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Receive Interrupts • 0000 • RCC Receive Command Complete The ’Receive Command Complete’ interrupt vector is issued after successful completion of commands ’Receive Init’ and ’Receive Off’, which can ...
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Mailbox Interrupts to the Local Bus Mailbox interrupts are stored in an internal interrupt FIFO which is located inside the MUNICH256 and can be read from either the local microprocessor or (for test purposes) via the chip internal bridge ...
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LAST 0 The ’Mailbox’ interrupt vector is generated, in case that the host CPU on PCI side has written data to the mailbox status register MBP2E0. LAST Last indication LAST indicates that at least one ...
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Interface Description 5.1 PCI Interface A 32-bit and 66 MHz capable PCI bus controller provides the interface between the MUNICH256 and the host system. PCI Interface pins are measured as compliant to the 3.3V signalling environment according PCI specification ...
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IRDY is deasserted on clock 7, and FRAME stays asserted. Only when IRDY is asserted can FRAME be deasserted, which occurs on clock 8. • CLK FRAME AD Address C/BE Command IRDY TRDY DEVSEL Address phase ...
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CLK FRAME AD Address C/BE Command IRDY TRDY DEVSEL Address phase Figure 5-2 PCI Write Transaction 5.2 SPI Interface (ROM Load Unit) Additional pins, which are not covered from the PCI specification, but are closely related, are ...
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PCI Interface directly after a system reset. In this case the PCI configuration space contains the default values. 5.2.1 Accesses to a SPI EEPROM The EEPROM contents can also be controlled (read and write) ...
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SPSI pin. The read operation is terminated by setting SPCS high (see Figure 5-3). • SPCS 0 1 SPCLK SPSO 0 0 ...
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Local Microprocessor Interface The Local Microprocessor Interface is a demultiplexed switchable Intel or Motorola style interface with master and slave functionality. The MUNICH256 provides a local clock output LCLK, which is a feed through of the PCI system clock ...
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Intel Mode 5.3.1.1 Slave Mode In Intel slave mode the bus interface supports 16-bit transactions in demultiplexed bus operation. It uses the local bus port pins LA(12:1) for the 16 bit address and the local bus port pins LD(15:0) ...
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LA(12:0) 1 LBHE LCS0 (In) LCS1,2 (Out) LRD LWR 2 LRDY LD(15:0) Note 1: Supported in local bus master mode only. Note 2: Ready controlled bus cycles only. Figure 5-5 Intel Bus Mode • 1 LHOLD LHLDA Bus Cycle ...
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Access Error’ interrupt vector. Table 5-2 C/BE to LA/LBHE mapping and correspondence between PCI data and local bus in Intel bus mode (8 bit port mode) C/BE(3:0) LA(1:0) ...
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Motorola Mode 5.3.2.1 Slave Mode The demultiplexed bus modes use the local bus port pins LA(12:1) for the 16- bit address and the local bus port pins LD(15:0) for 16 bit data. A read/write access is initiated by placing ...
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LA(12:0) 1 LSIZE0 LCS0 (In) LCS1,2 (Out) LDS LRDWR 2 LDTACK LD(15:0) Note 1: Supported in local bus master mode only. Note 2: LDTACK controlled bus cycles only. Figure 5-7 Motorola Bus Mode • 1 LBR LBG LBGACK Bus ...
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The address and byte enable signals on the PCI bus are mapped to the local bus according to table 5-4 and table 5-5. It can be seen that the MUNICH256 supports different valid C/BE combinations which result in either a ...
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Serial Line Interface The serial interface of the interface can be configured in a 16-port mode and additionally in a 28-port mode. Dependent on the port configuration (16-port mode or 28-port mode) the MUNICH256 supports T1, E1, channelized 4.096 ...
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Interface Timing in 16-port mode In 16-port mode each receive port has a receive data input RD(x), a receive synchronization input RSP(x) and the corresponding receive clock input RCLK(x). In transmit direction each port consists of the transmit data ...
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Time slot 31 (E1), 63 (4.096 MHz), 127 (8.192 MHz) E1 frame, 4.096 MHz frame or 3 8.192 MHz frame 1 TCLK(x) 1 TSP(x) 1 TD(x) B3 Transmit 2 Bit Shift 1. TSP(x) sampled with the rising edge of ...
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TCLK(x) Reference 1 Clock 2 TD(x) RCLK(x) 3 RD(x) 1. Reference Clock is provided for high speed port #0. 2. TD(x) can be transmitted synchronous to the rising or the falling edge of TCLK(x). 3. RD(x) can be sampled ...
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E1 frame 1 TCLK(x) 1 TD(x) 1. TD(x) updated with the falling edge of TCLK(x). E1 frame 2 RCLK(x) 2 RD(x) 2. RD(x) sampled with the rising edge of RCLK(x). Figure 5-14 E1-mode Interface Timing in 28-port Mode Preliminary ...
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JTAG Interface A test access port (TAP) is implemented in the MUNICH256. The essential part of the TAP is a finite state machine (16 states) controlling the different operational modes of the boundary scan. Both, TAP controller and boundary ...
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The desired test mode is selected by serially loading a 4-bit instruction code into the instruction register via TDI (LSB first). EXTEST is used to examine the interconnection of the devices ...
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Channel Programming / Reprogramming Concept For channel programming the MUNICH256 provides a on-chip channel specification data structure. All information necessary to setup a channel has to be provided using this data structure. As soon as all channel information has ...
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Register CSPEC_XMIT_ACCM CSPEC_BUFFER CSPEC_FRDA CSPEC_FTDA CSPEC_IMASK 6.1 Channel Commands The following section describes all receive and transmit channel commands and the programming sequence in details. 6.2 Transmit Channel Commands Transmit Init Before a ’Transmit Init’ command is given, the MUNICH256 ...
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Command Failed’ interrupt vector. Furthermore the MUNICH256 will not start processing the linked list for this particular channel. New commands for the same channel may be given after the user received ...
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The MUNICH256 will NOT generate a ’Transmit Command Complete’ interrupt vector after this command is programmed. Transmit Update FNUM The ’Transmit Update CSPEC_MODE_XMIT.FNUM in the internal channel database, which allows to change dynamically the number of idle flags that are ...
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A ’Receive Command Complete’ interrupt vector is generated after the channel information is copied into the internal channel database. New commands for the same channel may be given after the MUNICH256 issued the ’Receive Command Complete’ interrupt vector. Prior to ...
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Receive Debug The ’Receive Debug’ command allows to read back the current settings of the internal channel database. After the ’Receive Debug’ command has been programmed system software can read back the current values of the channel specification registers. Register ...
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Reset and Initialization procedure Since the term “initialization” can have different meanings, the following definition applies: Chip Initialization Generating defined values in all on-chip registers, RAMs (if required), flip-flops etc. Mode Initialization Software procedure, that prepares the device to ...
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The register bit CONF1.IIP is the result of all signals. As soon as all internal modules have finished their RAM initialization the register bit CONF1.IIP is deasserted. Software must poll the register bit CONF1.IIP until ...
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Register Description The register description of the MUNICH256 is divided into two parts, an overview of all internal registers and in the second part a detailed description of all internal registers. 8.1 Register Overview The first part of the ...
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Register Access Address CISP R SSID/ R SSVID ERBAD R Reserved R Reserved R MAXLAT/ MINGNT/ R/W INTPIN/ INTLIN User defined configuration space register SPI R/W REQ R/W MEM R/W DEBUG R Preliminary Data Sheet Reset Comment value 28 00000000 ...
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PCI Slave Register Set (Direct Access) This section shows all registers which are located on the first configuration bus. These registers are used to setup the basic operating modes of the device and to setup the port, time slots ...
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Register Access Address *_FTDA R/W *_IMASK R/W Port and time slot control registers PMIAR R/W PMR R/W REN R/W TEN R/W TSAIA R/W TSAD R/W PPP character map/ demap registers REC_ACCMX R/W XMIT_ACCMX R/W Receive buffer control RBMON R RBTH ...
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PCI and Local Bus Register Set (Direct Access) This section describes the registers which are located on the configuration bus II (see also "MUNICH256 Block Diagram" on page 3-39). These registers can be accessed either from PCI bus via ...
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Register Access MBP2E1 MBP2E2 MBP2E3 MBP2E4 R/W MBP2E5 MBP2E6 MBP2E7 Preliminary Data Sheet Address Address Reset (Local (PCI) value Bus) 164 168 16C 170 38 0000 H H 174 3A H ...
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Detailed Register Description 8.2.1 PCI Configuration Register DID/VID Device ID/Vendor ID Access : read Address : 00 H Reset Value : 2106110A 31 15 DID Device ID The device ID identifies the particular device hardwired to value ...
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STAT/CMD Status/Command Register Access : read/write Address : 04 H Reset Value : 02A00000 DPE SSE RMA RTA DPE Detected Parity Error This bit will be asserted whenever ...
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RTA Received Target Abort This bit will be set whenever a transaction in which the MUNICH256 acted as bus master was terminated with target abort target abort detected. 1 Transaction terminated with target abort. This bit will be ...
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CC/RID Class Code/Revision ID Access : read Address : 08 H Reset Value : 02800001 31 BCL(7:0) 15 ICL(7:0) The class code, consisting of base class, subsystem class and interface class, is used to identify the generic function of the ...
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BIST/Header Type/Latency Timer/Cache Line Size Access : read/write Address : 0C H Reset Value : 00000000 LT(7:3) LT Latency Timer The value of this register times eight specifies, in units of PCI clocks, the value ...
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BAR1 Base Address 1 Access : read/write Address : 10 H Reset Value : 00000000 BAR(31:12) 0 The first base address of the MUNICH256 is marked as non-prefetchable and can be relocated anywhere in 32 bit address ...
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BAR2 Base Address 2 Access : read/write Address : 14 H Reset Value : 00000000 The second base address of the MUNICH256 is marked as non-prefetchable and can be relocated anywhere in 32 bit ...
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SID/SVID Subsystem ID/Subsystem vendor ID Access : read Address : 2C H Reset Value : 00000000 31 15 SID Subsystem ID The subsystem ID uniquely identifies the add-in board or subsystem where the system resides. The value of SID may ...
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ML/MG/IP/IL Maximum Latency/Minimum Grant/Interrupt Pin/Interrupt Line Access : read/write Address : 3C H Reset Value : 06020100 31 ML(7:0) 15 IP(7:0) ML Maximum Latency This value specifies how often the device needs to access the PCI bus in multiples of ...
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SPI SPI Access Register Access : read/write Address : 40 H Reset Value : 0000001F SBA(7:0) SPIS SPI Start To start the EEPROM transaction, which is defined in the SPI command, the byte ...
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SD SPI Data For the write status register transactions and the write data to memory array transactions, the data, that has to be written to the EEPROM, must be written to this register before the transaction is started. After a ...
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LR Long Request Register Access : read/write Address : 44 H Reset Value : 00000000 Long Request 0 The PCI interface deasserts the REQ signal in parallel ...
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MEM PCI Memory Command Register Access : read/write Address : 48 H Reset Value : 000007E6 BAR2 Enable Base Address Register 2 Setting this bit enables Base ...
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EEPROM or by reading or writing from PCI side. Preliminary Data Sheet Register Description 136 PEB 20256 E PEF 20256 E 08.99 ...
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DEBUG PCI Debug Support Register Access : read Address : 4C H Reset Value : 00000000 31 15 DSR Debug Support register The value of this register contains the address of the next initiator transfer during normal operation. In case ...
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PCI Slave Register CSPEC_CMD Channel Specification Command Register Access : read/write Address : 000 H Reset Value : 00000000 31 CMDX(7: The channel specification registers are the access registers to the chip internal ...
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CMDX Command Transmit For detailed description of transmit commands and programming sequences refer to Chapter 6.2. 01 Transmit Init H 02 Transmit Off H 04 Transmit Abort/Branch H 08 Transmit Hold Reset H 10 Transmit Debug H 20 Transmit Idle ...
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CSPEC_MODE_REC Channel Specification Mode Receive Register Access : read/write Address : 004 H Reset Value : 00000000 DEL SFDE TFF INV TMP CRCX CRC DEL DEL (Delete) Demap ...
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SFDE Short/Small Frame Drop Enable This bit enables either the drop of short frames or the drop of small frames. This bit is valid in HLDC and PPP modes only. 0 Short Frame Drop. Frames smaller than four bytes payload ...
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CRC32 CRC32 Select This bit selects the generator polynomial in the receiver. The checksum of incoming data packets will be compared against CRC16 or CRC32. CRC Select is valid in HDLC and PPP modes only. 0 Select CRC16 checksum. 1 ...
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CSPEC_REC_ACCM Channel Specification Receive ACCM Map Register Access : read/write Address : 008 H Reset Value : 00000000 Any of ...
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CSPEC_MODE_XMIT Channel Specification Mode Transmit Register Access : read/write Address : 014 H Reset Value : 00000000 31 FNUM(7: IFTF 0 FA INV TMP FNUM Flag number FNUM denotes the number of flags send between two ...
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INV Bit Inversion If bit inversion is enabled outgoing channel data is inverted after processed by the protocol machine. E.g. a outgoing idle flag is transmitted as octet 81 0 Disable bit inversion. 1 Enable bit inversion. TMP Transparent Mode ...
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DEL DEL (Delete) Map Flag This bit enables mapping of the control character DEL. This bit is valid in PPP modes only. 0 Disable mapping of DEL. 1 Enable mapping of DEL. PMD Protocol Machine Mode This bit field selects ...
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CSPEC_XMIT_ACCM Channel Specification Transmit ACCM Map Register Access : read/write Address : 018 H Reset Value : 00000000 Any of ...
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CSPEC_BUFFER Channel Specification Buffer Configuration Register Access : read/write Address : 020 H Reset Value : 00200000 TQUEUE(2: TBRTC(3:0) TQUEUE Transmit Interrupt Vector Queue This bit field determines the interrupt queue where channel interrupts ...
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TBFTC Transmit Buffer Forward Threshold Code Note: Please note that the internal architecture is 32 bit wide. Therefore each buffer location corresponds to four data octets. TBFTC is a coding for the transmit buffer forward threshold. Please refer to Table ...
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Coding Threshold in DWORDs 1001 64 B 1010 96 B 1011 128 B 1100 192 B 1101 256 B 1110 384 B 1111 512 B Preliminary Data Sheet RBTC TBFTC x x Not Valid 150 PEB 20256 E PEF 20256 ...
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CSPEC_FRDA Channel Specification FRDA Register Access : read/write Address : 024 H Reset Value : 00000000 31 15 FRDA First Receive Descriptor Address This 30-bit pointer contains the start address of the first receive descriptor. The receive descriptor is read ...
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CSPEC_FTDA Channel Specification FTDA Register Access : read/write Address : 028 H Reset Value : 00000000 31 15 FTDA First Transmit Descriptor Address This 30-bit pointer contains the start address of the first transmit descriptor. The transmit descriptor is read ...
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CSPEC_IMASK Channel Specification Interrupt Vector Mask Register Access : read/write Address : 02C H Reset Value : 00000000 TAB 0 HTAB RAB RFE HRAB MFL ROFD CRC ILEN RFOP ...
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Command Interrupt Vector Receive RAB Mask ’Receive Abort’ RFE Mask ’Receive Frame End’ HRAB Mask ’Hold Caused Receive Abort’ MFL Mask ’Maximum Frame Length Exceeded’ RFOD Mask ’Receive Frame Overflow DMU’ CRC Mask ’CRC Error’ ILEN Mask ’Invalid Length’ RFOP ...
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CONF1 Configuration Register 1 Access : read/write Address : 040 H Reset Value : 820000F1 31 IIP MFL(12:0) IIP Initialization in Progress (Read Only) After reset (hardware reset or software reset) the internal RAM’s are ...
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IIP will be asserted. When IIP is deasserted system software can reset SRST to ’0’ to start normal operation again. 0 Normal operation 1 Start software reset. 28/16 Select 28/16-port mode This bit switches between the 28-port mode and the ...
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Disable interrupt vector. SFL Short Frame Length This bit is a global parameter which defines the length of short frames for all channels. 0 Short frame is defined as a frame containing less than 4 bytes (CRC16) or less ...
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CONF2 Configuration Register 2 Access : read/write Address : 044 H Reset Value : 00000000 SYSQ(2: RCL 0 0 SYSQ System Interrupt Queue SYSQ sets up the interrupt queue where system ...
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The incoming transmit clock of port zero is visible on pin TCLKO. This function is available when port zero is operated in unchannelized mode. 1 Pin TCLKO is set to tri-state. RCL Remote Channel Loop The remote channel loop ...
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CONF3 Configuration Register 3 Access : read/write Address : 048 H Reset Value : 00090000 MINFL(5:0) TPBL Transmit Packet Burst Length This bit field is a coding for the maximum ...
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RBAFT Receive Buffer Access Failed Interrupt Threshold Register Access : read/write Address : 04C H Reset Value : 00000000 31 15 RBAFT Receive Buffer Access Failed Interrupt Threshold This register sets the threshold for the ’Receive Buffer Access Failed’ interrupt ...
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SFDT Small Frame Dropped Interrupt Threshold Register Access : read/write Address : 050 H Reset Value : 00000000 31 15 SFDIT Small Frame Dropped Interrupt Vector Threshold The programmed threshold defines the threshold for the ’Small Frame Dropped’ interrupt vector. ...
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PMIAR Port Mode Indirect Access Register Access : read/write Address : 060 H Reset Value : 00000000 Note: This register is an indirect access register which must be ...
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PMR Port Mode Register Access : read/write Address : 064 H Reset Value : 0104C000 31 28 PCM(3: RIM TIM RXF TXR RSF Note: Effected port is selected via register PMIAR. All settings in ...
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RIM Receive Synchronization Error Interrupt Vector Mask This bit disables generation of the port interrupt vector receive. See "Port Interrupts" on page 4-79 for description of interrupt vectors. 0 Enable 1 Disable TIM Transmit Synchronization Error Interrupt Vector Mask This ...
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TSF Transmit Synchronization Pulse Falling This bit selects the sample mode for incoming transmit synchronization pulse. The transmit synchronization pulse can be sampled on the rising or falling edge of the selected transmit clock. 0 Sample transmit synchronization pulse on ...
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REN Receive Enable Register Access : read/write Address : 068 H Reset Value : 00000000 REN Receive Enable Setting a bit in this bit field enables the receive function of the selected port. ...
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TEN Transmit Enable Register Access : read/write Address : 06C H Reset Value : 00000000 TEN Transmit Enable This bit field enables the transmit function of the selected port. After reset all transmit ...
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TSAIA Time slot Assignment Indirect Access Register Access : read/write Address : 070 H Reset Value : 00000000 31 DIR DIR Direction This bit select the direction for which programming is ...
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TSNUM Time Slot Number This bit field selects the time slots, which can be accessed via register TSAIA. Valid time slot numbers are: 0..23 T1, Unchannelized 0..31 E1 0..63 4.096 MHz Channelized 0..127 8.192 MHz Channelized Preliminary Data Sheet Register ...
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TSAD Time slot Assignment Data Register Access : read/write Address : 074 H Reset Value : 02000000 CHAN(7:0) Note: The time slot assignment data register assigns a channel and a mask to a ...
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MASK Mask Bits Setting a bit in this bit field selects the corresponding bit in a time slot which is enabled for operation receive direction the corresponding bit is discarded. In transmit direction the bit is tri-stated. 1 ...
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REC_ACCMX Receive Extended ACCM Map Register Access : read/write Address : 080 H Reset Value : 00000000 31 CHAR3(7:0) 15 CHAR1(7:0) This register is only used by channels operated in octet synchronous PPP mode. A character written to this register ...
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RBAFC Receive Buffer Access Failed Counter Register Access : read Address : 084 H Reset Value : 00000000 31 15 RBAFC Receive Buffer Access Failed Counter The read value of this register defines the number of packets which have been ...
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SFDIA Small Frame Dropped Indirect Access Register Access : read/write Address : 088 H Reset Value : 00000000 AIC Auto Increment Channel This bit enables the auto increment ...
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SFDC Small Frame Dropped Counter Register Access : read Address : 08C H Reset Value : 00000000 31 15 These both bit fields show the current value of the small frame dropped counter of the channel N and N+1 selected ...
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XMIT_ACCMX Transmit Extended ACCM Map Access : read/write Address : 090 H Reset Value : 00000000 31 CHAR3(7:0) 15 CHAR1(7:0) This register is only used by a channel in octet synchronous PPP mode. A character written to this register will ...
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RBMON Receive Buffer Monitor Indirect Access Register Access : read Address : 0B0 H Reset Value : 02000BFF RBAQC Receive Buffer Action Queue Free Count The value of ...
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RBTH Receive Buffer Threshold Register Access : read/write Address : 0B4 H Reset Value : 02000001 RBAQTH Receive Buffer Action Queue Free Pool Threshold Function of RBAQTH is ...
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IQIA Interrupt Queue Indirect Access Register Access : read/write Address : 0E0 H Reset Value : 00000000 DBG Debug This bit selects the debug mode of the interrupt ...
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SIQL Set Interrupt Queue Length This bit field enables setup of the interrupt queue length of queue Q. The value to be programmed has to be configured via register IQL prior to a write access to this bit ...
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IQBA Interrupt Queue Base Address Register Access : read/write Address : 0E4 H Reset Value : 00000000 31 15 IQBA Interrupt Queue Base Address The interrupt queue base address register assign s a base address to the eight channel interrupt ...
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IQL Interrupt Queue Length Register Access : read/write Address : 0E8 H Reset Value : 00000000 IQL Interrupt Queue Length This bit field assigns a interrupt queue length ...
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IQMASK Interrupt Queue High Priority Mask Access : read/write Address : 0EC H Reset Value : 00000000 THI TAB 0 HTAB RHI RAB RFE HRAB MFL ROFD CRC ILEN RFOP SF ...
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GISTA/GIACK Interrupt Status/Interrupt Acknowledge Register Access : read/write Address : 0F0 H Reset Value : 00000000 31 INTOF Depending on the corresponding bits in register GMASK, an interrupt indication in ...
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LINT changes from an inactive to an active state the interrupt pin INTA will be asserted. Note: This bit does not clear by writing a ’1’. This bit is set as long as the interrupt pin LINT is asserted. ...
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GMASK Global Interrupt Mask Register Access : read/write Address : 0F4 H Reset Value : FFFFFFFF 31 INTOF Each bit in this register mask the interrupts, which are flagged in ...
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PCI and Local Bus Slave Register Set FCONF Configuration Register Access : read/write Address : 100 (PCI Reset Value : 8080 IIP IIP Initialization in Progress (Read Only) After reset ...
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BSD Byte Swap Disable This bit disables byte swapping on 16-bit transfers when the local bus is operated in Motorola master mode. 0 Enable byte swap. 1 Disable byte swap. P28..P08 Switch Page 2..0 to 8-bit mode The MUNICH256 maps ...
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MTIMER Master Local Bus Timer Register Access : read/write Address : 104 (PCI Reset Value : 0000 H 15 TIMER Local Bus Latency Timer TIMER*16 determines the time in clock cycles the MUNICH256 holds the local bus as ...
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INTCTRL Interrupt Control Register Access : read/write Address : 108 (PCI Reset Value : 0001 Interrupt Direction This pin determines the direction of the interrupt pin LINT. 0 LINT is ...
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INTFIFO Interrupt FIFO Access : read Address : 10C (PCI Reset Value : FFFF Interrupt Vector After the MUNICH256 asserted interrupt pin LINT on the local bus side, this bit field contains an interrupt vector ...
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MBE2P0 Mailbox Local Bus to PCI Command Register Access : read/write Address : 140 (PCI Reset Value : 0000 Mailbox Data register This register can be written and read from local bus side. From PCI ...
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MBE2P1-7 Mailbox Local Bus to PCI Data Register 1-7 Access : read/write Address : 144 -15C H Reset Value : 0000 Mailbox Data register This register can be written and read from local bus side. From PCI ...
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MBP2E0 Mailbox PCI to Local Bus Status Register Access : read/write Address : 160 (PCI Reset Value : 0000 Mailbox Status Register This register can be written and read from PCI side. From local bus ...
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MBP2E1-7 Mailbox PCI to Local Bus Data Register 1-7 Access : read/write Address : 164 -17C H Reset Value : 0000 Mailbox Data Register This register can be written and read from PCI side. From local bus ...
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Electrical Characteristics 9.1 Important Electrical Requirements Both V and V can take on any power-on sequence. Within 50 milliseconds of DD3 DD25 power-up the voltages must be within their respective absolute voltage limits. At power- down, within 50 milliseconds ...
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Parameter Core operational supply power down current (no clocks) V DD25 I/O supply operational current power down V (no clocks) DD3 Sum of Input leakage current and Output leakage current (Outputs Hi-z) Power Dissipation b) Non-PCI Interface Pins Table 9-3 ...
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Parameter L-output voltage H-output voltage 9.4 AC Characteristics a) Non-PCI interface pins = - 3 DD3 Inputs are driven to 2.4 V for a logical ‘1’ and to 0.4 V for a ...
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PCI Bus Interface Timing • 0.6 V 0.5 V DD3 0.4 V DD3 0.3 V DD3 Figure 9-2 PCI Clock Cycle Timing Table 9-5 PCI Clock Characteristics Parameter CLK cycle time CLK high time CLK low time CLK slew ...