LT6552IS8 Linear Technology, LT6552IS8 Datasheet - Page 14

• Manufacturer Part Number: LT6552IS8
• Description: IC OPAMP VID DIFF SGL 3.3V 8SOIC
• Manufacturer: Linear Technology

Specifications of LT6552IS8

• Applications: Differential
• Number Of Circuits: 1
• -3db Bandwidth: 75MHz
• Slew Rate: 600 V/µs
• Current - Supply: 14mA
• Current - Output / Channel: 70mA
• Voltage - Supply, Single/dual (±): 3 V ~ 12.6 V, ±1.5 V ~ 6.3 V
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PACKAGE DESCRIPTIO
LT6552
APPLICATIO S I FOR ATIO
SHDN Pin
The LT6552 includes a shutdown feature that disables the
part, reducing quiescent current and making the output
high impedance. The part can be shutdown by bringing the
SHDN pin within 0.5V of V
current is typically 400 A and the output leakage current
14
3.5 0.05
U
2.15 0.05
U
–
. When shutdown the supply
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
TOP MARK
1.65 0.05
(2 SIDES)
(NOTE 6)
0.25 0.05
PIN 1
0.200 REF
W
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
U
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
ON TOP AND BOTTOM OF PACKAGE
2.38 0.05
(2 SIDES)
8-Lead Plastic DFN (3mm 3mm)
(Reference LTC DWG # 05-08-1698)
U
0.50
BSC
DD Package
0.675 0.05
0.75 0.05
3.00 0.10
(4 SIDES)
PACKAGE
OUTLINE
is 0.25 A (V
can be tied to V
nected, an internal FET pull-up will keep the LT6552 fully
operational.
0.00 – 0.05
1.65 0.10
(2 SIDES)
–
BOTTOM VIEW—EXPOSED PAD
0.25 0.05
R = 0.115
V
+
OUT
TYP
4
or left floating; if the pin is left uncon-
5
2.38 0.10
(2 SIDES)
V
+
). In normal operation the SHDN
8
1
0.50 BSC
0.38 0.10
(DD8) DFN 1203
6552f