XPC107APX100LC Freescale Semiconductor, Inc, XPC107APX100LC Datasheet
XPC107APX100LC
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Advance Information MPC107EC/D Rev. 1, 11/2002 MPC107 PCI Bridge/Memory Controller Hardware Specifications This document provides an overview of the MPC107 PCI bridge/memory controller (PCIB/MC) for high-performance embedded systems. The MPC107 is a cost-effective, general-purpose PCIB/MC for applications using PCI in ...
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Features MPC107 60x Bus Interface (64- or 32-Bit Data Bus) Peripheral Logic Block Message Unit (with DMA Controller Controller PIC 5 Direct/ Interrupt 16 Serial Controller/ Interrupts Timers PCI Interface 1.2 ...
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Low-voltage TTL logic (LVTTL) interfaces — Port X: 8-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with programmable address strobe timing • 32-bit PCI interface operating MHz — PCI 2.1-compliant — PCI 5.0-V ...
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General Parameters • Built-in PCI bus performance monitor facility • Debug features — Error injection/capture on data path — IEEE 1149.1 (JTAG)/test interface • Processor interface — Supports up to two PowerPC microprocessors with 60x bus interface — Supports various ...
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Absolute Maximum Ratings The tables in this section describe the MPC107 DC electrical characteristics. Table 1 provides the absolute maximum ratings. 1 Characteristic Supply voltage—core Supply voltage—memory bus drivers Supply voltage—processor bus drivers Supply voltage—PCI and standard I/O buffers ...
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Electrical and Thermal Characteristics 1.4.1.2 Recommended Operating Conditions Table 2 provides the recommended and tested operating conditions for the MPC107. Proper device operation outside of these conditions is not guaranteed. Table 2. Recommended Operating Conditions Characteristic Supply voltage Supply voltages ...
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Figure 2 shows supply voltage sequencing and separation cautions 3 2 Voltage Regulator Delay Power Supply Ramp Up Reset Configuration Pins HRESET HRESET_CPU Notes: 1. Numbers associated with waveform separations correspond to caution ...
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Electrical and Thermal Characteristics Figure 3 shows the undershoot and overshoot voltage of the memory interface of the MPC107 GND GND – 0 GND – 1.0 V Figure ...
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Table 3. DC Electrical Specifications (continued) At recommended operating conditions (See Table 2) Characteristics Output high voltage I = driver dependent OH (BV DD All outputs except CPU_CLK[0: driver dependent OH (BV DD CPU_CLK[0:2] only Output low voltage ...
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Electrical and Thermal Characteristics 1.4.1.4 Output Driver Characteristics Table 4 provides information on the characteristics of the output drivers referenced in Table 17. The values are from the MPC107 IBIS model (v1.1) and are not tested. For additional detailed information, ...
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Power Characteristics Table 5 provides the preliminary power consumption estimates for the MPC107. Power consumption on the PLL supply pin (AV ) and the DLL supply pin (LAV DD and is not tested. 25/50 Mode V I/O DD Power ...
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Electrical and Thermal Characteristics 1.4.1.6 Thermal Characteristics Table 6 provides the package thermal characteristics for the MPC107. Refer to Section 1.7, “System Design Information,” for more details about thermal management. Table 6. FC-PBGA Package Thermal Characteristics Characteristic Junction-to-ambient natural convection ...
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Clock AC Specifications Table 8 provides the clock AC timing specifications as defined in Section 1.4.2.2. These specifications are for the default driver strengths indicated in Table 4. Table 8. Clock AC Timing Specifications At recommended operating conditions (See ...
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Electrical and Thermal Characteristics Table 8. Clock AC Timing Specifications (continued) At recommended operating conditions (See Table 2) with LV 20 OSC_IN Duty Cycle Measured at 1 OSC_IN Frequency Stability Notes: 1 Rise and fall times for the ...
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MPC107 Spec. 10 PLL OSC_IN Specs Figure 5. Clock Subsystem Block Diagram 25 MHz MHz MHz 20 ns 100 MHz Propagation Delay Time in Nanoseconds loop ...
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Electrical and Thermal Characteristics 1.4.2.2 Input AC Timing Specifications Table 9 provides the input AC timing specifications. See Figure 7 and Figure 8. Table 9. Input AC Timing Specifications At recommended operating conditions (see Table 2) with LVdd = 3.3 ...
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PCI_SYNC_IN SDRAM_SYNC_IN shown in 2:1 mode 10b-d MEMORY INPUTS/OUTPUTS Input Timing Figure 7. Input - Output Timing Diagram Referenced to SDRAM_SYNC_IN . PCI_SYNC_IN 10a PCI INPUTS/OUTPUTS Input Timing Figure 8. Input - Output Timing Diagram Referenced to PCI_SYNC_IN Figure 9 ...
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Electrical and Thermal Characteristics Table 10. Output AC Timing Specifications At recommended operating conditions (see Table 2) with LVdd = 3.3 V ± 0.3 V Num Characteristic 12a PCI_SYNC_IN to output valid, 66 MHz PCI, with SDMA4 pulled-down to logic ...
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PCI Signal Output Hold Timing In order to meet minimum output hold specifications relative to PCI_SYNC_IN for both 33 MHz and 66 MHz PCI systems, the MPC107 has a programmable output hold delay for PCI signals. The initial value ...
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Electrical and Thermal Characteristics PCI_SYNC_IN 12a for 33 MHz PCI PCI_HOLD_DEL = 100 PCI INPUTS/OUTPUTS 33 MHz PCI 12a for 66 MHz PCI PCI_HOLD_DEL = 000 PCI INPUTS/OUTPUTS 66 MHz PCI PCI INPUTS and OUTPUTS Diagram ...
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Table 12 recommended operating conditions (see Figure 2) with LVdd = 3.3 V ± 0 Characteristic m 3 SCL/SDA rise time (from 0.5v to 2.4v) 4 Data hold time 5 SCL/SDA fall time (from 2.4 to ...
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Electrical and Thermal Characteristics Table 13. MPC107 Maximum FDR Hex Divider (Dec 1152, 1280 A, B, 2E, 2F, 30, 31 1536, 1792, 1920, 2048, 2560, 3072 C, D 2304, 2560 E, F, 32, 33, 34, ...
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Table 14 recommended operating conditions (see Figure 2) with LVdd = 3.3 V ± 0.3 V Num Characteristic 5 SCL/SDA fall time (from 2 0 Clock high time 7 Data setup time (MPC107 as ...
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Electrical and Thermal Characteristics 5 SCL VM 8 SDA DFFSR FILTER CLK SDA Note: DFFSR filter clock is the SDRAM_CLK/CPU_CLK clock times DFFSR value. VM SCL/SDA realtime 1 Delay VM SCL/SDA qualified Note: The delay is the local memory clock ...
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Table 15. PIC Serial Interrupt Mode AC Timing Specifications At recommended operating conditions (see Figure 2) with LVdd = 3.3 V ± 0.3 V Num Characteristic 4 Output hold time 5 S_FRAME, S_RST output valid time 6 S_INT input setup ...
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Electrical and Thermal Characteristics 1.4.2.7 IEEE 1149.1 (JTAG) AC Timing Specifications Table 16 provides the JTAG AC timing specifications for the MPC107 while in the JTAG operating mode. Table 16. JTAG AC Timing Specification (Independent of PCI_SYNC_IN) At recommended operating ...
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TCK TRST Figure 19. JTAG TRST Timing Diagram . TCK DATA INPUTS DATA OUTPUTS DATA OUTPUTS Figure 20. JTAG Boundary Scan Timing Diagram . TCK TDI, TMS TDO TDO Figure 21. Test Access Port Timing Diagram MOTOROLA MPC107 PCI Bridge/Memory ...
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Package Description 1.5 Package Description This section details the MPC107 package parameters and pin assignments and listings. 1.5.1 Package Parameters The MPC107 uses mm, 503 pin Plastic Ball Grid Array (PBGA) package. The plastic package ...
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Pin Assignments and Package Dimensions Figure 22 shows the top surface, side profile, and pinout of the MPC107, 503 PBGA package. MOTOROLA MPC107 PCI Bridge/Memory Controller Hardware Specifications Package Description 29 ...
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Package Description Figure 22. MPC107 Package Dimensions and Pinout Assignments 30 MPC107 PCI Bridge/Memory Controller Hardware Specifications MOTOROLA ...
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Pinout Listings Table 17 provides the pinout listing for the MPC107, 503 PBGA package. Signal Name Package Pin Number A[0–31] AE22, AE16, AA14, AE17, AD21, AD14, AD20, AB16, AB20, AB15, AA20, AD13, Y15, AE12, AD15, AB9, AB14, AA8, AC13, ...
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Package Description Table 17. MPC107 Pinout Listing (continued) Signal Name Package Pin Number TT[0–4] AD19,AC19,AB19,AA19,AA18 WT AC16 AD[31–0] N23, N21, M20, M21, M22, M24, M25, L20, L22, K25, K24, K23, K21, J20, J24, J25, H20, F24, E25, F21, E24, E22, ...
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Table 17. MPC107 Pinout Listing (continued) Signal Name Package Pin Number MDL[0–31] M5, L1, L2, K1, K3, J1, J2, H1, H2, H6, G2, G4, F4, G1, F2, E2, F14, F15, A16, F17, B16, A17, A18, A19, B18, E18, D19, F19, ...
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Package Description Table 17. MPC107 Pinout Listing (continued) Signal Name Package Pin Number PCI_SYNC_IN P20 PCI_SYNC_OUT P25 SDRAM_CLK [0–3] D14, D13, E12, E14 SDRAM_SYNC_IN E13 SDRAM_SYNC_OUT D12 HRESET AA23 HRESET_CPU AB21 MCP AE20 NMI AC25 QACK AE18 QREQ M4 SRESET ...
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Table 17. MPC107 Pinout Listing (continued) Signal Name Package Pin Number GND AA21, AB22, AC11, AC14, AC17, AC20, AC23, AC3, AC5, AC8, AD24, AE25, C12, C15, C18, C21, C23, C3, C6, C9, E3, F10, F16, F20, F23, F6, G11, G13, ...
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PLL Configuration cient to prevent unused inputs from floating. 11 This pin is affected by programmable PCI_HOLD_DEL parameter, see Section 1.4.2.4, “PCI Signal Output Hold Timing.” 12 This pin is an open drain signal. 13 This pin is a sustained ...
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PLL Power Supply Filtering The AVdd and LAVdd power signals are provided on the MPC107 to provide power to the peripheral logic/memory bus PLL and the SDRAM clock delay-locked loop (DLL), respectively. To ensure stability of the internal clocks, ...
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System Design Information The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and then returned to the PCI_SYNC_IN input of the MPC107. The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM ...
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The board designer can choose between several types of heat sinks to place on the MPC8245. There are several commercially available heat sinks for the MPC8245 provided by the following vendors: Aavid Thermalloy 80 Commercial St. Concord, NH 03301 Internet: ...
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System Design Information External Resistance Internal Resistance Printed-Circuit Board External Resistance Figure 24. C4 Package with Heat Sink Mounted to a Printed-Circuit Board For this PBGA package, heat is dissipated from the component via several concurrent paths. Heat is conducted ...
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Figure 25. Thermal Performance of Select Thermal Interface Material The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based upon high conductivity, yet adequate ...
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System Design Information Thermagon Inc. 4707 Detroit Ave. Cleveland, OH 44102 Internet: www.thermagon.com 1.7.6.2 Heat Sink Usage An estimation of the chip junction temperature θ where T = ambient temperature for the ...
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When a heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. ...
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Document Revision History 1.8 Document Revision History Table 19 provides a revision history for this hardware specification. Rev. No. 0.0 Preliminary release with some TBDs in the spec tables 0.1 Removed references to CBGA packaging. Removed references to BVdd = ...
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Table 19. Document Revision History (continued) Rev. No. 0.3 Removed references to the suspend (power-saving) mode. In Section 1.3, technology reference updated from 0.35 µm to 0.29 µm CMOS. Updated Figure 2 and Note 5 to indicate only HRESET must ...
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Ordering Information Table 19. Document Revision History (continued) Rev. No. 0.6 Updated Table 5 to include the maximum numbers. Corrected solder attach and ball information in Section 1.5 Sn/36 Pb/2 Ag. Table 17: Changed the voltage supply information ...
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Part Numbers Not Fully Addressed by This Document Table 21. Part Numbers Addressed by XPC107APXnnnWx series Part Number Specification (Document Order No. MPC107APXPNS/D) XPC nnn A Product Part Part Code Identifier Modifier XPC 107 A 1.9.3 Part Marking Parts ...
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Ordering Information 48 MPC107 PCI Bridge/Memory Controller Hardware Specifications MOTOROLA ...
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MOTOROLA MPC107 PCI Bridge/Memory Controller Hardware Specifications Ordering Information 49 ...