HD6437041F28 HITACHI, HD6437041F28 Datasheet
HD6437041F28
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HD6437041F28 Summary of contents
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... SuperH RISC engine On-Chip Supporting Modules Name Hitachi Micro Systems, Incorporated 1/24/97 SH7040 Series Application Note ...
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... All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document ...
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The SH7040, SH7041, SH7042, and SH7043 are high-performance microcomputers with a 32-bit SH-2 CPU core that uses a RISC (reduced instruction set computer) type instruction set, and comprehensive on-chip peripheral functions. On-chip peripherals include ROM, RAM, a 16-bit multifunction timer ...
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Section 1 Using the SH7040 Series Application Note 1.1 Application Note Organization.......................................................................................... Section 2 SH7040 Series On-Chip Supporting Modules 2.1 Pulse High and Low Width Measurement (MTU) ............................................................ 2.2 Pulse Output (MTU).......................................................................................................... 11 2.3 PWM 4-Phase Output (MTU) ........................................................................................... 2.4 ...
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... This Application Note describes the peripheral functions of the SH7040 Series by means of simple sample tasks. 1.1 Application Note Organization The on-chip I/O volume uses the layout shown in figure 1 to describe the use of the peripheral functions. On-chip I/O volume Figure 1 Application Note Organization Specifications Functions Used Operation Software Flowchart Program List Modules Arguments Internal Registers RAM HITACHI 1 ...
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... RAM Describes the labels and functions of the RAM used by the modules. Flowchart Describes the software that executes the sample task, using a general flowchart. Program List Shows a program list of the software that executes the sample task. 2 HITACHI ...
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... Pulse high- and low-level widths are measured as shown in figure 2-1-1, and stored in RAM 28.7 MHz operation, pulse high- and low-level widths 2.28 ms can be measured units. Pulse Pulse high-level width Figure 2-1-1 Pulse Width Measurement Timing MTU (Input Capture) Pulse low-level width HITACHI 3 ...
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... TIOC0A Inputs pulse to be measured TGR0A Detects counter value at rise and fall of pulse TGI0A Initiates pulse high- and low-level width measurement on rise and fall of pulse 4 HITACHI Timer control register 0 (Input capture clear specification) Edge detection and capture signal generation circuit (TGR0A) ...
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... Transfer TCNT0 value to TGR0A Software processing TGI0A processing 1. TGR0A value pulse low-level width 2. Set falling edge as detected edge Time Hardware processing 1. TGI0A generation 2. Transfer TCNT0 value to TGR0A Software processing TGI0A processing 1. TGR0A value pulse high-level width 2. Set rising edge as detected edge HITACHI 5 ...
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... Setting of timer value corresponding to pulse low-level width Pulse low-level width is calculated from following formula: Pulse low-level width (ns) = Timer value at 28.7 MHz operation) 6 HITACHI Label Function Assignment pwhlmn MTU initialization pwhl1 Initiated by TGI0A; measures pulse high- and low- level widths according to TGR0A value and sets result in RAM ø ...
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... This sample task does not use any RAM apart from the arguments. Note: The SH7040 header file name is used as the register label. Module Main routine Main routine Pulse high- and low-level width measurement Main routine Pulse high- and low-level width measurement Main routine HITACHI 7 ...
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... Flowchart 1. Main routine 8 HITACHI pwhlmn Set input capture A as ch0 counter clear source with T0.TCR0 Set rising edge as pulse detected edge with T0.TIOR0H Enable interrupts by TGI0A with T0.TIER Set TGI0A interrupt priority level of 15 with INCT.IPRD Enable pulse input from TIOC0A with PFCE ...
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... Pulse high- and low-level width measurement pwhl1 Clear interrupt request flag Rising edge detected? Set pulse width in low-level area Set falling edge as pulse detected edge with T0.TIOR0H RTE No Yes as pulse detected edge Set pulse width in high-level area Set rising edge with T0.TIOR0H HITACHI 9 ...
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... T0.TSR0 =0xfe; if(( T0.TIOR0H & 0x0f ) == 0x08) { pwh_hdata = T0.TGR0A; T0.TIOR0H |= 0x01 } else { pwh_ldata = T0.TGR0A; T0.TIOR0H &=0xfe; 10 HITACHI INCLUDE FILE PROTOTYPE RAM ALLOCATION (*(unsigned short *)0xffffe800) (*(unsigned short *)0xffffe802) MAIN PROGRAM /* timer clear input capture TGRA0 */ /* input capture rising edge TIOC0A */ /* initialize TGIOA0 */ ...
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... Pulse Output Specifications 1. Using MTU ch0, a 50% duty pulse of the specified cycle is output as shown in figure 2-2- 28.7 MHz operation, any output pulse cycle from 69 2.28 ms can be set. TIOC0A pin Pulse cycle 50% Figure 2-2-1 Example of Pulse Output MTU (Output Compare Match) 50% HITACHI 11 ...
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... Pin/Register Name Function Assignment TIOC0A Pulse output pin TCR0 Selects counter clear source and input clock TIOR0H Pulse output level setting TGR0A 1/2 pulse cycle setting 12 HITACHI (Toggle output setting) register 0A (TGR0A) Compare match 0A (TCNT0) Figure 2-2-2 MTU/ch0 Block Diagram Timer I/O control register 0H ...
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... Set 1/2 cycle in TGR0A 3. Start count operation Figure 2-2-3 Principles of Pulse Output Operation Hardware processing 1. TGR0A compare-match generation 2. Counter clear 3. High-level output from TIOC0A Software processing None Hardware processing 1. TGR0A compare-match generation 2. Counter clear 3. Low-level output from TIOC0A Software processing None HITACHI 13 ...
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... T0.TMDR0 Sets ch0 to normal mode 4. RAM Used This application example does not use any RAM apart from the arguments. Note: The SH7040 header file name is used as the register label. 14 HITACHI Label Function Assignment puls_out PFC and pulse output setting ø cycle ( ...
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... Flowchart 1. Main routine puls_out Set TIOC0A to output with PFCE.PECR2 Set counter clear source with T0.TCR0 Set compare-match 0A toggle output with T0.TIOR0H Set 1/2 pulse cycle in T0.TGR0A Set normal operation mode with T0.TMDR0 Enable ch0 count operation with TMRSH.TSTR HITACHI 15 ...
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... PFCE.PEIOR = 0x0001; PFCE.PECR2 = 0x0001; T0/TCR0 = 0x20; T0.TIOR0H = 0x03; T0.TGR0A = pul_cyc; T0.TCNT0 = 0x0000; T0.TMDR0 = 0xc0; TMRSH.TSTR = 0x01; while(1 HITACHI INCLUDE FILE PROTOTYPE RAM ALLOCATION (*(unsigned short *)0xffffe800) MAIN PROGRAM /* TIOC0A output */ /* TIOC0A output compare/match output */ /* compare/match clear of TGR0A */ /* start' 0' compare/match toggle output */ ...
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... A duty 100% can be set, with 1/65535 resolution. ch1 PWM cycle TIOC1A pin ch2 PWM cycle TIOC2A pin TIOC3A pin TIOC3C pin Figure 2-3-1 Example of PWM Output ch1 PWM cycle ch2 PWM cycle ch3 PWM cycle MTU (PWM Mode 1) ch2 PWM cycle ch3 PWM cycle HITACHI 17 ...
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... TGR2A/B) Comparator A Timer counters 1, 2 (TCNT1, 2) ch3 Timer general registers 3A/B/C/D (TGR3A/B/C/D) Comparator A Timer counter 3 (TCNT3) Figure 2-3-2 MTU/ch1, ch2, ch3 Block Diagram 18 HITACHI (Initial output setting) Timer I/O control register 1 (TIOR1) Compare-match 1A/B Output compare signal generator Timer control registers 1, 2 (TCR1, 2) (Counter clear source ...
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... PWM pulse output pins TIOC2A TIOC3A TIOC3C TCR1 Select ch1 to ch3 timer counter clear sources and input clocks TCR2 TCR3 TMDR1 Specify ch1 to ch3 operating in PWM mode 1 TMDR2 TMDR3 TGR1A PWM cycle settings TGR2A TGR3A TGR1B Duty value settings TGR2B TGR3B TGR3C TGR3D HITACHI 19 ...
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... Timer initialization • TCR1 setting • TGR1A/B, TGR2A/B, TGR3A/B/C/D setting • TIOR1, 2, 3H/L setting 3. Start count operation Figure 2-3-3 Principles of PWM Waveform Operation 20 HITACHI Hardware processing Change PWM output pin output level to high on compare-match generation Hardware processing Change PWM output pin Software processing ...
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... Pulse cycle (ns) = Timer value pul_duty1b Setting of timing for change of waveform output pul_duty2b from TIOC pin pul_duty3b pul_duty3c pul_duty3d Label Function Assignment pwm_1 PFC and PWM output setting ø cycle ( 28.7 MHz operation) Data Input/ Length Module Output 1 word Main Input routine HITACHI 21 ...
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... TGR3B T1.TMDR1 Set operating mode to PWM mode 1 T2.TMDR2 T3.TMDR3 4. RAM Used This application example does not use any RAM apart from the arguments. Note: The SH7040 header file name is used as the register label. 22 HITACHI Module Main routine ...
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... Set TCR counter clear sources in TGR1A, TGR2A, TGR3A Set pulse cycles in T1.TGR1A, T2.TGR2A, T3.TGR3A Set duty values in T1.TGR1B, T2.TGR2B, T3.TGR3B, T3.TGR3C, T3.TGR3D Set waveform output value with TIOR Set TMDR1 PWM mode 1 Enable ch1, ch2, ch3 count operation with TMRSH.TSTR HITACHI 23 ...
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... T3.TIOR3L = 0x21; T31.TCNT3 = 0x0000; T31.TGR3A = pul_cyc3; T31/TGR3B = pul_duty3b; T31.TGR3C = pul_duty3c; T31.TGR3D = pul_duty3d; T3.TMDR3 = 0xc2; TMRSH.TSTR = 0x46; while(1 HITACHI INCLUDE FILE PROTOTYPE RAM ALLOCATION (*(unsigned short *)0xffffe800) (*(unsigned short *)0xffffe802) (*(unsigned short *)0xffffe804) (*(unsigned short *)0xffffe806) (*(unsigned short *)0xffffe808) (*(unsigned short *)0xffffe80a) ...
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... The pulse high-level width is varied to generate variable-duty 7-phase PWM output as shown in figure 2-4- 28.7 MHz operation, any output PWM cycle from 69 2.28 ms can be set. TIOC0B pin TIOC0C pin TIOC0D pin TIOC1A pin TIOC1B pin TIOC2A pin TIOC2B pin Figure 2-4-1 Example of PWM Output PWM cycle MTU (PWM Mode 2) HITACHI 25 ...
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... Timer control registers 1, 2 (TCR1, 2) Timer general registers (respective duty values set for TGR0B to TGR2B) Comparator Timer counters 1, 2 (TCNT1, 2) Figure 2-4-2 Synchronous Clear Block Diagram 26 HITACHI Synchronous clear source generation Control logic Compare-match Clear Control logic Compare-match Clear ...
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... TIOC2B TSYR Synchronous operation of ch0 to ch2 TCR0 to TCR2 Select ch0 to ch2 timer counter clear sources and input clocks TGR0A PWM cycle setting TGR0B Duty value settings TBR0C TGR0D TGR1A TGR1B TGR2A TGR2B TMDR0 to TMDR2 Specify ch0 to ch2 operating in PWM mode 2 HITACHI 27 ...
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... Timer initialization • TCR0 setting • TGR0A/B/C/D, TGR1A/B, TGR2A/B setting • TIOR0H/L, TIOR1, 2 setting 3. Start count operation Figure 2-4-3 Principles of PWM Output (7-Phase) Operation Used for Sawtooth 28 HITACHI Hardware processing Change PWM output pin output level to high on compare-match generation Software processing None ...
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... Pulse cycle (ns) = Timer value pul_duty0b Setting of timing for change of waveform output pul_duty0c from TIOC pin pul_duty0d pul_duty1b pul_duty2a pul_duty2b Label Function Assignment pwm_2 PFC and PWM output setting ø cycle ( 28.7 MHz operation) Data Input/ Length Module Output 1 word Main Input routine HITACHI 29 ...
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... TGR1B T0.TMDR0 Set operating mode for each channel to PWM mode 2 T1.TMDR1 T2.TMDR2 4. RAM Used This application example does not use any RAM apart from the arguments. Note: The SH7040 header file name is used as the register label. 30 HITACHI Module Main routine ...
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... Set counter clear source to TGR0A with T0.TCR0, and set synchronous clear for T1.TCR1, T2.TCR2 Set pulse cycle in T0.TGR0A Set duty values in T0.TGR0B/C/D, T1.TGR1A/B, T2.TGR2/B Set waveform output value with TIOR Set TMDR0 PWM mode 2 Enable ch0, ch1, ch2 count operation with TMRSH.TSTR HITACHI 31 ...
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... T2.TCR2 = 0x60; T2.TIOR2 = 0x22; T2.TCNT2 = 0x0000; T2.TGR2A = pul_duty2a; T2.TGR2B = pul_duty2b; T2.TMDR2 = 0xc3; TMRSH.TSYR = 0x07; TMRSH.TSTR = 0x07; while(1 HITACHI INCLUDE FILE PROTOTYPE RAM ALLOCATION (*(unsigned short *)0xffffe800) (*(unsigned short *)0xffffe802) (*(unsigned short *)0xffffe804) (*(unsigned short *)0xffffe806) (*(unsigned short *)0xffffe808) (*(unsigned short *)0xffffe80a) ...
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... TIOC4C pin Pulse low-level width TIOC4B pin TIOC4D pin Duty = Figure 2-5-1 Example of Positive-Phase and Opposite-Phase PWM 3-Phase Pulse cycle Pulse high-level width Pulse high-level width Pulse high-level width Pulse high-level width 100 (%) pulse cycle Output Waveform MTU (Reset-Synchronized PWM Mode) HITACHI 33 ...
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... TCLKA/B Timer control register 3 (TCR3) (Compare-match A clear specification) Counter clear signal generator Timer start register (TSTR) (Count operation enabling) Figure 2-5-2 MTU/ch3, ch4 Block Diagram 34 HITACHI Synchronous setting Timer Timer general general register 4A register 3A (TGR4A) (TGR3A) Compare- match A Comparator A Timer counter ...
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... TIOC4B PWM output 3 TIOC4C PWM output 2 opposite-phase waveform TIOC4D PWM output 3 opposite-phase waveform TCR3 Selects ch3 timer counter clear source and input clock TMDR3 Specifies ch3 operating in reset-synchronized PWM mode TGR3A PWM cycle setting TGR3B Duty value settings TGR4A TGR4B HITACHI 35 ...
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... TCR3 setting • TOCR setting • TGR setting • TOER setting • TMDR setting 3. Start timer counter Figure 2-5-3 Principles of Reset-Synchronized PWM Waveform Output Operation 36 HITACHI Hardware processing Toggle output each time TGR3B, TGR4A, or TGR4B compare-match or timer counter clear occurs Software processing None ...
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... Setting of timer counter value that causes high-level output from TIOC4B/D T3.TOER Reset-synchronized PWM output enable setting T3.TMDR3 Reset-synchronized PWM mode setting Label Function Assignment rst_pwm PFC and PWM output setting ø cycle ( 28.7 MHz operation) Data Input/ Length Module Output 1 word Main Input routine Module Main routine HITACHI 37 ...
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... RAM Used This application example does not use any RAM apart from the arguments. Note: The SH7040 header file name is used as the register label. 38 HITACHI ...
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... Set enabling of toggle output synchronized with PWM cycle, and positive-phase and opposite-phase output levels, with T3.TOCR Set pulse cycle in T31.TGR3A Set duty values in T31.TGR3B, T3.TGR4A/B Enable reset-synchronized PWM output with T3.TOER Set reset-synchronized PWM mode with T3.TMDR3 Enable ch3 count operation with TMRSH.TSTR HITACHI 39 ...
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... T31.TGR3B =pul_duty3b; T31.TCNT4 = 0x0000; T31.TGR4A = pul_duty4a; T31.TGR4B = pul_duty4b; T3.TOER = 0xff; T3.TOCR = 0x43; T3.TMDR3 = 0xc8; TMRSH.TSTR = 0x40; while(1 HITACHI INCLUDE FILE PROTOTYPE RAM ALLOCATION (*(unsigned short *)0xffffe800) (*(unsigned short *)0xffffe802) (*(unsigned short *)0xffffe804) (*(unsigned short *)0xffffe806) MAIN PROGRAM /* TIOC3B/D,TIOC4A/B/C/D output */ /* TIOC3B/D,TIOC4A/B/C/D output */ ...
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... Toggle waveform output is performed in synchronization with the cycle 28.7 MHz operation, any output pulse cycle from 69 2.28 ms can be set. TIOC3A pin TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin Figure 2-6-1 Complementary PWM 3-Phase Output Waveform MTU (Complementary PWM Mode) 100 (%) Cycle Non-overlap time HITACHI 41 ...
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... TGR4A/B) When TGR4B is set Timer general registers 3B, 4A/B (TGR3B, TGR4A/B) Figure 2-6-2 MTU/ch3, ch4 Block Diagram 2. Table 2-6-1 shows the function assignments for this task. MTU functions are assigned as 42 HITACHI Timer output Timer mode master enable register 3 register (TOER) (TMDR3) (TCNT3, 4) ...
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... TGR3A Setting of 1/2 PWM cycle + dead time value TGR3C TGR3A buffer register TGR3B Output pulse turning point setting (compare register) TGR4A TGR4B TGR4C TGR4A buffer register TGR4D TGR4B buffer register TDDR Dead time setting TCDR 1/2 cycle setting TCBR TCDR buffer register HITACHI 43 ...
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... Set non-overlap period with TDDR 7. Set TCNT4 upper limit with TCBR, TCDR 8. Enable TIOC4B/D pin output 9. Set complementary PWM mode 10. Start count operation Figure 2-6-3 Principles of Complementary PWM Single-Phase Waveform 44 HITACHI TCNT3 TCNT4 Hardware processing 1. Compare-match generation 2. Pulse output Software processing None Hardware processing 1 ...
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... However, generation of a compare-match at which the output waveform is set to the active level (compare-match (1) or (3)) occurs only after the generation of a compare at which the respective output waveform is set to the positive level (compare-match (4) or (2)). Tb1 TGR3A TCDR TDDR H'0000 Figure 2-6-4 Principles of Operation of PWM Waveform Output Method Ta Tb2 (3) (4) Area (a) Ta Tb1 (1) (2) Area (b) HITACHI 45 ...
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... Set non-overlap period with TDDR 7. Set TCNT4 upper limit with TCBR, TCDR 8. Enable TIOC4B/D pin output 9. Set complementary PWM mode 10. Start count operation Note: * This processing also occurs with 3-phase output when data is set in TGR4D. Figure 2-6-5 Principles of Complementary PWM Single-Phase Waveform 46 HITACHI Ta Tb1 Ta TCNT3 TCNT4 A ...
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... Set TCNT4 upper limit with TCBR, TCDR 9. Enable TIOC3A/B/D, TIOC4A/B/C/D pin output 10. Set complementary PWM mode 11. Start count operation Figure 2-6-6 Principles of PWM Waveform Output Operation TCNTS TCNT3 TCNT4 Hardware processing TGR3A compare-match interrupt generation Software processing 1. Set RAM contents in buffer register HITACHI 47 ...
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... Set non-overlap period with TDDR 8. Set TCNT4 upper limit with TCBR, TCDR 9. Enable TIOC4B/D pin output 10. Set complementary PWM mode 11. Start count operation Figure 2-6-7 Principles of Toggle Waveform Output Operation Synchronized 48 HITACHI TCNT3 TCNT4 Hardware processing TGR3A compare-match generation 1. Toggle output of PWM waveform ...
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... PWM carrier cycle register value setting dead_time Non-overlap period setting Label Function Assignment comple Complementary PWM output setting setdata Sets waveform change timing in buffer register ø cycle ( 28.7 MHz operation) Data Input/ Length Module Output 1 word Main Input routine Main routine Data setting HITACHI 49 ...
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... INTC.IPRE Sets TGI0A compare-match interrupt priority level RAM Used This application example does not use any RAM apart from the arguments. Note: The SH7040 header file name is used as the register label. 50 HITACHI Module Main routine Main routine Data setting Main routine ...
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... PWM cycle, and positive-phase and opposite-phase output levels, with T3.TOCR Enable complementary PWM output in TOER Set complementary PWM mode with T3.TMDR3 Enable TGI3A interrupt with T3.TIER3 Set TGI0A interrupt priority level to 15 with INTC.IPRE Enable ch3, ch4 count operation with TMRSH.TSTR HITACHI 51 ...
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... T31.TSR3 &= 0xfe; T31.TCBR = c_cyc; T31.TGR3C = pul_cyc1; T31.TGR3D = pul_duty3d; T31.TGR4C = pul_duty4c; T31.TGR4D = pul_duty4d HITACHI INCLUDE FILE PROTOTYPE RAM ALLOCATION (*(unsigned short *)0xffffe800) (*(unsigned short *)0xffffe802) (*(unsigned short *)0xffffe804) (*(unsigned short *)0xffffe806) (*(unsigned short *)0xffffe808) (*(unsigned short *)0xffffe80a) MAIN PROGRAM ...
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... The initial value of the timer counter is H'0000, and counting can be performed from –2147483648 to 2147483647 using a software counter. Measurement time 1 Measurement time 2 TCLKA pin External clock TCLKB pin input Figure 2-7-1 2-Phase Encoder Counter Latching MTU (Phase Counting Mode) TCNT0 TCNT1 Counting up Counting down HITACHI 53 ...
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... Clock ø/2 selection ø/4 circuit ø/8 Timer I/O control register 0H (TIOR0H) (Detected edge specification) General register 0B (TGR0B) 54 HITACHI General register 0A (TGR0A) Compare-match 0A (TGI0A) Comparator A Timer counter 0 (TCNT0) Compare-match 0C (TGI0C) Comparator C General register 0C (TGR0C) Timer control register 0 (TCR0) (Input capture clear specification) ...
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... Timer general register 1A (TGR1A) Timer general register 1B (TGR1B) Figure 2-7-3 MTU/ch1 Block Diagram Input capture interrupt A/B (TIOC1A/B) (Phase counting mode setting) Timer mode register 1 (TMDR1) Timer counter 1 (TCNT1) Clock TCLKA pin selection TCLKB pin circuit Overflow/underflow interrupt (TCIU1, TCIV1) Overflow/underflow signal generator HITACHI 55 ...
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... Set to 2 every measurement interval TMDR1 Phase counting mode setting TCR1 Counter clock and counter clear source selection TIOR0 Sets TIOC0A/C to input capture on generation of ch1 output compare TIER1 Enables TGI1A/B, TIOU1, TIOV1 interrupts TGR1A Holds input capture A count result TGR1B 56 HITACHI ...
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... Set phase counting mode 2. Start count operation Figure 2-7-4 Principles of Phase Counting Mode Operation (1) Hardware processing Hardware processing 1. TCNT1 1. TCNT1 incrementing decrementing Software processing Software processing None None Time Hardware processing 1. TIOU1 generation Software processing TIOU1 handling 1. Software down-count due to underflow HITACHI 57 ...
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... Set phase counting mode 5. Set input capture signal to ch1 output compare 6. Enable input capture A, input capture B, and overflow/underflow interrupts 7. Enable count operation Figure 2-7-5 Principles of Phase Counting Mode Operation (2) 58 HITACHI Hardware processing 1. TGI1A generation 2. TGI1B generation Software processing TGI1A/B handling 1. Store count result in RAM ...
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... Initiated by TGI1B; sets up/down-count result in RAM from TGRB value Initiated by TIOV1; increments software counter Initiated by TIOU1; decrements software counter Data Length Word ø cycle (35 ns Longword Word Input/ Module Output Main routine Input Counter value Output measurement 1 Counter value measurement 2 Counter value measurement 1 HITACHI 59 ...
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... RAM Used Module Label Counter value wrk measurement 1, 2 All modules cnt Note: The SH7040 header file name is used as the register label. 60 HITACHI Function Assignment Used as work area when setting data Software counter Module Main routine Counter value measurement 1 Main routine ...
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... Set TIOC1A/B to input capture operation with T1.TIOR1 Set counter measurement times with T0.TGR0A/C Enable interrupts with T1.TIER1 Set interrupt priority level to 15 with INTC.IPRD Enable pulse input from TCLKA/B pins Set phase counting mode with T1.TMDR1 Enable ch0/1 count operation HITACHI 61 ...
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... Counter value measurement 1 phacnt1 Clear interrupt request flag ch1 down-count? Set ch1 count result in RAM Set pulse width in RAM RTE 62 HITACHI No Yes Set ch1 count result in RAM ...
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... Counter value measurement 2 phacnt2 Clear interrupt request flag ch1 up-count? Set ch1 count result in RAM RTE No Yes Set ch1 count result in RAM HITACHI 63 ...
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... Overflow 5. Underflow 64 HITACHI ovf1 Clear interrupt request flag Increment software counter RTE ovf1 Clear interrupt request flag Increment software counter RTE ...
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... TIOC0A */ /* input capture TIOC0B */ /* output compare TIOC0C */ /* input capture TIOC1A interrupt TIOC1A,TIOC1B,TCIU1,TCIV1 */ /* set position cycle */ /* set speed cycle */ /* set interrupt level= set imask level TIOCnx sellect */ /* set phase counting mode1 */ /* TGRB and TGRD buffer mode */ /* start timer0 loop */ */ */ */ */ HITACHI 65 ...
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... T0.TGR0D; } void phacnt2(void) { T1.TSR1 &= 0xfd; wrk = T1.TGR1A; if(cnt<0) cnt_data2 = (unsigned long)wrk-0x010000+cnt*0x010000; /* set po */ else cnt_data2 = (unsigned long)wrk+cnt*0x010000 HITACHI /* clear flag */ /* count clear flag */ /* count down */ /* clear flag */ /* count< set set width pulse */ /* clear flag */ /* set po */ ...
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... External signal POE0 pin TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin Figure 2-8-1 Example of Externally Triggered Timer Waveform Cutoff Timer output MTU, POE High-impedance state HITACHI 67 ...
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... Timer start register (TSTR) (Count operation enabling) POE Input level control/status register (POE input mode setting) POE0 pin Input level detection circuit Figure 2-8-2 MTU/ch3, ch4, POE Block Diagram 68 HITACHI Synchronous setting Timer Timer general general register 4A register 3A (TGR4A) (TGR3A) Compare- ...
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... Selects ch3 timer counter clear source and input clock TMDR3 Sets ch3, ch4 to reset-synchronized PWM mode TGR3A PWM cycle setting TGR3B Output waveform change timing setting TGR3C TGR3D TGR4A TGR4B TOER Enables/disables TIOC3B/D, TIOC4A/B/C/D pin timer output ICSR POE input mode selection HITACHI 69 ...
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... TGR3B, TGR4A, TGR4B 4. Enable TIOC3B/D, TIOC4A/B/C/D pin output 5. Set waveform cutoff on falling edge of POE0 6. Start count operation Figure 2-8-3 Principles of Externally Triggered Timer Waveform Cutoff Operation 70 HITACHI Timer output Hardware processing 1. High-impedance output from TIOC3B/D, TIOC4A/B/C/D pins Software processing ...
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... Setting to high-impedance output synchronized with falling edge of POE0 pin input signal FPCE.PEIOR Sets TIOC3B/D, TIOC4A/B/C/D pins to output FPCE.PECR1 Sets TIOC3B/D, TIOC4A/B/C/D pins to MTU output Label Function Assignment down DC motor control waveform generation Data Input/ Length Module Output 1 word Main routine Input Module Main routine HITACHI 71 ...
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... RAM Used This sample task does not use any RAM apart from the arguments. Note: The SH7040 header file name is used as the register label. 72 HITACHI ...
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... PWM cycle, and positive-phase and opposite-phase output levels, with T3.TOCR Set pulse cycle in T31.TGR3A Set duty values in T31.TGR3B, T31.TGR4A/B Set reset-synchronized PWM mode with TMDR Set TIOC3B/D, TIOC4A/B/C/D pins to MTU output with T31.TOER Enable ch3 count operation with TMRSH.TSTR HITACHI 73 ...
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... T3.TMDR3 = 0xc8; T31.TGR3A = cycle; T31.TGR3B = duk1; T31.TGR4A = duk2; T31.TGR4B = duk3; T3.TOER = 0xff; TMRSH.TSTR = 0xc0; while(1 HITACHI INCLUDE FILE PROTOTYPE RAM ALLOCATION MAIN PROGRAM /* stop timer POE0 falling edge */ /* set output level */ /* TIOCnx sellect */ /* timer clear input capture TGRA0 */ /* input capture riseing edge TIOC0A */ ...
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... PWM output. TIOC0A pin Feedback TIOC0B pin input TIOC0C pin TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin Figure 2-9-1 Example of DC Brushless Motor Control Signal Output MTU (Gate Control Register) Chopping output HITACHI 75 ...
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... Counter clear signal generator Timer start register (TSTR) (Count operation enabling) (DC motor control waveform output enabling) Timer gate control register TIOC0A/B/C pins Gate output circuit Figure 2-9-2 MTU/ch3, ch4 Block Diagram 76 HITACHI Synchronous setting Timer Timer general general register 4A register 3A (TGR4A) (TGR3A) Compare- ...
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... Selects ch3 timer counter clear source and input clock TMDR3 Sets ch3, ch4 to reset-synchronized PWM mode operation TGR3A PWM cycle setting TGR3B Output waveform change timing setting TGR3C TGR3D TGR4A TGR4B TOER Enables/disables TIOC3B/D, TIOC4A/B/C/D pin timer output TGCR Enables/disables DC motor control waveform output HITACHI 77 ...
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... TGR3B, TGR4A, TGR4B 4. Enable TIOC3B/D, TIOC4A/B/C/D pin output 5. Enable DC motor control gate signal output 6. Start count operation Figure 2-9-3 Principles of DC Motor Control Signal Output Operation 78 HITACHI Hardware processing 1. Output gate signals to TIOC3B/D, TIOC4A/B/C/D pins on rising/falling edge of TIOC0A/B/C 2 ...
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... Setting of timing for change of waveform output from TIOC4B, TIOC4D T3.TOER Sets TIOC3B/D, TIOC4A/B/C/D pins to MTU output T3.TMDR3 Reset-synchronized PWM mode setting T3.TGCR Enables DC motor control waveform output Label Function Assignment dc_3out DC motor control waveform generation Data Input/ Length Module Output 1 word Main routine Input Module Main routine HITACHI 79 ...
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... RAM Used This sample task does not use any RAM apart from the arguments. Note: The SH7040 header file name is used as the register label. 80 HITACHI ...
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... T3.TOCR3 Set pulse cycle in TGR3A Set duty values with T31.TGR3B, T31.TGR4A/B Set TIOC3B/D, TIOC4A/B/C/D pins to MTU output with TOER Set reset-synchronized PWM mode with T3.TMDR Enable DC motor control output with TGCR Enable ch3 count operation with TSTR HITACHI 81 ...
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... T31.TGR3A = cycle; T31.TGR3B = duk1; T31.TGR4A = duk2; T31.TGR4B = duk3; T3.TOER = 0xff; T3.TGCR = 0x70; TMRSH.TSTR = 0xc1; while(1 HITACHI INCLUDE FILE PROTOTYPE RAM ALLOCATION MAIN PROGRAM /* set output level */ /* TIOCnx sellect */ /* timer clear input capture TGRA0 */ /* timer clear input capture TGRA3 */ /* set output level */ ...
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... Input voltage ch0 Input voltage ch1 Input voltage ch2 Input voltage ch3 Input voltage ch4 Input voltage ch5 Input voltage ch6 Input voltage ch7 Figure 2-10-1 Block Diagram of Voltage Measurement by SH7040 DTC (Block Transfer), A/D Converter AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 HITACHI 83 ...
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... A function for starting A/D conversion upon MTU compare-match without software intervention • A function for automatically outputting pulses by hardware without software intervention (output compare) TIOC0A (A/D start source) A/D converter Figure 2-10-2 SH7040 ch0 Block Diagram 84 HITACHI ch0 Control logic Timer interrupt enable register 0 (TIER0) Timer I/O control register 0H (TIOR0H) Timer general register 0A (TGR0A) Comparator ...
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... A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D data register E (ADDRE) A/D data register F (ADDRF) A/D data register G (ADDRG) A/D data register H (ADDRH) ADI (DTC activation source) + A/D TIOC0A – conversion (A/D activation source) control circuit A/D control register (ADCR) DTC MTU/ ch0 HITACHI 85 ...
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... A/D ADI (DTC activation source) converter DTC source address register (DTSAR) DTC transfer count register A (DTCRA) Transfer data Figure 2-10-4 SH7040 DTC Block Diagram 86 HITACHI (DTMR) DTC controller Bus controller Internal address/data bus DTC information base register (DTBR) DTC enable register C (DTEC) DTC destination address ...
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... ADDRA to ADDRH Store A/D conversion results DTMR Sets DTC to block transfer mode DTCRA Transfer number specification DTCRB Block length specification DTSAR Transfer source address setting DTDAR Transfer destination address setting DTBR DTC vector upper 16 bit setting DTEC Enables DTC activation at end of A/D conversion HITACHI 87 ...
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... Set block transfer mode as DTC transfer mode • Set DTC activation by A/D end interrupt • Set transfer conditions 4. Start count operation Figure 2-10-5 Principles of Pulse Width Measurement Operation 88 HITACHI Hardware processing 1. Execute A/D conversion for AN0–AN7 2. Store conversion results sequentially in ADDRA–ADDRH ...
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... Table 2-11-2 Register Information Address Register Name RF DTC mode register (DTMR) RF+2 DTC transfer count register A (DTCRA) RF+6 DTC transfer count register B (DTCRB) RF+8 DTC source address register (DTSAR) RF+12 DTC destination address register (DTDAR) RF: Register information start address Data Length Word Word Word Longword Longword HITACHI 89 ...
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... Register DTC information information base register (DTBR) start address upper 16 bits Figure 2-10-6 Principles of the DTC Activated Operation 90 HITACHI DTC vector + address lower 16 bits DTC vector table RF RF+1 RF+2 RF+3 RF+4 RF+5 RF+6 RF+7 Register RF+8 information RF+9 RF+10 RF+11 RF+12 RF+13 RF+14 RF+15 RF+16 ...
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... Each 10-bit conversion result is set as follows: Upper byte Lower byte AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Label Function Assignment adscan Setting of A/D converter activation by MTU and DTC activation at end of A/D conversion Data Length Module Longword Main routine AD9 AD8 HITACHI 91 Input/ Output Input ...
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... Enables pulse input from TIOC0A INTC.IPRG Sets A/D conversion end interrupt level RAM Used This sample task does not use any RAM apart from the arguments. Note: The SH7040 header file name is used as the register label. 92 HITACHI Module Main routine — Main routine ...
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... Set transfer source address • Set transfer destination address Set upper 16 bits of DTC vector with DTC.DTBR Enable DTC activation on generation of A/D conversion end interrupt with DTC.DTEC Set ADI interrupt priority level to 15 with INTC.IPRG Enable ch0 count operation with TMRSH.TSTR HITACHI 93 ...
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... TMRSH.TSTR = 0x01; while(1); } Note: Set the lower 16 bits of the register information start address in DTC vector table address 0x422 (vector when DTC activation condition is A/D conversion end). 94 HITACHI INCLUDE FILE PROTOTYPE RAM ALLOCATION MAIN PROGRAM /* timer clear output compare TGR0A */ /* interrupt TGI00A */ ...
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... Console TX RX Figure 2-11-1 Block Diagram of SCI Transfer of RAM Data by SH7040 RDR Figure 2-11-2 Data Transfer Using DMAC (Transfer Source Direct Address) RS-232C level conversion RXD TXD SCI, DMAC RDR DMA transfer RAM TDR DMA transfer Address 1 Address 2 4 bytes Address 3 Address 4 HITACHI 95 ...
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... Table 2-11-2 DMAC Transfer Conditions in SCI Transmission (RAM Condition DMAC channel Transfer source Transfer destination Number of transfers Transfer source address Transfer destination address Transfer request source Bus mode Transfer unit 96 HITACHI DMAC Temporary 4 bytes buffer Address Description Channel 0 On-chip SCI channel 0 On-chip RAM 4 ...
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... Serial status register (SSR) Transfer rate generation Baud rate generator Baud rate register (BRR) Figure 2-11-4 SCI Transmission Block Diagram Transmit shift register (TSR) Transmission/reception control circuit Transmit data register (TDR) Holds transmit data Transmit-data-empty interrupt (TEI) TXD pin (serial output) DMAC/ ch3 HITACHI 97 ...
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... A function that generates an interrupt on completion of reception (RXI interrupt) Holds receive data Receive data register (RDR) RXD pin (serial input) Receive shift register (RSR) Figure 2-11-5 SCI Reception Block Diagram 98 HITACHI Interrupt setting Receive mode setting Serial control register (SCR) Asynchronous mode setting Serial communication format setting ...
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... Transfer source block Figure 2-11-6 DMA/ch0 Block Diagram DMAC0 Transfer number setting DMA DMA transfer operation register count register 0 (DMAOR) DMA control Transfer destination address setting Bus DMA destination controller address register 0 Internal address/data bus (TCR0) DEI0 (DAR0) Transfer destination block HITACHI 99 ...
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... TEI (DMA3 activation source) SCI Transfer source address setting DMA source address register 3 Transfer source block Figure 2-11-7 DMA/ch3 Block Diagram 100 HITACHI DMAC3 DMA operation register (DMAOR) DMA control Bus controller (SAR3) Internal address/data bus Transfer number setting DMA transfer ...
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... RXD Data receive pin TXD Data transmit pin SMR SCI transmission format setting SCR SCI interrupt enabling/disabling setting SSR Interrupt status setting RDR Holds receive data from console TDR Holds transmit data to be sent to console BRR Transfer rate setting HITACHI 101 ...
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... Hardware processing 1. Store RDR contents in RAM 2. Increment transfer destination address Software processing None Figure 2-11-8 Principles of Data Transfer Operation Using SCI 102 HITACHI Data 4 Data 1 Hardware processing 1. Store RDR contents in RAM 2. Generate DEI0 Software processing 1. Enable transmit-data-empty ...
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... Initiated by DEI3; re-sets transfer source and destination addresses and number of transfers Disables transmit-data-empty interrupt requests Data Length Longword Input/ Module Output Main routine Input Module Main routine Main routine Main routine Receive data transfer Main routine Main routine Transmit data transfer HITACHI 103 ...
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... RAM Used Label Function lk_addr Stores RAM reference address Note: The SH7040 header file name is used as the register label. 104 HITACHI Data Length Module Unsigned long Main routine ...
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... Set transfer source address and transfer destination address with DM0.SCR0/DM0.DCR0 Set transfer method with DM0.TCR0/DM0.CHCR0 Set transfer source address and transfer destination address with DM3.SCR3/DM3.DCR3 Set transfer method with DM3.TCR3/DM3.CHCR3 Activate DMAC with DMAC.DMAOR Set interrupt priority levels to 15/10 with INTC.IPRC/IPRF HITACHI 105 ...
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... Receive data transfer 3. Transmit data transfer 106 HITACHI dma_rdr Clear interrupt request flag Enable transmit interrupts, transmit operation Set transfer source address, number of transfers Clear interrupt request flag RTE dma_tdr Clear interrupt request flag Enable receive interrupts, receive operation Set transfer destination ...
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... HITACHI 107 ...
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... DM3.TCR3 = 0x01; DM3.CHCR3 I= 0x00000001; } void dma_tdr(void) { DM3.CHCR3 &= 0xfffffffc; SCI0.SCR0 = 0x70; DM0.DAR0 = (long)(&dat.addr0); DM0.TCR0 = 0x04; } 108 HITACHI /* clear flag */ /* interrupt transmit sci,transmit enabled */ /* source address:RAM */ /* transmit count clear flag */ /* clear flag */ /* interrupt receive sci,receiving enabled */ /* distination address:SCI transmit register */ /* transmit count:4 */ ...
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... interrupt priority register interrupt priority register interrupt priority register interrupt controll register */ /* IRQ status register */ /* user break address register user break address register user break mask register user break mask register user break bus cycle register */ */ */ */ */ */ HITACHI 109 ...
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... WCR1; short WCR2; short res2; short DCR; short RTCSR; short RTCNT; short RTCOR; }; #define BSC (*(volatile struct bsc *)0xffff8620) 110 HITACHI /* enable register enable register enable register enable register enable register control/status register */ /* information base register */ /* cash control register */ /* bus control register 1 */ ...
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... HITACHI 111 ...
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... TSR2; short TCNT2; short TGR2A; short TGR2B; }; #define T2 (*(volatile struct timer2 *)0xffff82a0) /*----------------------------------------------------------------------*/ /* MTU CH3,4 112 HITACHI /* timer controll register timer mode register timer i/o controll register timer i/o controll register timer interrupt enable register timer stasus register timer counter timer general register 0A */ ...
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... HITACHI 113 ...
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... ADDRE; short ADDRF; short ADDRG; short ADDRH; }; #define A_D (*(volatile struct a_d *)0xffff83e0) #define A_D0 (*(volatile struct a_d0 *)0xffff83f0) 114 HITACHI /* serial mode register bit-rate register sirial contorol register transmit data register sirial status register receive data register serial mode register 1 */ ...
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... I/O register */ /* portC I/O register */ /* portB contorol register portB contorol register portC contorol register */ /* portD data register portD data register portD I/O register portD I/O register portD contorol register portD contorol register portD contorol register portE data register portF data register */ /* portE I/O register */ */ */ HITACHI 115 ...
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... PFCE (*(volatile struct pfce *)0xffff83B0) #define PFC0 (*(volatile struct pfc0 *)0xffff83C8) /*----------------------------------------------------------------------*/ /* POE /*----------------------------------------------------------------------*/ volatile struct poe { short ICSR; short OCSR; }; #define POE (*(volatile struct poe *)0xffff83c0) 116 HITACHI /* portE contorol register portE contorol register IRQOUT contorol register */ /* input-level contorol status register */ /* output-level contorol status register */ */ ...
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... SH7040 Series On-Chip Supporting Modules Application Note Publication Date: 1st Edition, September 1996 Published by: Semiconductor and IC Div. Hitachi, Ltd. Edited by: Technical Documentation Center Hitachi Microcomputer System Ltd. Copyright © Hitachi, Ltd., 1996. All rights reserved. Printed in Japan. ...