IDT77V012L155DA ETC, IDT77V012L155DA Datasheet
IDT77V012L155DA
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IDT77V012L155DA Summary of contents
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IDT77V012 % ...
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IDT77V012 ...
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IDT77V012 TCLAV 128 I TENB 123 O TxLED 124 O TCLK 125 ...
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IDT77V012 ADDR[ ADDR[ ADDR[ ...
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IDT77V012 DATA[5] 31 I/O DATA[6] 32 I/O DATA[7] 33 I/O DATA[8] 34 ...
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IDT77V012 $ ...
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IDT77V012 ' ' ' ' ...
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IDT77V012 Cells can be dropped on the Rx UTOPIA interface by setting the RxData Cell Filter bit of the Configuration 2 register. This option is to prevent cells from reaching the switch when the 77V012 is in software reset, but ...
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IDT77V012 TCLK (output) TCLAV (input (output) TSOC (output) TxDATA[7:0] (output) TCLK (output) TCLAV (input (output) TSOC (output) TxDATA[7:0] 49 (output ...
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IDT77V012 ' ...
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IDT77V012 DTxCLK (output) DTxFRM (input) DTxDATA[3:0] 104 105 (input) DTxCLK (output) DTxFRM (input) DTxDATA[3:0] (input ADDR[2:0] Tx TAG Size ...
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IDT77V012 ...
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IDT77V012 active low signal used as an enable to read data from an addressed location on the AD[7:0] bus active low signal used as an enable to write data to an addressed location on ...
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IDT77V012 EEPROM Mux Select indicates whether the EEPROM pins will be connected to the In-Stream™ logic the EEPROM registers. When connected to the In-Stream™ logic 32-bytes of data are read from the EEPROM if a Discovery/Identify command is ...
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IDT77V012 Rx TAG and 8006 6 Init from Mode Select EEPROM 1 64K x 32 13K 1 128K x 32 16K 1 256K x 32 16K 1. Best case conditions are limited by the Result Node, which uses a memory ...
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IDT77V012 $ $ $ $ ...
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IDT77V012 12-bit VPI Lookup Search Table (one level of search) 4095 {SO [5:0]; VPI [11:0]} 31:30 18:17 16: 1-bit 2-bits {RNO [1:0]; TLN [15:1];RB [0]} 31 Tunneling Node (TN) - 32-bit field returned from the first level of ...
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IDT77V012 {SO [5:0]; VPI [11:0]} 31:30 18:17 16:15 TB 1-bit 2-bits 31 Result Bit (RB) - 2-bit field indicating what 32-bit entry the Result Node pointer is pointing to points to the TAG, RB=01 points to the ...
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IDT77V012 {SO [5:0]; VPI [11:0]} 31 18:17 16:15 STO 2-bits 64K 01 64K 10 64K 11 64K 256Kx32-bit SRAM 18-bit address used for first level of search 0 RN STN 16-bits Search Offset (SO) - 6-bit offset ...
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IDT77V012 Get next two bits of VCI = [SB0,SB1] and overwrite LSB (bit with SB0 31 16-bit address Get next two bits of VCI = [SB0,SB1] and overwrite LSB (bit 0) of NTN with SB0 31 16-bit ...
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IDT77V012 {RNO[1:0]; LN[15:1]; RB[0 64K 01 64K 10 64K 11 64K 256Kx32-bit SRAM { ...
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IDT77V012 4 Null Counting On 5 Search GFC 6 Search PT/CLP Pass All Cells Configuration 2 8002 0 Insert New Header 1 Overwrite GFC Overwrite PT/ CLP Table Offset 8003 5:0 Search ...
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IDT77V012 UTOPIA Rx Cell 801E [7:0] Rx Cell Counter Byte 3 Counter [31:24] UTOPIA Rx Cell 801F [7:0] Rx Cell Counter Byte 2 Counter [23:16] UTOPIA Rx Cell 8020 [7:0] Rx Cell Counter Byte 1 Counter [15:8] UTOPIA Rx Cell ...
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IDT77V012 ...
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IDT77V012 In-Stream™ 8015 [7:0] In-Stream™ TAG TAG Byte 0 [7:0] OC-3 ATM PHY UTOPIA 1 Header Payload Configuration 2 8002 4 Tx Move PT/CLP Pin Control 8004 0 Override Pin Control Tx TAG 8005 [2:0] Tx Tag ...
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IDT77V012 OC-3 ATM PHY Header SRAM IDT71V633 SWITCHStAR Header IDT77V400 Xlater & IDT77V012 IDT77V500 UTOPIA 1 4-bit DPI Payload TAG New Header Payload Figure 25 Receive Tag Routing Diagram ADSL PHY DPI to ADSL PHY UTOPIA 2 ...
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IDT77V012 ...
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IDT77V012 The first five bytes contain the cell header. The In-Stream™ programming cell address is in the first 28-bits with the default value of GFC =0x0, VPI =0x0, VCI =0x001F, PT/CLP =0xX, where X=don't care. The remaining byte is the ...
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IDT77V012 Rx TAG and 8006 5 In-Stream™ Mode Select Direction In-Stream™ Cell 800E [7:0] In-Stream™ Header Byte 0 Header [31:24] In-Stream™ Cell 800F [7:0] In-Stream™ Header Byte 1 Header [23:16] In-Stream™ Cell 8010 [7:0] In-Stream™ Header Byte 2 Header [15:8] ...
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IDT77V012 Command Cell Transaction ID (two byte field) Bit Copied from Command Cell Copied from Command Cell Figure 28 Valid Transaction Field Formats for In-Stream Figure 29 Valid Message Type Field Format for In-Stream Discovery/Identify ...
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IDT77V012 Read/Write Command Cell Message Data and/or Padding Field (36 byte field) Bit Number of valid bytes Base address Base address Base address Data and/or padding Data and/or padding Figure 31 Valid Message and/or Data ...
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IDT77V012 7:6 Not Used 5 Tx Null Pointer Error 4 Tx Time Out 3 Rx Null Pointer Error 2 Rx Time Out 1 PHY Interrupt Status 0 PHY Time Out Pin Control 8004 1 Control A 2 Control B $ ...
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IDT77V012 t Address to ALE Falling Edge Setup Time AAL t Address to ALE Falling Edge Hold Time ALA t Data to rising edge of RD Setup Time DRS t Data to rising edge of RD Hold Time DRH t ...
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IDT77V012 SYSCLK SYSCLK RCLK Figure 34 System Clock to UTOPIA Receive Clock Propagation Delay SYSCLK TCLK Figure 35 System Clock to UTOPIA Transmit Clock Propagation Delay SYSCLK DRxCLK SYSCLK DTxCLK t CYC Figure 33 System Clock ...
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IDT77V012 TCLK TxDATA(0-7), TENB, TSOC, TxLED, TxPRTY TCLAV RCLK RENB, RxLED RxDATA(0-7), RSOC, RCLAV DTxCLK DTxFRM, DTxDATA(0-3) DRxCLK DRxFRM, DRxDATA(0-3) t UCYC t UCH t UCL t TOV t UTS Figure 38 UTOPIA Transmit Timing Waveform t URS t ROV ...
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IDT77V012 SYSCLK SYSCLK SYSCLK EECS EECLK EEDO EEDI tPPHYR Figure 42 System Clock to PHYRST Propagation Delay tPINTS tPINTH Figure 43 System ...
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IDT77V012 Device ID 8000 Configuration 1 8001 Figure 46 Timing Waveform for SRAM Read and Write Cycles Device Version NA Device version number. 77V012 Rev A = 0x10, 77V012 ...
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IDT77V012 Configuration 2 8002 Table Offset 8003 Pin Control 8004 TAG 8005 ...
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IDT77V012 Rx TAG and 8006 Mode Select Notification 8007 0 Mask Status 8008 Timeout Status 8009 ...
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IDT77V012 Reset 800A Null Pointer 800B Address Byte Null Pointer 800C Address Byte 1 Null Pointer 800D Address Byte 0 In-Stream™ 800E ...
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IDT77V012 Tx Null Pointer 801B Header Byte 2 Tx Null Pointer 801C Header Byte 1 Tx Null Pointer 801D Header Byte 0 UTOPIA Rx Cell 801E Counter byte ...
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IDT77V012 18000 16000 14000 12000 10000 8000 6000 4000 2000 0 0 500 18000 16000 14000 12000 10000 8000 6000 4000 2000 0 0 500 128K memory - 28 bits header lookup - Cell accounting Best Case Worst Case 1000 ...
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IDT77V012 14000 12000 10000 8000 6000 4000 2000 0 0 500 18000 16000 14000 12000 10000 8000 6000 4000 2000 0 0 500 64K memory - 32 bits header lookup - Cell accounting Best Case Worst Case 1000 1500 2000 ...
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IDT77V012 18000 16000 14000 12000 10000 8000 6000 4000 2000 0 0 500 ...
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... Process/ Temperature Range (Blank) Industrial DA 155 L 77V012 READ RD to for SALES: 800-345-7015 or 408-727-6116 fax: 408-330-1748 www.idt.com PQFP (144-pin) 4-bit Port Bandwidth in Mbps Low Power DATA PATH INTERFACE (DPI) TO UTOPIA LEVEL 1 HEADER TRANSLATION DEVICE 5347drw58 ; in Note for Figure 46, added overbar to pins for Tech Support: email: sarhelp@idt ...