VG36128161BT-7L VML, VG36128161BT-7L Datasheet
VG36128161BT-7L
Related parts for VG36128161BT-7L
VG36128161BT-7L Summary of contents
Page 1
... Programmable /CAS latency (2 and 3) • Automatic precharge and controlled precharge • CBR (Auto) refresh and self refresh • X4, X8, X16 organization • LVTTL compatible inputs and outputs • 4,096 refresh cycles / 64ms . Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Rev.1 Page 1 ...
Page 2
... Function CLK Master Clock CKE Clock Enable /CS Chip Select /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable DQ0 ~ DQ15 Data I/O Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM VG36128401 (x4) VG36128801 (x8) VG36128161 (x16 DQ15 SSQ ...
Page 3
... VIS Block Diagram CLK Clock Generator CKE Address Mode Register CS RAS CAS WE Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Bank D Row Bank C Address Bank B Buffer & Refresh Counter Bank A Sense Amplifier Column Decoder & Column Latch Circuit Address Buffer & ...
Page 4
... Data Input / Output: Data bus Supply Power Supply for the memory array and peripheral circuitry. DD Supply Power Supply are supplied to the output buffers only. DDQ, SSQ Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Function Rev.1 Page 4 ...
Page 5
... Low Level Input Voltage (all inputs) Pin Capacitance ( 70° Parameter Input Capacitance, address & control pin Input Capacitance, CLK pin Data input / output capacitance Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Symbol Conditions V with respect ...
Page 6
... CC5 Self refresh current I CC6 NOTES specified at the output open condition. CC(max) 2. Input signals are changed one time during 30ns. 3. Normal version: VG36128401BT-7H / VG36128801BT-7L / VG36128161BT-8H 4. Low power version: VG36128401BTL-7H / VG3636128401BTL-7L / VG3636128401BTL-8H DC Characteristics 2 ( 70° 3.3 0. DDQ Parameter Input leakage current (Inputs) ...
Page 7
... IH IL Input rise and fall time Output Load Conditions V V DDQ DDQ V OUT Device Under Test Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM = V = 3.3 0. DDQ SS SSQ 2.0 / 0.8V Input timing reference level / Output timing reference level 1ns Output load condition Rev ...
Page 8
... Row precharge time Row active to active delay Write recovery time Transition time Mode reg. set cycle Power down exit setup time Self refresh exit time Refresh time Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM = V = 3.3 0. DDQ SS SSQ Symbol ...
Page 9
... CKE Write with Auto Precharge WRITE A CKE WRITE A SUSPEND CKE Precharge POWER ON Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM MRS REF IDLE CKE ROW ACTIVE CKE Read (write recovery) Write Precharge Note: After the AUTO refresh operation, precharge operation is performed automatically and enter the IDLE state Rev ...
Page 10
... Self refresh Self refresh exit Idle Power down entry Power down Power down exit H : High level Low level X : High or Low level (Don’t care Valid Data input Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM CKE RAS CAS H ...
Page 11
... Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Address Command X DESL Nop or Power down X NOP or BST Nop or Power down BA, CA, A10 READ/READA ILLEGAL BA, CA, A10 WRIT/WRITA ILLEGAL BR, RA ACT Row active BA, A10 ...
Page 12
... Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Address Command X DESL Continue burst to end X NOP Continue burst to end X BST ILLEGAL BA, CA, A10 READ/READA ILLEGAL BA, CA, A10 WRIT/WRITA ILLEGAL BA, RA ACT ILLEGAL ...
Page 13
... Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Must mask preceding data which don’t satisfy t 10. Illegal not satisfied. RRD 11. Illegal for single bank, but legal for other banks in multi-bank devices. Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Address Command X X DESL ...
Page 14
... EXIT. 3. Power down and Self refresh can be entered only from the both banks idle state. 4. Must be legal command as defined in Operative Command Table. 5. Illegal not satisfied. SREX Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM RAS CAS WE Address X X ...
Page 15
... The wrap type specifies the order in which the burst data will be addressed. The order is programmable as either “Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system. Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Rev.1 Page 15 ...
Page 16
... VIS 5. Mode Register LTMODE 0 Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Burst length Wrap type Rev.1 Bits2 - 000 1 1 001 2 2 010 4 4 011 8 8 100 ...
Page 17
... Full page burst is an extension of the above tables of sequential addressing, with the length being 2,048 (for 32Mx4), 1,024 (for 16M x 8) and 512 (for 8Mx16). Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Sequential Addressing Interleave Addressing Sequence Sequence (decimal) ...
Page 18
... In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is valid. In the following table, minus means clocks before the reference; plus means time after the reference. CAS latency 2 3 Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM is satisfied. RAS(min.) is the time required to perform the precharge. RP ...
Page 19
... CLK Command READA B CAS latency = 2 DQ Command READA B CAS latency = 3 DQ Remark READA means READ with AUTO PRECHARGE Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM has been satisfied New Command to Bank B Auto precharge starts QB0 QB1 ...
Page 20
... In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid. In the table below, minus means clocks before the reference; plus means clocks after the reference. CAS latency 2 3 Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM ...
Page 21
... WRITE will be interrupted by another WRITE. Each write command can be asserted in every clock without any restriction. WRITE to WRITE Command Interval T0 CLK Write A Command QA0 DQ 1 cycle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Read B QA0 QB0 QB1 T1 T3 ...
Page 22
... During a read cycle, READ can be interrupted by WRITE. DQM must be in High at least 3 clocks prior to the write command. There is a restriction to avoid a data conflict. The data bus must be Hi-Z using DQM before Write. Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM . OUT ...
Page 23
... READ to WRITE Command Interval T0 CLK Read Command DQM DQ Hi-Z 1 cycle T0 T1 CLK Command Read DQM CLK Command Read DQM DQ Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Write Hi-Z is necessary ...
Page 24
... Hi-Z at the same clock with the burst stop command. Burst Termination T0 CLK Command CAS latency=2 DQ CAS latency=3 DQ Remark BST: Burst stop command T0 CLK Command CAS latency=2,3 DQ Remark BST: Burst command Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM BST Read Write Q0 ...
Page 25
... When CAS latency is 3, the read data will remain valid until two clocks after the precharge command. Precharge Termination in READ Cycle T0 T1 CLK Read Command CAS latency=2 DQ command Read CAS latency=3 DQ Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM from the precharge command PRE ...
Page 26
... PRECHARGE TERMINATION in WRITE Cycle T0 T1 CLK Write Command CAS latency = 2 DQM DQ D0 command Write CAS latency = 3 DQM DQ D0 Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM from the precharge command. The DQM must be high to mask PRE PRE Rev ...
Page 27
... VIS Timing Diagram Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Rev.1 Page 27 ...
Page 28
... VIS Mode Register Set CLK CKE CS RAS CAS WE BS0,1 A10 ADD DQM Hi-Z DQ Precharge Command All Banks Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM RSC Address Key t RP Mode Register Command Set Command Rev T10 Page 28 ...
Page 29
... Command Bank A Command Bank B Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Begin Auto Precharge Begin Auto Precharge Bank A ...
Page 30
... QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 Activate Write with Command Auto Precharge Bank A Command Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Begin Auto Precharge Begin Auto Precharge Bank A Bank DAL RC ...
Page 31
... CS RAS CAS WE *BS0 A10 ADD DQM t RCD Hi-Z DQ Activate Command Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM RRD t RAS AC2 t HZ AC2 QAa0 QAa1 ...
Page 32
... CAS WE *BS0 A10 ADD t RRD DQM t RCD Hi-Z DQ Activate Command Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM T10 T11 t RAS AC3 AC3 QAa0 QAa1 ...
Page 33
... Inputs All Banks Command must be stable for 200us Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Minimum of 8 Refresh Cycles are required t RC 2nd Auto Refresh Command Rev ...
Page 34
... QAa0 Read Activate Command Command Bank A Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 t HZ QAa1 QAa2 QAa3 Clock Clock ...
Page 35
... Hi-Z DQ Activate Read Command Command Bank A Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 t HZ QAa0 QAa1 QAa2 QAa3 Clock Clock ...
Page 36
... Suspended Command 1 Cycle Bank A Write Command Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 DAa2 DAa3 Clock Clock Suspended Suspended ...
Page 37
... Suspended Command 1 Cycle Bank A Write Command Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 DAa1 DAa2 DAa3 Clock Clock Suspended ...
Page 38
... Power Down Power Down Mode Entry Mode Exit * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAa QAa0 QAa1 QAa2 Read ...
Page 39
... CBR Refresh Command Command All Banks * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RAa CAa RAa ...
Page 40
... BS1=”L”, Bank C,D = Idle * Clock can be stopped at CKE=Low. If clock is stopped, it must be restarted/stable for 4 clock cycles before CKE=High Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM ** T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
Page 41
... QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3 Precharge Read Command Command Bank A Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RAa RAd CAb CAc RAd Read ...
Page 42
... Command Command Bank A Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAb CAc QAc2 QAc3 QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 ...
Page 43
... Da2 Activate Write Command Command Bank B Bank B * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Cb Cc Dc2 Dc3 Da3 Db0 Db1 ...
Page 44
... Da1 Activate Write Command Command Bank B Bank B * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Cb Cc Da2 Db0 Db1 Dc0 Dc2 ...
Page 45
... Read Command Command Bank B Bank B * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Burst Length=8, CAS Latency T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 t RP QAa0 QAa1 QAa2 ...
Page 46
... Command Command Bank B Bank B * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 t RP QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 ...
Page 47
... Activate Write Command Command Bank A Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Burst Length=8, CAS Latency T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 t t DPL RP QBa0 QBa1 ...
Page 48
... Write Activate Command Command Bank A Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Burst Length=8, CAS Latency T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RBa t t DPL ...
Page 49
... Write Command Command Bank A Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAb CAc DAb0 DAb1 ...
Page 50
... RAa DQM Hi-Z DQ Activate Read Command Command Bank A Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM CAb DAb0 DAb1 QAa0 QAa1 QAa2 QAa3 DAb3 Write The Write Data Command is Masked with a Bank A Zero Clock Latency Rev ...
Page 51
... RCD Hi-Z DQ QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 Activate Read Activate Command Command Command Bank A Bank A Bank B * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM QBb0 QBb1 QBc0 QBc1 QAb0 Read Read Read Read ...
Page 52
... RRD Hi-Z DQ Activate Read Command Command Bank A Bank A Activate Command Bank B * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM AC3 QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 Read Read Read Read ...
Page 53
... RRD Hi-Z DQ DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 Activate Write Activate Command Command Command Bank A Bank B Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM DBb0 DBb1 DBc0 DBc1 DAb0 DAb1 DBd0 Write Write ...
Page 54
... QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 Activate Write Command Command Bank A Bank A Activate Command Bank B * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency DPL QBb0 QBc0 QBc1 QAb0 ...
Page 55
... Activate Read with Command Auto Precharge Command Command Command Bank A Bank A Bank B Bank B * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Start Auto Precharge Start Auto Precharge Bank B Bank QBa2 QBa3 QAb0 QAb1 ...
Page 56
... Hi-Z DQ Activate Activate Command Command Bank A Bank B Read Command Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Start Auto Precharge Bank QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 Activate Read with ...
Page 57
... Write with Activate Command Auto Precharge Command Command Command Bank A Bank B Bank A Bank B * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Start Auto Precharge Start Auto Precharge Bank B Bank QBa2 QBa3 QAb0 QAb1 ...
Page 58
... QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 Activate Activate Command Command Bank A Bank B Read Command Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Start Auto Precharge Bank RBb Rb QBa2 QBa3 QAb0 QAb1 QAb2 ...
Page 59
... BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Burst Length=Full Page, CAS Latency T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
Page 60
... Bank A Bank B Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Burst Length=Full Page, CAS Latency T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Ca QAa+1 QBa0 QBa+1 QBa+2 QBa+3 QBa+4 QBa+5 ...
Page 61
... BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Burst Length=Full Page, CAS Latency T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
Page 62
... BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Burst Length=Full Page, CAS Latency T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
Page 63
... Activate Command Command Bank A Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Burst Length=4, CAS Latency T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAc CAd CAb DQs are ...
Page 64
... Bank B Read Command Command Bank A Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Burst Length=Full Page, CAS Latency T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
Page 65
... Bank B Write Command Command Bank A Bank A * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Burst Length=Full Page, CAS Latency T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
Page 66
... Bank A Precharge Termination of a Write Burst. Write data is masked. * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RAb RAc RAb CAb ...
Page 67
... Bank A Bank A Write Data Precharge Termination is masked of a Write Burst. * BS1=”L”, Bank C,D = Idle Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RAb RAb CAb t t ...
Page 68
... ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm. DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER THAN THE MIN b DIMENSION BY MORE THAN 0.07mm. Document :1G5-0183 VG36128401BT / VG36128801BT / VG36128161BT CMOS Synchronous Dynamic RAM Cycle time Package 7.5 ns (133MHz 2/2/2) 400mil, 54-Pin 7 ...