RTL8100CL ETC ETC, RTL8100CL Datasheet
RTL8100CL
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RTL8100CL Summary of contents
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... RTL8100C & RTL8100CL SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT DATASHEET Rev. 1.06 05 November 2004 Track ID: JATR-1076-21 ...
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... USING THIS DOCUMENT This document provides detailed user guidelines to achieve the best performance when implementing a 2-layer board PC design with the RTL8100C or RTL8100CL Single-Chip Fast Ethernet Controller with Power Management Control. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide ...
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... GENERAL DESCRIPTION...............................................................................................................1 2. FEATURES..........................................................................................................................................2 3. BLOCK DIAGRAM............................................................................................................................3 4. PIN ASSIGNMENTS ..........................................................................................................................4 4.1. RTL8100C (QFP) & RTL8100CL (LQFP).....................................................................................4 5. PIN DESCRIPTION............................................................................................................................5 5. OWER ANAGEMENT 5.2. PCI I ................................................................................................................................6 NTERFACE 5.3. EPROM/EEPROM I 5. .....................................................................................................................................8 OWER INS 5.5. LED I ...............................................................................................................................8 NTERFACE 5. TTACHMENT NIT 5. EST AND THER INS 5. EGISTER ESCRIPTIONS 5 ...
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... F .......................................................................................39 PACE UNCTIONS S S .............................................................................................41 PACE TATUS P - (RSTB A OWER ON SSERTED F .........................................................................................45 UNCTIONS D ) .......................................................................................................48 ATA ...................................................................................................................49 ......................................................................................................................49 ..............................................................................................................49 ...............................................................................................................50 ..........................................................................................................50 ODULE ..................................................................................................................50 ii RTL8100C & RTL8100CL (O 0060 -0061 EGISTER FFSET H , R/W).................................................. R)..........................................................29 H 0066 -0067 , R/W) .........................30 FFSET 0068 -0069 , R) ...................31 FFSET H H 006A -006B , R) ..................................... ....................................................... R/W) ...
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... Supply Voltage (Vdd25 = 2.3V min. to 2.7V max.)..............................................................54 8. HARACTERISTICS 8.3.1. PCI Bus Operation Timing ..................................................................................................55 9. APPLICATION INFORMATION ..................................................................................................61 10. MECHANICAL DIMENSIONS ......................................................................................................62 10.1. RTL8100C 128-P IN 10.2. N RTL8100C 128-P OTES FOR 10.3. RTL8100CL 128-P IN 10.4. N RTL8100CL 128-P OTES FOR 11. ORDERING INFORMATION ........................................................................................................65 Single-Chip Fast Ethernet Controller ......................................................................................................................51 .........................................................................................................54 ...................................................................................................................54 ...................................................................................................................55 QFP...............................................................................................................62 QFP ............................................................................................63 IN LQFP ...
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... Table 27. Basic Mode Status Register .........................................................................................................29 Table 28. Auto-Negotiation Advertisement Register...................................................................................30 Table 29. Auto-Negotiation Link Partner Ability Register..........................................................................31 Table 30. Auto-Negotiation Expansion Register .........................................................................................32 Table 31. Disconnect Counter......................................................................................................................32 Table 32. False Carrier Sense Counter ........................................................................................................32 Table 33. NWay Test Register......................................................................................................................33 Single-Chip Fast Ethernet Controller List of Tables ii RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Table 43. Base IO Address...........................................................................................................................42 Table 44. Base Memory Address for Memory Accesses .............................................................................43 Table 45. Default Values after Power-On (RSTB Asserted)........................................................................44 Table 46. Thermal Characteristics ...............................................................................................................54 Table 47. Supply Voltage (3.0V min. to 3.6V max.)....................................................................................54 Table 48. Supply Voltage (2.3V min. to 2.7V max.)....................................................................................54 Single-Chip Fast Ethernet Controller RTL8100C & RTL8100CL iii Track ID: JATR-1076-21 Rev. 1.06 Datasheet ...
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... Figure 13. Target Initiated Termination - Retry...........................................................................................58 Figure 14. Target Initiated Termination - Disconnect..................................................................................59 Figure 15. Target Initiated Termination - Abort...........................................................................................59 Figure 16. Master Initiated Termination – Abort.........................................................................................60 Figure 17. Parity Operation - One Example ................................................................................................60 Figure 18. Application Information .............................................................................................................61 Single-Chip Fast Ethernet Controller List of Figures iv RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... RTL8100C(L) is also capable of receiving packets with an InterFrame Gap equal to or more than 40-bit time. The RTL8100C(L) is highly integrated and requires no glue logic or external memory. Single-Chip Fast Ethernet Controller ® wake-up frame) in both ACPI and APM (Advanced Power Management) 1 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Packet*, LinkChg, and Microsoft® wake-up frame) * Third-party brands and names are the property of their respective owners. Note: The QFP package model number is RTL8100C. The LQFP package model number is RTL8100CL. Single-Chip Fast Ethernet Controller RTL8100C & RTL8100CL Supports 4 Wake-On-LAN (WOL) signals ...
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... Wander Correction MLT-3 3 Level Comparator to NRZI ck Serial to Slave Parrallel PLL Data Control Voltage Figure 1. Block Diagram 3 RTL8100C & RTL8100CL LED Driver Transmit/ Receive MII Logic Interface Interface RXD Descrambler RXC 25M TXD TXC 25M Link Pulse 10M Output Waveform Shaping Receive Low Pass Filter ...
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... Pin Assignments 4.1. RTL8100C (QFP) & RTL8100CL (LQFP) 1 TX+ 2 TX- 3 AVDD33 4 GND 5 RX+ 6 RX- 7 AVDD33 8 CTRL25 AVDD25 GND AVDD33(REG) 21 GND ISOLATEB INTAB 26 VDD33 27 PCIRSTB 28 PCICLK 29 GNTB 30 REQB 31 PMEB 32 VDD25 33 AD31 34 AD30 ...
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... When a PME event is received, LWAKE and PMEB assert at the same time if LWPME (bit4, CONFIG4) is set LWPME is set to 1, LWAKE asserts only when PMEB asserts and ISOLATEB is low. This pin is a 3.3V signaling output pin. 5 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... This pin allows the RTL8100C(L) to identify when configuration read/write transactions are intended for it. 25 INTAB. Used to request an interrupt asserted low when an interrupt condition occurs, as defined by the Interrupt Status, Interrupt Mask and Interrupt Enable registers. 6 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... SERRB pin low, and bit 14 of the Status register in Configuration Space. 69 Stop. Indicates the current target is requesting the master to stop the current transaction. 27 Reset. When RSTB is asserted low, the RTL8100C(L) performs an internal system hardware reset. RSTB must be held for a minimum of 120ns. 7 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Ground. Table 5. LED Interface Pin No 117, 115, 114 LEDS1-0 LED0 LED1 LED2 During power down mode, the LEDs are OFF. 8 RTL8100C & RTL8100CL Description LED Pins TX/RX TX/RX TX LINK100 LINK10/100 LINK10/100 LINK10 FULL RX Track ID: JATR-1076-21 Rev. 1.06 ...
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... CLKRUN. For the host system S/T/S signal. The host system (central resource) is responsible for maintaining CLKRUN asserted, and for driving it high to the negated (deasserted) state. Not Connected. 120, 125, 126 9 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Early Rx Status Register. CR Command Register. CAPR Current Address of Packet Read. CBR Current Buffer Address. The initial value is 0000h. It reflects total received byte-count in the Rx buffer. IMR Interrupt Mask Register. ISR Interrupt Status Register. TCR Transmit (Tx) Configuration Register. 10 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Power Management CRC register 0 for wakeup frame 0. CRC1 Power Management CRC register 1 for wakeup frame 1. CRC2 Power Management CRC register 2 for wakeup frame 2. CRC3 Power Management CRC register 3 for wakeup frame 3. CRC4 Power Management CRC register 4 for wakeup frame 4. 11 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... This bit set to 1 indicates that the received packet length is smaller than 64 bytes ( i.e. media header + data + CRC < 64 bytes ) LONG Long Packet. This bit set to 1 indicates that the size of the received packet exceeds 4k bytes. 12 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... When the byte count of the data in the Tx FIFO reaches this level, (or the FIFO contains at least one complete packet) the RTL8100C(L) will transmit this packet. 000000 = 8 bytes These fields count from 000001 to 111111 in units of 32 bytes. This threshold must be prevented from exceeding 2k bytes. 13 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... The power-on value set when the Rx byte count of the arriving packet exceeds the Rx threshold. After the whole packet is received, the RTL8100C(L) will set ROK or RER in ISR and clear this bit simultaneously. Setting this bit will invoke an ROK interrupt. 14 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... This bit will be reset after PCI reset deassertion. - Reserved. BUFE Buffer Empty. RX Buffer Empty. There are no packets stored in the RX buffer ring. Table 13. Interrupt Mask Register Symbol Description SERR System Error Interrupt. 1: Enable 0: Disable TimeOut Time Out Interrupt. 1: Enable 0: Disable 15 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Set to 1 when the RTL8100C(L) signals a system error on the PCI bus. TimeOut Time Out. Set to 1 when the TCTR register reaches the value of the TimerInt register. LenChg Cable Length Change. Cable length is changed after Receiver is enabled. - Reserved. 16 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Rx threshold. Table 15. Transmit Configuration Register Symbol Description - Reserved. HWVERID_A Hardware Version ID A. RTL8139 RTL8139A RTL8139A-G RTL8139B RTL8130 RTL8139C RTL8100 RTL8100B RTL8100C RTL8139D RTL8139C+ RTL8101 Reserved 17 RTL8100C & RTL8100CL Bit3 Bit2 Bit2 Bit2 Bit2 ...
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... Reserved. CLRABT Clear Abort. Setting this bit to 1 causes the RTL8100C(L) to retransmit the packet at the last transmitted descriptor when this transmission was aborted, Setting this bit is only permitted in the transmit abort state. 18 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... The RTL8100C(L) accepts error packets with a length larger than 64 bytes. The power-on default is zero. If AER set, the RER (Receive Error) will be set when the RTL8100C(L) receives an error packet with a length larger than 8 bytes. RER8 is irrelevant in this situation. 19 RTL8100C & RTL8100CL Datasheet 0001 = 1/16 0011 = 3/16 0101 = 5/16 0111 = 7/16 ...
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... Kbytes buffer to accept the remainder of the packet. We assume that the remainder of the packet is X bytes. The next packet will be moved into the memory from the X byte offset at the top of the Rx buffer. This bit is invalid when the Rx buffer is set to 64 Kbytes. - Reserved. 20 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Accept 0: Reject AB Accept Broadcast packets. 1: Accept 0: Reject AM Accept Multicast packets. 1: Accept 0: Reject APM Accept Physical Match packets. 1: Accept 0: Reject AAP Accept All Packets. Set accept all packets with a physical destination address. 1: Accept 0: Reject 21 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... These bits reflect the state of EECS, EESK, EEDI, and EEDO pins in auto-load or 93C46 programming mode. EESK EEDI EEDO 22 RTL8100C & RTL8100CL Datasheet Operating Mode Normal: RTL8100C(L) network/host communication mode. Auto-load: Entering this mode will force the RTL8100C(L) to load the contents of the 93C46 RSTB signal had been asserted ...
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... LWAKE pin is an active high signal. LWAKE Output 0 LWPTN 1 * Default value. Memory Mapping. Operational registers are mapped into PCI memory space. I/O Mapping. Operational registers are mapped into PCI I/O space. 23 RTL8100C & RTL8100CL Datasheet LWACT 0 1 Active high* Active low Positive pulse Negative pulse Track ID: JATR-1076-21 Rev. 1.06 ...
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... Flow control is enabled in full-duplex mode only. The default value comes from the 93C46. - Reserved. Aux_Status Aux. Power present Status. 1: Aux. Power is present 0: Aux. Power is absent The value of this bit is fixed after each PCI reset. 24 RTL8100C & RTL8100CL Datasheet Remote TXFCE/LdTXFCE NWAY FLY mode R/O NWAY mode only R/W No NWAY R/W ...
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... Allows parameters to be auto-loaded from the 93C46, and disables writing to PHY1_PARM, PHY2_PARM and TW_PARM registers via software. PHY1_PARM and PHY2_PARM can be auto-loaded from the EEPROM in this mode. The parameter auto-load process is executed each time the Link 100Mbps mode. 25 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... This bit is valid when the PWEn bit of CONFIG1 register is set. The RTL8100C(L), when in an adequate power state, will assert the PMEB signal to wakeup the operating system when the cable connection is re-established. - Reserved. FBtBEn Fast-Back-to-Back Enable. Set enable Fast-Back-to-Back. 26 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... LWAKE Pattern. See the LWACT bit in Table 19. CONFIG 1: Configuration Register 1, page 23. - Reserved. PBWakeup Pre-Boot Wakeup. The initial value comes from EEPROM auto load. 1: Pre-Boot Wakeup disabled (suitable for CardBus and MiniPCI applications) 0: Pre-Boot Wakeup enabled 27 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... TOK bit of Descriptor 0. TUN3 TUN bit of Descriptor 3. TUN2 TUN bit of Descriptor 2. TUN1 TUN bit of Descriptor 1. TUN0 TUN bit of Descriptor 0. TABT3 TABT bit of Descriptor 3. TABT2 TABT bit of Descriptor 2. TABT1 TABT bit of Descriptor 1. TABT0 TABT bit of Descriptor 0. 28 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Description/Usage 1: Enable 100Base-T4 support 0: Disable 100Base-T4 support 0: Disable 100Base-TX full-duplex support 0: Disable 100Base-TX half-duplex support 1: Enable 10Base-T full-duplex support 0: Disable 10Base-T full-duplex support 1: Enable 10Base-T half-duplex support 0: Disable 10Base-T half-duplex support 29 RTL8100C & RTL8100CL Datasheet Default/Attribute ...
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... Binary encoded selector supported by this node. Currently only CSMA/CD <00001> is specified. No other protocols are supported. 30 RTL8100C & RTL8100CL Datasheet Default/Attribute - ...
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... Link Partner's binary encoded node selector. Currently only CSMA/CD <00001> is specified. 31 RTL8100C & RTL8100CL Datasheet Default/Attribute ...
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... This 16-bit counter increments by 1 for every disconnect event. It rolls over when full cleared to zero by a read command. Table 32. False Carrier Sense Counter Description/Usage This 16-bit counter increments by 1 for each false carrier event cleared to zero by a read command. 32 RTL8100C & RTL8100CL Datasheet Default/Attribute - ...
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... Assertion of this bit forces the disconnect function to be bypassed. Reserved. This bit indicates the status of the connection. 1: Valid connected link detected 0: Disconnected link detected Assertion of this bit configures the LED1 pin to indicate connection status. Reserved. Bypass Scramble. 33 RTL8100C & RTL8100CL Datasheet Default/Attribute - Default/Attribute ...
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... LANWake signal enable/disable. 1: Enable LANWake signal 0: Disable LANWake signal PME_STS PME_Status bit. Always sticky/can be reset by PCI RST# and software. 1: The PME_Status bit may be reset by PCI reset or by software 0: The PME_Status bit may only be reset by software 34 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Power Management Capabilities. PCI configuration space address 52h and 53h. Reserved. Do not change this field without Realtek approval. Power Management Control/Status. PCI configuration space address 55h. Reserved. Do not change this field without Realtek approval. 35 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Checksum of the EEPROM content. Reserved. Do not change this field without Realtek approval. Reserved. Do not change this field without Realtek approval. PXE ROM code parameter. VPD data field. Offset 40h is the start address of the VPD data. 36 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Spd_Set GNTDel Magic PARM_EN - Magic PARM_EN RxFIFO AnaOff LongWF AutoClr - - - Bit7 Bit6 Bit5 Aux_I_b1 Aux_I_b0 DSI PME_D3 PME_D3 PME_D2 PME_D1 cold hot PME_Status - - PME_Status - - 37 RTL8100C & RTL8100CL Bit4 Bit3 Bit2 - - BS2 - - - LWACT MEMMAP IOMAP LWACT - - - - - - - - ANE - - ANE - - LinkUp - - LinkUp - - LWPME ...
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... RESERVED SVID6 SVID5 SVID4 SVID14 SVID13 SVID12 SMID6 SMID5 SMID4 SMID14 SMID13 SMID12 - - - RESERVED ILR6 ILR5 ILR4 RTL8100C & RTL8100CL Bit4 Bit3 Bit2 Bit1 BMEN MEMEN - - BMEN MEMEN FBTBEN SERREN - ...
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... RESERVED VPDADDR VPDADD VPDADD 6 R5 VPDADDR VPDADD VPDADD 14 R13 Data6 Data5 Data4 Data14 Data13 Data12 Data22 Data21 Data20 Data30 Data29 Data28 RESERVED 39 RTL8100C & RTL8100CL Bit4 Bit3 Bit2 Version ...
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... The RTL8100C(L) responds to memory space accesses 0: The RTL8100C(L) ignores memory space accesses 0 IOEN I/O Space Access. 1: The RTL8100C(L) responds to IO space accesses 0: The RTL8100C(L) ignores I/O space accesses Single-Chip Fast Ethernet Controller Table 41. PCI Configuration Space Functions 40 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Read as 0. Write operation has no effect. The RTL8100C(L) has no 66MHz capability. 4 NewCap New Capability. Config3<PMEn>=0, Read as 0. Write operation has no effect. Config3<PMEn>=1, Read as 1. 0-3 - Reserved. Single-Chip Fast Ethernet Controller Table 42. PCI Configuration Space Status 41 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Read back as 0. This allows the PCI bridge to determine that the RTL8100C(L) requires 256 bytes of IO space Reserved. 0 IOIN IO Space Indicator. Read only. Set the RTL8100C(L) to indicate that it is capable of being mapped into IO space. Single-Chip Fast Ethernet Controller Table 43. Base IO Address 42 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Indicates how long the RTL8100C(L) is allowed access to the PCI bus, in units of 1/4 microseconds. This field will be set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h. Single-Chip Fast Ethernet Controller RTL8100C & RTL8100CL 43 Track ID: JATR-1076-21 Rev. 1.06 Datasheet ...
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... RESERVED (ALL Ptr7 Ptr6 Ptr5 RESERVED (ALL RESERVED (ALL 0) 44 RTL8100C & RTL8100CL Bit4 Bit3 Bit2 Bit1 BMEN MEMEN ...
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... Note: In this case, if wakeup support is desired when the main power is off suggested that the EEPROM PMC be set to (Realtek default value not recommended to set the D0_support_PME bit to 1. Single-Chip Fast Ethernet Controller RTL8100C & RTL8100CL 45 Track ID: JATR-1076-21 Rev. 1.06 Datasheet ...
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... Software should calculate the 8-bit Power Management CRC for each specific sample wakeup frame and store the calculated CRC in the corresponding CRC register for the RTL8100C(L) to check whether there is a Wakeup Frame coming in. Single-Chip Fast Ethernet Controller RTL8100C & RTL8100CL 46 Track ID: JATR-1076-21 Rev. 1.06 Datasheet ...
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... RST# is asserted, the power state must be changed the original power state was D3 hardware enforced delays in the RTL8100C(L)’s power state. When in ACPI mode, the RTL8100C(L) does not support PME from D0 owing to the PMC register setting (this setting comes from EEPROM). Single-Chip Fast Ethernet Controller RTL8100C & RTL8100CL 47 Track ID: JATR-1076-21 Rev. 1.06 Datasheet ...
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... Write the flag bit to a zero at the same time the VPD address is written. When the flag bit is set to one by the RTL8100C(L), the VPD data (all 4 bytes) has been transferred from the 93C46 to the VPD data register. Single-Chip Fast Ethernet Controller RTL8100C & RTL8100CL 48 Track ID: JATR-1076-21 Rev. 1.06 Datasheet ...
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... The signal detect function of the 8100C(L) is incorporated to meet the specifications mandated by the ANSI FDDI TP-PMD standard as well as the IEEE 802.3 100Base-TX standard for both voltage thresholds and timing parameters. Single-Chip Fast Ethernet Controller RTL8100C & RTL8100CL 49 Track ID: JATR-1076-21 Rev. 1.06 Datasheet ...
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... If the RTL8100C(L) is not in full-duplex mode, a collision event occurs when the receive input is not idle while the RTL8100C(L) transmits. If the collision was detected during the preamble transmission, a jam pattern is transmitted after completing the preamble (including the JK symbol pair). Single-Chip Fast Ethernet Controller RTL8100C & RTL8100CL 50 Track ID: JATR-1076-21 Rev. 1.06 Datasheet ...
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... Note: The PAUSE operation cannot be used to inhibit transmission of MAC Control frames (e.g. PAUSE packet). NWay flow control capability can be disabled. Refer to section 5.37 EEPROM (93C46) Contents, page 35. Single-Chip Fast Ethernet Controller RTL8100C & RTL8100CL 51 Track ID: JATR-1076-21 Rev. 1.06 Datasheet ...
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... The Link Monitor senses whether a station is connected and monitors link integrity. Note: In 10/100Mbps mode, LED function is the same as that of the RTL8139C(L). 7.12.2. LED_RX Single-Chip Fast Ethernet Controller Power On LED = High No Receiving Packet? Yes LED = High for (100 ±10) ms LED = Low for (12 ±2) ms Figure 3. LED_RX 52 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... LED = High No Transmitting Packet? Yes LED = High for (100 ±10) ms LED = Low for (12 ±2) ms Figure 4. LED_TX Power On LED = High Packet? Yes LED = High for (100 +- 10) ms LED = Low for ( Figure 5. LED_TX+LED_RX 53 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... I OH= -8mA I OL= 8mA V IN GND V OUT GND I OUT= 0mA Conditions I OH= -8mA I OL= 8mA V IN= V dd25 or GND V OUT= V dd2 5 or GND I OUT= 0mA 54 RTL8100C & RTL8100CL Datasheet Units °C +125 °C 70 Minimum Maximum 0.9 * Vcc Vcc 0.1 * Vcc 0.5 * Vcc Vcc+0.5 -0.5 0.3 * Vcc -1 ...
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... AC Characteristics 8.3.1. PCI Bus Operation Timing Target Read Target Write Single-Chip Fast Ethernet Controller Figure 6. Target Read Figure 7. Target Write 55 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Configuration Read Configuration Write Single-Chip Fast Ethernet Controller Figure 8. Configuration Read Figure 9. Configuration Write 56 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Bus Arbitration Memory Read Single-Chip Fast Ethernet Controller Figure 10. Bus Arbitration Figure 11. Memory Read 57 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Memory Write Target Initiated Termination - Retry Single-Chip Fast Ethernet Controller Figure 12. Memory Write Figure 13. Target Initiated Termination - Retry 58 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Target Initiated Termination - Disconnect Figure 14. Target Initiated Termination - Disconnect Target Initiated Termination - Abort Single-Chip Fast Ethernet Controller Figure 15. Target Initiated Termination - Abort 59 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Master Initiated Termination – Abort Parity Operation - One Example Single-Chip Fast Ethernet Controller Figure 16. Master Initiated Termination – Abort Figure 17. Parity Operation - One Example 60 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Application Information RJ-45 Single-Chip Fast Ethernet Controller EEPROM LED Magnetics RTL8100C(L) PCI INTERFACE Figure 18. Application Information 61 RTL8100C & RTL8100CL Datasheet CLK Auxiliary Power Track ID: JATR-1076-21 Rev. 1.06 ...
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... Mechanical Dimensions 10.1. RTL8100C 128-Pin QFP See the Mechanical Dimensions notes on the next page. Single-Chip Fast Ethernet Controller RTL8100C & RTL8100CL 62 Track ID: JATR-1076-21 Rev. 1.06 Datasheet ...
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... Controlling dimension: Millimeter 0.10 0.25 0.91 4. General appearance spec. should be based on final visual inspection spec. 2.60 2.85 3.10 0.12 0.32 0.22 0.05 0.15 0.25 13.75 14.00 14.25 TITLE: 128 QFP (14x20 mm) PACKAGE OUTLINE 19.75 20.00 20.25 0.25 0.5 0.75 16.90 17.20 17.50 APPROVE 22.90 23.20 23.50 0.68 1.08 0.88 1.35 1.60 1.85 CHECK - - 0.10 - 0° 12° 63 RTL8100C & RTL8100CL -CU L/F, FOOTPRINT 3.2 mm LEADFRAME MATERIAL : DOC. NO. 530-ASS-P004 VERSION PAGE DWG NO. DATE REALTEK SEMICONDUCTOR CORP. Track ID: JATR-1076-21 Rev. 1.06 Datasheet 1 OF Q128 - 1 ...
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... RTL8100CL 128-Pin LQFP See the Mechanical Dimensions notes on the next page. Single-Chip Fast Ethernet Controller RTL8100C & RTL8100CL 64 Track ID: JATR-1076-21 Rev. 1.06 Datasheet ...
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... Notes for RTL8100CL 128-Pin LQFP Symbol Dimension in inch Min Type Max 0.067 A1 0.000 0.004 0.008 0.00 A2 0.051 0.055 0.059 1.30 b 0.006 0.009 0.011 0.15 0.004 - 0.006 0.09 c 0.541 0.551 0.561 13.75 14. 0.778 0.787 0.797 19.75 20. 0.020 BSC HD 0.620 0.630 0.640 15.90 16.00 HE 0.855 0.866 0.877 21.70 22.00 L 0.016 0.024 0.031 0.45 ...