AL101 Allayer Communications, AL101 Datasheet

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AL101

Manufacturer Part Number
AL101
Description
8-port RoX Switch IC
Manufacturer
Allayer Communications
Datasheet

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Figure 1
8 Port 10/100 Mbit/s Dual Speed Fast Ethernet Switch
Product Description
The AL101 is an 8-port 10/100 Mbit/s dual speed Ethernet switch. A low-cost and scalable solution
for up to 32 ports is achieved through the use of low-cost buffer memory and Allayer’s proprietary
RoX
System Block Diagram
TM
Supports 8 10/100 Mbit/s Ethernet
ports with RMII interface
Capable of trunking for up to 800 Mbit/
s link
Full- and half-duplex mode operation
Speed auto-negotiation through MDIO
Built-in storage of 1K MAC addresses
Designed to utilize low-cost SGRAM
Scalable design for stackable switch
implementation
RoX expansion link supports 4.8 Gbit/s
throughput
Serial EEPROM interface for low cost
system configuration
Gigabit Ethernet ready
architecture. In addition, the AL101 supports VLAN and multiple link aggregation trunks.
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
Reference Only / Allayer Communications
High Speed
Switch Fabric
Management
Information
Automatic source address learning
Secure mode traffic filtering
Broadcast storm control
Port monitoring support
IEEE 802.3x flow control for full-
duplex operation
Optional backpressure flow control sup-
port for half-duplex operation
Supports store-and-forward mode
switching
VLAN support
RMON and SNMP support with exter-
nal management (MIB) device
3.3V operation
Packaged in 256-pin PQFP
Switch
Controller
Address
Control
Address
Table
Expansion
Interface
EEPROM
Interface
Address
Table
Expansion
Buffer
Manager
Revision 1.0
AL101

Related parts for AL101

AL101 Summary of contents

Page 1

... Gigabit Ethernet ready Product Description The AL101 is an 8-port 10/100 Mbit/s dual speed Ethernet switch. A low-cost and scalable solution for ports is achieved through the use of low-cost buffer memory and Allayer’s proprietary TM RoX architecture. In addition, the AL101 supports VLAN and multiple link aggregation trunks. ...

Page 2

... Life Support Applications Allayer Communications products are not designed for use in life support appliances, systems, or devices where malfunctions can be reasonably expected to result in personal injury. 5/00 Reference Only / Allayer Communications ...

Page 3

... AL101 Overview ..................................................................................................... 5 2. Pin Descriptions....................................................................................................... 7 3. Functional Description........................................................................................... 17 3.1 RoX Interface................................................................................................. 17 3.2 Data Reception............................................................................................... 17 3.2.1 Illegal Frame Length ............................................................................. 17 3.2.2 Long Frames ......................................................................................... 17 3.2.3 False Carrier Events .............................................................................. 18 3.2.4 Frame Filtering ...................................................................................... 18 3.3 Frame Forwarding.......................................................................................... 18 3.3.1 Broadcast Storm Control ....................................................................... 19 3.3.2 Frame Transmission .............................................................................. 19 3.3.3 Frame Generation .................................................................................. 19 3.4 Half Duplex Mode Operation ........................................................................ 20 3.5 Secure Mode Operation ................................................................................. 20 3.6 Address Learning ........................................................................................... 21 3.6.1 Address Aging ....................................................................................... 22 3 ...

Page 4

... EEPROM MAP ..................................................................................... 42 3.17 SGRAM Interface .......................................................................................... 46 4. Register Descriptions............................................................................................. 46 5. Timing Requirements............................................................................................. 63 6. Electrical Specifications ........................................................................................ 72 7. AL101 Mechanical Data........................................................................................ 73 8. Appendix I (VLAN Mapping Work Sheet) ........................................................... 74 9. Appendix II (Port to Trunk Port Assignment Work Sheet) ................................... 75 10. Appendix III (Suggested Memory Components)................................................... 76 5/00 Reference Only / Allayer Communications 4 ...

Page 5

... The device also provides two levels of security for intrusion protection. Security can be implemented on a per port basis. The AL101 operates only in the store and forward mode. The entire frame is checked for errors and any frames with errors are automatically filtered and will not be forwarded to the destination port. ...

Page 6

... RID6 RID5 RID4 RID3 M2CRS 55 GND GND M2TXD1 VCC M2TXD0 60 M2TXEN M2RXCLK M2RXD0 M2RXD1 65 Figure 2 AL101 Pin Diagram (Top View) 5/00 Reference Only / Allayer Communications ROD29 ROD28 ROD27 190 ROD26 VCC ROD25 ROD24 185 ROD23 GND GND M7RXD1 M7RXD0 M7RXCLK 180 M7TXEN ...

Page 7

... Transmit Enable - Synchronous to the transmit clock Receive Data - NRZ data from the transceiver. 35 For RMII interface, signal RX_DV, RX_ER and RX_D0 through RX_D1 are sampled by the rising edge of RX_CLK Receive Clock. (50 MHz Carrier Sense. Active high. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION 7 ...

Page 8

... Transmit Enable - Synchronous to the transmit clock Receive Data - NRZ data from the transceiver. 89 For RMII interface, signal RX_DV, RX_ER and RX_D0 through RX_D1 are sampled by the rising edge of RX_CLK Receive Clock. (50 MHz Carrier Sense. Active high. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION 8 ...

Page 9

... Transmit Enable - Synchronous to the transmit clock. I Receive Data - NRZ data from the transceiver. For RMII interface, signal RX_DV, RX_ER and RX_D0 through RX_D1 are sampled by the rising edge of RX_CLK. I Receive Clock. (50 MHz) I Carrier Sense. Active high. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION 9 ...

Page 10

... Transmit Enable - Synchronous to the transmit clock. I Receive Data - NRZ data from the transceiver. For RMII interface, signal RX_DV, RX_ER and RX_D0 through RX_D1 are sampled by the rising edge of RX_CLK. I Receive Clock. (50 MHz) I Carrier Sense. Active high. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION 10 ...

Page 11

... Table 9: RoX Input Interface I Ring Input Device Ring Control Signal Ring In Clock. Reference Only / Allayer Communications DESCRIPTION 11 ...

Page 12

... ROD1 122 ROD0 121 RODH 120 ROCTL7 119 ROCTL6 118 ROCTL5 116 ROCTL4 115 ROCTL3 114 ROCTL2 113 ROCTL1 112 ROCTL0 111 ROCTLH 110 5/00 Table 10: RoX Output Interface I/O O Ring Output Device Ring Control Data. O Reference Only / Allayer Communications DESCRIPTION 12 ...

Page 13

... Mbit/s SGRAM. 236 O This pin is connected to address 9 when connected Mbit/s SGRAM and address 8 when connected Mbit/s SGRAM. 256 O This pin is connected to address 8 when connected Mbit/s SGRAM and unconnected when connected Mbit/s SGRAM. Reference Only / Allayer Communications DESCRIPTION 13 ...

Page 14

... Write Enable. 196 O System Clock Output to drive the SGRAM. Table 12: EEPROM Interface I/O 253 I/O EEPROM Data Input and Output. 254 O EEPROM Clock. Table 13: MDIO Interface I PHY Management Clock. 94 I/O PHY Management Data Input and Output. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION DESCRIPTION 14 ...

Page 15

... This pin bypasses the EEPROM setup. This pin should be tied to ground. 248 I 75 MHz System Clock. Table 15: Power Interface PIN NUMBER 226, 241 130 Reference Only / Allayer Communications DESCRIPTION DESCRIPTION Ground 3.3 V Supply Voltage. Supply Voltage for RMII. For 5V RMII interface, VccM should be 5V. For 3.3V RMII, VccM should be 3 ...

Page 16

... PBD[n] 9 PBA[n] PBBA Buffer PBCS Manager PBRAS PBCAS PBWE PBDSF PBDQM PBCLK Figure 3 Interface Block Diagram 5/00 High Speed Switch Fabric Reference Only / Allayer Communications Switch Controller Expansion Interface Address Control Address Table PHY Management Management Information EEPROM Interface ROD[n] ROCTL[n] RODH ...

Page 17

... Long Frames The AL101 can handle frames up to 1536 bytes. All frames longer than 1536 bytes will be discarded. If the port continued to receive data after the 1536 If the port is in half-duplex mode, the port will no longer be able to transmit or receive data during the long frame reception ...

Page 18

... The false carrier event is recorded for the MIB counter. 3.2.4 Frame Filtering The AL101 will make filtering and forwarding decisions for each frame received based on its frame routing table, VLAN Mapping, port state, and the system configuration. Under the following conditions, received frames are filtered. ...

Page 19

... VLANs of the receiving port. If the Flood Control option is enabled, the AL101 will forward the frame only to the uplink port specified at the receiving port. The AL101 defines a port as either a single port or a trunk. If the port monitoring function is enabled, the frame forwarding decision is also subject to the port monitoring configurations. If the first bit of the destination address is a “ ...

Page 20

... IEEE backoff algorithm. 3.5 Secure Mode Operation The AL101 provides security support on a per port basis. Whenever the secure mode is enabled, the port will stop learning new addresses. The address table of each port will remain unchanged. In this mode of operation, the address lookup table will freeze and no additional new address will be learned ...

Page 21

... If the security option is selected for the port, AL101 will consider this as a security violation. If port is a non-protected port, the AL101 will delete the SA from the previous port’s address table and update it to the current port’ ...

Page 22

... An uplink port can either be a single port or a trunk. The AL101 provides two VLAN register per ports (register 1D to 2C) for mapping to 32 ports (32 bits). Each register contains a 16-bit bit-map (total of 32 bits) to indicate the VLAN group for the port. The VLAN registers hold the broadcast destination mask for each source port. A “ ...

Page 23

... Reference Only / Allayer Communications ...

Page 24

... Reference Only / Allayer Communications ...

Page 25

... VLAN. In essence, the AL101 treats a trunk as any single port within the same VLAN. If the ports traffic is evenly distributed among all the trunk ports, load balancing is achieved and the aggregate bandwidth of the trunk can be as high as 800 Mbit/s (full duplex) ...

Page 26

... This is to ensure that broadcast frames will only be forwarded to the assigned port. Note: The specific bits in the register are reference by a “X.Y” notation, where X is the register number and Y is the bit number. 5/00 Figure AL101 Trunk Port 0 Reference Only / Allayer Communications 5) ...

Page 27

... Trunk ports should be assigned with their own the port number in the port to trunk port register. The port to trunk port bits should be: 32.2= 0, 32.3 =1 33.2= 1. 33.3 =0 34.2= 1, 34.3 =1 5/00 Reference Only / Allayer Communications 27 ...

Page 28

... Trunk 6 2 Bits 1 13 Trunk 5 6 Bits 5 11 Trunk 4 2 Bits Trunk 3 6 Bits 5/00 Table 18: Trunking Port Assignment BIT VALUE Reference Only / Allayer Communications 28 ...

Page 29

... TRUNK PORT 3 Trunk 2 2 Bits Trunk 1 6 Bits Trunk 0 2 Bits 5/00 Table 18: Trunking Port Assignment BIT VALUE Reference Only / Allayer Communications ...

Page 30

... Reference Only / Allayer Communications ...

Page 31

... MAC Based Load Balancing For MAC address based load balancing, there is no need to assign a port to a trunk port. The AL101 dynamically assigns MAC address to the trunk port. MAC address based trunks must consist of four trunk ports. The bits are chosen for their randomness. The statistically random bits will ensure good load balancing among all four trunk ports. The following is a procedure to set up the trunk ...

Page 32

... Reference Only / Allayer Communications ...

Page 33

... The IPG of the jamming signal can be programmed be either 64BT or 96BT. Collision Based backpressure is generated by the AL101, only when the switch port receives a frame. The AL101 will cease to jam the line when the line is idle. ...

Page 34

... Queue Management Each port of the AL101 has its own individual transmission and receive queues. All frames that come into the AL101 are stored into the shared memory buffer, and are lined up in the transmission queues of corresponding destination port. Each port of the AL101 has an input frame queue, and a dedicated queue to buffer the locally generated management event messages ...

Page 35

... Mbit/s. A copy of egress (TX) data and ingress (RX) data of the monitored port is sent to their respective snooping ports. The monitored port is selected by register 06. The AL101 allows the transmit and receive data to be monitored by different snooping ports. The snooping ports are also selected by register 06. ...

Page 36

... For a read operation, the AL101 will output a “10” to indicate read operation after the start of frame indicator. Following the “10” read signal will be the five-bit ID address of the PHY device and the five-bit register address ...

Page 37

... The AL101 can set the port operation mode manually through the MDIO interface (see EEPROM section for programming the AL101 CPU is used to reprogram the PHY via AL101, the operating mode is changed without reset or powered down. In order to ensure the link is operating in the desired mode, the PHY should renegotiate either through a command or unplugging the RJ45 ...

Page 38

... Unfortunately, such register addresses are vendor specific. The AL101 provides a register (register 05) to specify the register address of the PHY to for the AL101 to read. The AL101 will read from that register and configure the port operation accordingly. ...

Page 39

... EEPROM. The most significant four bits of the EEPROM address are the device type identifier. These four bits are 1010. The EEPROM device address should be set to the device ID number. The EECLK is an output from the AL101. EEDIO is an input if the AL101 is reading the EEPROM or an output writing to it. (See Figure 8 and 9.) EECLK ...

Page 40

... R/W bit of the EEPROM address is set to a “1.” Device Start Address EEDIO Acknowledge Figure 9 Typical Read Operation 5/00 Device Address Word Address Acknowledge Start S Word Address Acknowledge Reference Only / Allayer Communications Stop S Data n Acknowledge No Acknowledge Device Address Acknowledge Data n 40 ...

Page 41

... AL101 as an EEPROM. The read and write timing is the same as an EEPROM. Because you read as well write to the AL101, status of the register can be read from the AL101. This will serve as a very useful tool for diagnostic of an unmanaged switch. ...

Page 42

... Y is the bit number. The following table shows the EEPROM addresses map cross-referenced to the register/bit set of the AL101. Addresses 00 through 6D are for configuring the device. They are downloaded by the AL101 during reset or power up. Address 06 and 07 should be programmed as 0000 0001 and 0001 0100. ...

Page 43

... Port 1 Configuration I 20-21 Port 1 Configuration II 22-23 Port 2 Configuration I 24-25 Port 2 Configuration II 26-27 Port 3 Configuration I 28-29 Port 3 Configuration II 2A-2B Port 4 Configuration I 2C-2D Port 4 Configuration II 2E-2F Port 5 Configuration I 30-31 Port 5 Configuration II 32-33 Port 6 Configuration I 5/00 Table 21: AL101 EEPROM Mapping DESCRIPTION Reference Only / Allayer Communications AL101 REGISTER/BIT 00.15 to 00.8 00.7 to 00.0 01.15 to 01.0 02.15 to 02.0 03.15 to 03.0 04.15 to 04.0 05.15 to 05.0 06.15 to 06.0 07.15 to 07.0 08.15 to 08.0 09.15 to 09.0 0A.15 to 0A.0 0B.15 to 0B.0 0C.15 to 0C.0 0D.15 to 0D.0 0E.15 to 0E.0 0F.15 to 0F.0 10.15 to 10.0 11 ...

Page 44

... Table 21: AL101 EEPROM Mapping (Continued) 34-35 Port 6 Configuration II 36-37 Port 7 Configuration I 38-39 Port 7 Configuration II 3A-3B Port 0 VLAN Map I 3C-3D Port 0 VLAN Map II 3E-3F Port 1 VLAN Map I 40-41 Port 1 VLAN Map II 42-43 Port 2 VLAN Map I 44-45 Port 2 VLAN Map II 46-47 Port 3 VLAN Map I 48-49 Port 3 VLAN Map II 4A-4B Port 4 VLAN Map I 4C-4D Port 4 VLAN Map II ...

Page 45

... Table 21: AL101 EEPROM Mapping (Continued) 6F Last Entry Address 70-71 Static Entry 1 (Port Number) 72-73 Static Entry 1 (MAC [47:32]) 74-75 Static Entry 1 (MAC [31:16]) 76-77 Static Entry 1 (MAC [15:0]) 78-7f Static Entry 2 80-87 Static Entry 2 88-8f Static Entry 4 90-97 Static Entry 5 98-9f Static Entry 6 A0-A7 Static Entry 7 A8-AF Static Entry 8 B0-B7 Static Entry 9 B8-BF Static Entry 10 C0-C7 Static Entry 11 ...

Page 46

... SGRAM Interface All ports of the AL101 work in Store-And-Forward mode so that all ports can support both 10 Mbit/s and 100 Mbit/s data speed. The AL101 utilize a central memory buffers pool, which is shared by all ports within the same device. After a frame is received passed across the SGRAM interface and stored in the buffer ...

Page 47

... Port 0 VLAN Map I Port 0 VLAN Map II Port 1 VLAN Map I Port 1 VLAN Map II Port 2 VLAN Map I Port 2 VLAN Map II Port 3 VLAN Map I Port 3 VLAN Map II Port 4 VLAN Map I Port 4 VLAN Map II Port 5 VLAN Map I Port 5 VLAN Map II Port 6 VLAN Map I Reference Only / Allayer Communications 47 ...

Page 48

... Port 3 Operation Status Port 4 Operation Status Port 5 Operation Status Port 6 Operation Status Port 7 Operation Status Indirect Resource Access Command Indirect Resource Access Data I Indirect Resource Access Data II Indirect Resource Access Data III Indirect Resource Access Data IV CheckSum Reference Only / Allayer Communications 48 ...

Page 49

... Port Incoming Frame Flow Monitoring Enable Cable. 0: Disable 1: Enable Port Outgoing Frame Flow Monitoring Enable Cable. 0: Disable 1: Enable This bit is used by the AL101 when the AL101 is initialized by the CPU. A “1” indicates register file initialization is completed by the CPU. Reference Only / Allayer Communications DESCRIPTION 49 ...

Page 50

... Disable. Device will perform the IEEE standard exponential back off algorithm when a collision occurs. 1: Enable. When collisions occur, the AL101 will back off slots. Retry on Excessive Collision. 0: Normal collision handling. 1: Retry transmission after 16 consecutive collisions. Reference Only / Allayer Communications ...

Page 51

... SGRAM Select Mbit/s SGRAM 1: 16 Mbit/s SGRAM Back Pressure Control. 0: Carrier based. 1: Collision based. External Table Enable. 0: Disable 1: Enable Table Size Selection 16K 1: Multicast/Broadcast frame forward to CPU only. 0: Flow control multicast. 1: Flow control broadcast. Reference Only / Allayer Communications DESCRIPTION 51 ...

Page 52

... PHY’s Data Rate Status Register Bit Number. PHY’s Operating Duplex Mode Status Register Bit Number. Bit should be set at 0. Monitored Port ID. Snooping Port ID for Incoming Frame Flow. Snooping Port ID for Outgoing Frame Flow. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION 52 ...

Page 53

... If the uplink is a trunk, then the bits should read [100][trunk number]. The trunk number is numbered [Dev_ID][Trunk_ID]. If the local port is an uplink port, the uplink ID should be its own port ID. Any frame with unlearned SA will then be filtered. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION 53 ...

Page 54

... Member. Broadcast frames received from the port will be forwarded to the CPU port in addition to other member ports specified in the VLAN Map register of the port (excluding the source port). Learning Disable. 0: Source address from this port will be learned. 1: Source address from this port will not be learned. Reference Only / Allayer Communications 54 ...

Page 55

... Selects master mode. When the AL101 is in this mode, it will set the PHY capability advertisement register. The link will auto-negotiate to the highest capability. 0010: Selects slave mode. When the AL101 is in this mode, the PHY will set the PHY capability advertisement register. The link will auto-negotiate to the highest capability. ...

Page 56

... This bit is not relevant when MDIO is enabled. When MDIO is disabled, this bit forces the port into link up or link down state. 0: Link down. 1: Link up. 100 Full Duplex Mode. 100 Half Duplex Mode. 10 Full Duplex Mode. 10 Half Duplex Mode. Reference Only / Allayer Communications DESCRIPTION 56 ...

Page 57

... Non-member port. 1: Member port. Dev1Map Port VLAN Map corresponding to the port7~port0 of the device with Dev_ID of 01. 0: Non-member port. 1: Member port. Dev0Map Port VLAN Map corresponding to the port7~port0 of the device with Dev_ID of 00. 0: Non-member port. 1: Member port. Reference Only / Allayer Communications DESCRIPTION 57 ...

Page 58

... Trunk 4 Trunk Port of Trunk 4 00: Port 0, 01: Port 1 10: Port 2, 11: Port 3 Trunk 3 Trunk Port of Trunk 3 00: Port 4, 01: Port 5 10: Port 6, 11: Port 7 Trunk 2 Trunk Port of Trunk 2 00: Port 0, 01: Port 1 10: Port 2, 11: Port 3 Reference Only / Allayer Communications DESCRIPTION 58 ...

Page 59

... Device is ready to be programmed by the CPU. EEPROM Checksum Error. SGRAM Initialization Done. SRAMinit SRAM Initialization Done. REGinit Register Initialization Done. Traffic Counter. Reserved Chip ID 0000: AL101 Port Link Status. 0: Normal 1: Fail Port PHY Status. 0: Normal 1: Error Port Security Violation. 0: Normal 1: Violation ...

Page 60

... False Carrier Status. 0: Normal 1: False carrier experienced. Transmit Queue Underflow Status. 0: Normal 1: Underflow experienced. Frame Time Out. 0: Normal 1: Frame time out experienced. Port Operating Mode. 00: 10Mb half duplex. 01: 10Mb full duplex. 10: 100Mb half duplex. 11: 100Mb full duplex. Reference Only / Allayer Communications 60 ...

Page 61

... Write: MAC address delete. 101: Reserved 110: Reserved 111: Reserved External MAC address table read. If ResType = 011 and Operation = 0 0: On-chip address table read. 1: Off-chip address table read. The address of the entry within the accessed resource. Reference Only / Allayer Communications DESCRIPTION 61 ...

Page 62

... Table 40: Indirect Resource Access Data IV Register (Register 46) BIT NAME 15~0 IRAData BIT NAME 15~8 CheckSum 7~0 Reserved 5/00 Indirect Resource Access Data 1. Indirect Resource Access Data 2. Indirect Resource Access Data 3. Indirect Resource Access Data 4. Table 41: Checksum (Register 47) Checksum value of AL101 register contents. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 62 ...

Page 63

... RMII Receive Timing Diagram 5/00 Table 42: RMII Transmit Timing DESCRIPTION t txev t tdv DATA DATA DATA Table 43: RMII Receive Timing DESCRIPTION t t rxds rxdh DATA DATA DATA Reference Only / Allayer Communications MIN TYP MAX txev DATA DATA DATA MIN TYP MAX 3 - ...

Page 64

... SYMBOL t Setup time roxs t Hold time roxh Note: Test condition load. RICLK RID Figure 13 RoX Bus Timing 5/00 Table 44: RoX Bus Timing DESCRIPTION MIN t t roxs roxh Reference Only / Allayer Communications TYP MAX UNIT ...

Page 65

... PHY Management Read Timing Table 46: PHY Management (MDIO) Write Timing SYMBOL t MDC high time ch t MDC low time cl t MDC period mc t MDIO output delay d 5/00 DESCRIPTION MIN DESCRIPTION MIN Reference Only / Allayer Communications TYP MAX - - - - - - - - - - - - - - - TYP MAX - - ...

Page 66

... CKE setup time CKS t Clock low level width CL t PBCS#, PBRAS#, PBWE# setup time CS t Precharge command period RP t Auto-refresh to auto-refresh period RC 5/ Table 47: SGRAM Refresh Timing DESCRIPTION Reference Only / Allayer Communications t d MIN TYP MAX UNIT 3 ...

Page 67

... PBCLK CKH CKS CKE Precharge NOP Command BANK t Address RP Don't Care Figure 16 SGRAM Refresh Timing 5/00 t CHI Auto NOP Refresh t RC Reference Only / Allayer Communications t CL Auto Active NOP Refresh t RC BANK ROW 67 ...

Page 68

... OH t Active to precharge command RAS period t Active to read delay RCD Note: This timing requirement is for a SGRAM running at CAS Latency 2. Typically a -8 speed grade SGRAM needs to be used. 5/00 Table 48: SGRAM Read Timing DESCRIPTION Reference Only / Allayer Communications MIN TYP MAX - - 2 ...

Page 69

... Figure 17 SGRAM Read Timing 5/ CHI NOP READ NOP NOP BANK Dout Dout m m CAS Latency 256 location within the same row (Bank 0) Reference Only / Allayer Communications BURST NOP NOP NOP TERM. Dout Dout Dout Dout m m+1 m+2 m ...

Page 70

... Data in setup time DS t Active to precharge command RAS period t Active to read delay RCD Note: This timing requirement is for a SGRAM running at CAS Latency 2. Typically a -8 speed grade SGRAM needs to be used. 5/00 Table 49: SGRAM Write Timing DESCRIPTION Reference Only / Allayer Communications MIN TYP MAX 2 ...

Page 71

... DS PBD t (Bank 0) RCD t RAS Figure 18 SGRAM Write Timing 5/ NOP write NOP NOP BANK Din Din Din Din m m+1 m+2 m+3 256 location within the same row (Bank 0) Reference Only / Allayer Communications BURST NOP NOP NOP TERM. Din Din m m-1 Don't Care Undefined 71 ...

Page 72

... Input current-low (With no pull-up or pull-down) Vih Input high voltage Vil Input low voltage Icc Supply current 5/00 Table 50: Maximum Ratings Table 51: Recommended Operation Conditions Table 52: DC Electrical Characteristics DESCRIPTION Reference Only / Allayer Communications -0. 3.6V -0.3 ~ Vcc + 0.3V -0.3 ~ Vcc + 0.3V -0.6V to 6.0V -0.6 to Vcc5 + 0.3V -0.6 to Vcc5 + 0. - +150 C 3.3V ± 0.3V ...

Page 73

... AL101 Mechanical Data 256 PQFP Package 3.23 ± 0.07 0.25 min. Figure 19 AL101 Mechanical Dimensions 5/00 25.2 28.00 ± 0.10 30.6 ± 0.15 Reference Only / Allayer Communications 0.18 ± 0.04 0.40 4.07 max. 0.60 ± 0.10 1.30 ± 0.10 0.25 73 ...

Page 74

... Appendix I (VLAN Mapping Work Sheet) PORT BIT 5/00 Reference Only / Allayer Communications 74 ...

Page 75

... Appendix II (Port to Trunk Port Assignment Work Sheet) TRUNK / PORT 7 TRUNK 1 6 BITS TRUNK 0 2 BITS 5/00 BIT/ VALUE Reference Only / Allayer Communications 75 ...

Page 76

... Note: This is only a partial list of memory components that can be used in Allayer devices. The AL101 uses Frame Buffer SGRAM chips that require 32-bit wide SGRAM or SDRAM, that is 75 MHz or faster with CAS latency 2. The AL101 uses MAC Table Memory SSRAM chips that require Sync Burst pipelined SSRAM, 75 MHz or faster ...

Page 77

... Corrected register numbers in appendix II. 4. Corrected register numbers in tables 16, 17 and 19. 5. Added new RMII transmit and RMII receive tables and diagrams. Prelim 1.3 to 1.4 (1/31/00) 1. Pin RICLK was numbered 225 when the correct number is 255. Prelim 1.4 to Rev. 1.0 1. Fully released document. 5/00 Reference Only / Allayer Communications 77 ...

Page 78

... Port 100 Mbps + 2 Port 1 Gbps Managed Switch with RoX 17 A Address Aging 22 Address Learning 21 AL101 EEPROM Mapping 43 AL101 Mechanical Data 73 AL101 Overview 5 AL101 Pin Diagram (Top View) 6 Appendix I (VLAN Mapping Work Sheet) 74 Appendix II (Port to Trunk Port Assignment Work Sheet) 75 Appendix III (Suggested Memory Components Broadcast Storm Control 19 C ...

Page 79

... Typical Write Operation 40 U Uplink Port 35 V Vendor Specific PHY Register (Register 05) 52 VLAN Mapping for 16 Port Switch (Device 0) 23 VLAN Mapping for 16 Port Switch (Device 1) 24 VLAN Mapping for Port Based Load Balancing Trunk 30, 32 VLAN Set Up Example 22 5/00 Reference Only / Allayer Communications 79 ...

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