AL104 Allayer Communications, AL104 Datasheet

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AL104

Manufacturer Part Number
AL104
Description
Manufacturer
Allayer Communications
Datasheet

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Figure 1
8 PORT LOW COST 10/100 SWITCH WITH RMII
Product Description
The AL104 is an eight-port 10/100 Mbit/s dual speed Ethernet switch. A low-cost Fast Ethernet
switch can be implemented using the AL104 with low-cost SGRAM. The AL104 also supports
VLAN and multiple port aggregation trunks.
System Block Diagram
Supports 8 10/100 Mbit/s Ethernet ports
with RMII interface
Capable of trunking up to 800 Mbit/s link
Trunk fail-over feature
Full- and half-duplex mode operation
Speed auto-negotiation through MDIO
Built-in storage of 1K MAC addresses
expandable up to 17K
Design to utilize low-cost SGRAM
Serial EEPROM interface for low-cost
system configuration
Automatic source address learning
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
Reference Only / Allayer Communications
High Speed
Switch Fabric
Secure mode traffic filtering
Broadcast storm control
Port monitoring support
IEEE 802.3x flow control for full-duplex
operation
Optional backpressure flow control support
for half-duplex operation
Supports store-and-forward mode switching
VLAN support
3.3V operation
Packaged in 208-pin PQFP
Switch
Controller
Address
Control
Address
Table
EEPROM
Interface
Address
Table
Expansion
Buffer
Manager
Revision 1.0
AL104

Related parts for AL104

AL104 Summary of contents

Page 1

... Automatic source address learning Product Description The AL104 is an eight-port 10/100 Mbit/s dual speed Ethernet switch. A low-cost Fast Ethernet switch can be implemented using the AL104 with low-cost SGRAM. The AL104 also supports VLAN and multiple port aggregation trunks. 10/100 MAC ...

Page 2

... Life Support Applications Allayer Communications products are not designed for use in life support appliances, systems, or devices where malfunctions can be reasonably expected to result in personal injury. 9/00 Reference Only / Allayer Communications ...

Page 3

... AL104 Overview ..................................................................................................... 5 2. Pin Descriptions....................................................................................................... 7 3. Functional Description........................................................................................... 16 3.1 Data Reception............................................................................................... 16 3.1.1 Illegal Frame Length.............................................................................. 16 3.1.2 Long Frames .......................................................................................... 16 3.1.3 Frame Filtering....................................................................................... 16 3.2 Frame Forwarding.......................................................................................... 17 3.2.1 Broadcast Storm Control........................................................................ 17 3.2.2 Frame Transmission............................................................................... 18 3.2.3 Frame Generation................................................................................... 18 3.3 Half Duplex Mode Operation ........................................................................ 18 3.4 Secure Mode Operation ................................................................................. 18 3 ...

Page 4

... Register Descriptions............................................................................................. 37 5. System Configuration Registers ............................................................................ 40 6. Timing Requirements............................................................................................. 52 7. Electrical Specifications ........................................................................................ 61 8. AL104 Mechanical Data........................................................................................ 62 9. Appendix I (VLAN Mapping Work Sheet) ........................................................... 63 10. Appendix II (Port to Trunk Port Assignment Work Sheet) ................................... 64 11. Appendix III (Suggested Memory Components)................................................... 65 9/00 Reference Only / Allayer Communications ...

Page 5

... With this method of flow control, the switch will generate a jam signal when the receive buffer is full and the sending station will not start to transmit until the line is clear. In the full-duplex mode, the AL104 utilizes IEEE 802.3x as the flow control mechanism. ...

Page 6

... ETD13 ETD12 40 ETD11 ETD10 ETD9 VCC M2CRS 45 GND M2TXD1 VCC M2TXD0 M2TXEN 50 M2RXD0 M2RXD1 52 53 Figure 2 AL104 Pin Diagram 9/00 1 Reference Only / Allayer Communications 157 156 PBD29 155 PBD30 PBD31 PBCLK VCC GND GND 150 M7RXD1 M7RXD0 M7TXEN M7TXD0 145 VCC ...

Page 7

... M0RXD1 are sampled by the rising edge of M0RXCLK. I Receive Data Valid. Used only for MII mode. I Receive Clock. 50 MHz RMII clock for RMII mode. I Receive Data Error. Used only for MII mode. I Carrier Sense. I Collision Detect. Used only for MII mode. Reference Only / Allayer Communications DESCRIPTION 7 ...

Page 8

... Signal M3TXEN, and M3TXD0 through M3TXD1 are clocked out by the rising edge of M3RXCLK. O Transmit Enable. Synchronous to the transmit clock. I Receive Data - NRZ data from the transceiver. For RMII interface, signal M3RXD0 through M3RXD3 are sampled by the rising edge of M3RXCLK. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION DESCRIPTION 8 ...

Page 9

... Signal M5TXEN, and M5TXD0 through M5TXD1 are clocked out by the rising edge of M3RXCLK. O Transmit Enable. Synchronous to the transmit clock. I Receive Data - NRZ data from the transceiver. For RMII interface, signal M5RXD0 through M5RXD3 are sampled by the rising edge of M3RXCLK. I Carrier Sense. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION 9 ...

Page 10

... Signal M7TXEN, and M7TXD0 through M7TXD1 are clocked out by the rising edge of M3RXCLK. O Transmit Enable. Synchronous to the transmit clock. I Receive Data - NRZ data from the transceiver. For RMII interface, signal M7RXD0 through M7RXD3 are sampled by the rising edge of M3RXCLK. I Carrier Sense. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION 10 ...

Page 11

... SGRAM this pin is PBA 9. 192 O SGRAM Address. For 16 M SGRAM, this pin is PBA9 and for 8-Mbit SGRAM this pin is PBA SGRAM Address. For 16 M SGRAM, this pin is PBA8 and for 8-Mbit SGRAM this pin is no connect. Reference Only / Allayer Communications DESCRIPTION 11 ...

Page 12

... O Chip Select. Enables and disables the command decoder of the SGRAM. 203 O SGRAM Row Address Strobe. 208 O SGRAM Column Address Strobe. 207 O Write Enable. 153 O System Clock Output to Drive the SGRAM. I/O 29 I/O SRAM Data Bus Reference Only / Allayer Communications DESCRIPTION 12 ...

Page 13

... Output Enable. Active low. This enables data I/O output driver System Clock Output. Table 11: EEPROM Interface PIN NUMBER 2 3 Table 12: PHY Management Interface PIN NUMBER 76 77 Reference Only / Allayer Communications I/O DESCRIPTION I/O EEPROM Serial Data Input and Output. O EEPROM Serial Clock. I/O DESCRIPTION O PHY Management Clock. I/O PHY Management Data Input and Output ...

Page 14

... Table 13: Miscellaneous Pins PIN NUMBER 78 79 205 105 Table 14: Power Interface PIN NUMBER 175, 190, 206 182, 197, 204 106 Reference Only / Allayer Communications I/O DESCRIPTION I Reset I Test Mode Pin. This pin should be grounded for normal operation MHz System clock Connect. Must be left unconnected ...

Page 15

... MXCOL 10/100 MAC 32 PBD[n] 9 PBA[n] PBBA Buffer PBCS Manager PBRAS PBCAS PBWE PBDSF PBDQM PBCLK Figure 3 AL104 Interface Block Diagram 9/00 High Speed Switch Fabric Reference Only / Allayer Communications Switch Controller SRAM Address Interface Control Address Table PHY Management Management Information ...

Page 16

... Long Frames The AL104 can handle frame size up to 1536 bytes. All frames longer than 1536 bytes will be discarded. If the port continues to receive data after the 1536 If the port is in half-duplex mode, the port will no longer be able to transmit or receive data during the long frame reception ...

Page 17

... Flood Control option (System Configuration Register 00). If Flood Control is disabled, the frame will be forwarded to all ports (except the receiving port) within the same VLANs of the receiving port. If the Flood Control option is enabled, the AL104 will forward the frame only to the uplink port specified at the receiving port. ...

Page 18

... IEEE back off algorithm. 3.4 Secure Mode Operation The AL104 provides security support on a per port basis. Whenever the secure mode is enabled, the port will stop learning new addresses. The address table of each port will remain unchanged. In this mode of operation, the address lookup table will freeze and no additional new address will be learned ...

Page 19

... The AL104 will then check for error and security violations, and perform a SA search. If there is no error or security violation, the AL104 will store the source address in the address lookup table. If the SA has been previously stored in another port’s SA table, the AL104 will delete the SA from the previously stored location. ...

Page 20

... For example, let’s assume we want to set up two VLAN groups in an 8-port switch; Group 1 consists of and 6. Group 2 consists of and 7. The completed VLAN bit maps are shown in Table 15. PORT BIT 9/00 Table 15: VLAN Map for an 8 Port Switch Reference Only / Allayer Communications ...

Page 21

... AL104 will automatically shift the load from the port with the lost link to the next available port. This option is available for MAC address based loading trunk only. Once the port with a lost link recovers and links up, the AL104 will return to the original trunk setting. ...

Page 22

... Trunk Port Assignment The maximum number of trunks for the AL104 is two. The Port Configuration I registers provide the ability to designate a port member of a trunk. The trunk can consist four trunk ports. A trunk group must consist of either the top four ports or the bottom four ports, for example a trunk can consist of port 0 through port 3 or port 4 through port 7. Each trunk port’ ...

Page 23

... All the other ports are set up similarly. Bits 15 through 8 are reserved and should be set to ‘0’ for all VLAN mapping registers. Table 16: VLAN Mapping for Port Based Load Balancing Trunk PORT BIT 9/00 32.2= 1, 32.3 =1 33.2= 0, 33.3 =1 34.2= 1. 34.3 =0 35. Reference Only / Allayer Communications ...

Page 24

... MAC Based Load Balancing For MAC address based load balancing, there is no need to assign a port to a trunk port. The AL104 dynamically assigns MAC addresses to the trunk port. MAC address based trunks can consist of two, three, or four trunk ports. The bits are chosen for their randomness. The statistically random bits will ensure good load balancing among all trunk-ports ...

Page 25

... Select MAC address loading by setting bit 00.3 to “1.” Table 17: VLAN Mapping for MAC Based Loading Trunk PORT BIT Note: All bits are set to “1” except the ports themselves. 9/ Reference Only / Allayer Communications ...

Page 26

... Collision based backpressure is generated by the AL104, only when the switch port receives a frame. The AL104 will cease to jam the line, when the line is idle. The AL104 supports collision- based backpressure for customers that prefer collision-based backpressure. ...

Page 27

... Queue Management The AL104 ports have an advanced queue management algorithm for optimal switching performance. All frames received by AL104 are stored into the shared memory. If the frame is unicast type, the location of the frame in the buffer is then passed to the destination output queue manager ...

Page 28

... The transmit data is clocked out by the rising edge of the reference clock. Prior to any data transaction, AL104 will output 2-bits of “0” as preamble signal and then after the preamble, a “11” signal is used to indicate the start of the frame. ...

Page 29

... For a read operation, the AL104 will output a ”0” to indicate a read operation after the start of the frame indicator. Following the “10” read signal will be the 5-bit ID address of the PHY device and the 5-bit register address ...

Page 30

... Unfortunately, such register addresses are vendor specific. The AL104 provides a register (register 05) to specify the register address of the PHY for the AL104 to read. The AL104 will read from that register and configure the port operation accordingly. ...

Page 31

... The EEPROM contains configuration and initialization information, which will be accessed at power up or reset. If the reset pin is held low, the AL104’s EEPROM interface will go into a high impedance state. This feature is very useful for reprogramming the EEPROM during installation or reconfiguration. The EEPROM can be reprogrammed by an external parallel port. For reprogramming using a parallel port, a signal is used to hold the RESET pin low ...

Page 32

... Write Cycle Timing The EECLK is an output from the AL104 while EEDIO is a bi-directional signal. When accessing the EEPROM, the reset pin has to be held low or initialization of the AL104 must be finished before a writing operation can begin. Device Start Address Figure 6 EEPROM Write Cycle 3 ...

Page 33

... The customer can now program the AL104 as an EEPROM. The read and write timing is the same as an EEPROM. Because you read as well as write to the AL104, the registers status can be read from the AL104. This will serve as a very useful tool for diagnostic of an unmanaged switch. ...

Page 34

... BIT Port ID 000XXX or Trunk ID 100YYY Table 19: AL104 EEPROM Mapping System Configuration I System Configuration II System Configuration III Reserved (Value must be 0000 0001 0100) Reserved Vendor Specific PHY Port Monitoring Configuration Reserved Reserved Reserved Reserved Reserved ...

Page 35

... Table 19: AL104 EEPROM Mapping (Continued) 20-21 22-23 24-25 26-27 28-29 2A-2B 2C-2D 2E-2F 30-31 32-33 34-35 36-37 38-39 3A-3B 3C-3D 3E-3F 40-41 42-43 44-45 46-47 48-49 4A-4B 4C-4D 4E-4F 50-51 52-53 54-55 56-57 58-59 5A-5B 5C-5D 9/00 Port 1 Configuration II Port 2 Configuration I ...

Page 36

... Table 19: AL104 EEPROM Mapping (Continued) 5E-5F 60-61 62-63 64-65 66-67 68-69 6A-6B 6C- 70-77 78-7F 80-87 88-8F 90-97 98-9F A0-A7 A8-AF B0-B7 B8-BF C0-C7 C8-CF D0-D7 D8-DF E0-E7 E8-EF F0-F7 F8-FF 9/00 Port 0 to Trunk Port Assignment Port 1 to Trunk Port Assignment ...

Page 37

... During transmit, the frame is retrieved from the buffer pool and forwarded to the destination port. The AL104 is designed to use 8 Mbit SGRAM or 16 Mbit SGRAM to achieve low cost and high performance. The SGRAM is accessed in Page Burst Access Mode for very high-speed access. This burst mode is repeatedly sent to the same column ...

Page 38

... Port 3 VLAN Map Reserved Port 4 VLAN Map Reserved Port 5 VLAN Map Reserved Port 6 VLAN Map Reserved Port 7 VLAN Map Miscellaneous Register Port 0 to Trunk Port Assignment Reference Only / Allayer Communications 22,23 24,25 26,27 28,29 2A,2B 2C,2D 2E,2F 30,31 32,33 34,35 36,37 ...

Page 39

... Port 5 Operation Status Port 6 Operation Status Port 7 Operation Status Indirect Resource Access Command Indirect Resource Access Data I Indirect Resource Access Data II Indirect Resource Access Data III Indirect Resource Access Data IV Checksum Reference Only / Allayer Communications 5E,5F 60,61 62,63 64,65 66,67 68,69 6A,6B 6C-71 ...

Page 40

... Port Outgoing Frame Flow Monitoring Enable Control. 0: Disable 1: Enable Output Queue Watermark. Watermark selection for output queues and multicast queue full conditions. 16 Mbit/s SGRAM 00:128; 01:512; 10:768; 11:Test Mode. 8 Mbit/s SGRAM 00:64; 01:256; 10:384; 11:Test Mode. Reference Only / Allayer Communications DESCRIPTION 40 ...

Page 41

... Disable. Device will perform the IEEE standard exponential back off algorithm when a collision occurs. 1: Enable. When collisions occur, the AL104 will back off slots. Retry on Excessive Collision. 0: Normal collision handling. 1: Retry transmission after 16 consecutive collisions. Select the Bits Position for MAC Address to Trunk Assignment. ...

Page 42

... According to BpIPGSel value. IPG Control. 0: IPG = 96BT 1: IPG = 64BT Reserved SGRAM Select Mbit SGRAM Mbit SGRAM. Back Pressure Control. 0: Carrier based. 1: Collision based. Backpressure IPG Select. 00: 48BT; 01: 56BT; 10:65BT; 11: 72BT. Reserved 0: Flow control multicast. 1: Flow control multicast/broadcast. Reference Only / Allayer Communications DESCRIPTION 42 ...

Page 43

... Setting this bit to “1” will reverse the PHY ID/port number of the switch. PHY’s Operation Status Register Number. PHY’s Data Rate Status Register Bit Number. PHY’s Operating Duplex Mode Status Register Bit Number. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION 43 ...

Page 44

... MAC address checking. 1: Security on. The frames received from the port with unknown source MAC address or with source MAC address learned previously from another port will be discarded. Reserved (Must set to 0) Reference Only / Allayer Communications DESCRIPTION DESCRIPTION 44 ...

Page 45

... This bit is not relevant when MDIO is enabled. When MDIO is disabled, this bit forces the port into link up or link down state. Force 100 Full Duplex Mode. Force 100 Half Duplex Mode. Force 10 Full Duplex Mode. Force 10 Half Duplex Mode. Reference Only / Allayer Communications DESCRIPTION 45 ...

Page 46

... Port VLAN Corresponding to the Port 3. 0: Non-member port. 1: Member port. Port VLAN Corresponding to the Port 2. 0: Non-member port. 1: Member port. Port VLAN Corresponding to the Port 1. 0: Non-member port. 1: Member port. Port VLAN Corresponding to the Port 0. 0: Non-member port. 1: Member port. Reference Only / Allayer Communications DESCRIPTION 46 ...

Page 47

... Allow link fail over for trunking. Enable Port MAC Based Trunking Option. 0: Disable 1: Enable MAC Based Trunk Port Mapping for Trunk 1. 0: Non-trunk port. 1: Trunk port. MAC Based Trunk Port Mapping for Trunk 0. 0: Non-trunk port. 1: Trunk port. Reference Only / Allayer Communications DESCRIPTION 47 ...

Page 48

... SGRAM Initialization Done. 0: SGRAM initialization is not done. 1: SGRAM initialization is done. SRAM Initialization Done. 0: SRAM initialization is not done. 1: SRAM initialization is done. Register Initialization Done. 0: AL104 register initialization is not done. 1: AL104 register initialization is done. Traffic Counter. 0000: Minimum traffic. 1111: Maximum traffic. Reserved 0101: AL104 ...

Page 49

... Normal 1: Jabber experienced. Port Late Collision Status. 0: Normal 1: Late collision experienced. Port Transmit Pause Status transmit pause experienced. 1: Transmit pause experienced. Port Carrier Sense Loss During Transmission Status carrier sense loss experienced. 1: Carrier sense loss experienced. Reference Only / Allayer Communications DESCRIPTION 49 ...

Page 50

... Indirect Resource Access Command Register (Register 42) Indirect resource access command allows the management (Reverse EEPROM Method) to access other resources other than the AL104 register values. PHY registers, both internal and external MAC address tables, and SGRAM contents can be accessed using this command. ...

Page 51

... The address of the entry within the accessed resource. Indirect Resource Access Data 1. Indirect Resource Access Data 2. Indirect Resource Access Data 3. Indirect Resource Access Data 4. Table 39: Check Sum (Register 47) Check Sum Value of AL104 Register Contents. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION ...

Page 52

... Note: Delays are assuming 10pf loading on the output pins. TXCLK TXEN TXD Figure 9 RMII/MII Transmit Timing Diagram 9/00 Table 40: MII Transmit Timing DESCRIPTION Table 41: RMII Transmit Timing DESCRIPTION t txev t tdv DATA DATA DATA Reference Only / Allayer Communications MIN TYP MAX MIN TYP MAX ...

Page 53

... RX_DV, RXD, RX_ER hold time. rxdh RXCLK RXDV RXD Figure 10 RMII/MII Receive Timing Diagram 9/00 Table 42: MII Receive Timing DESCRIPTION Table 43: RMII Receive Timing DESCRIPTION t t rxds rxdh DATA DATA DATA Reference Only / Allayer Communications MIN TYP MAX MIN TYP MAX ...

Page 54

... MDC low time cl t MDC period mc t MDIO setup time ms t MDIO hold time mh MDC MDIO Figure 11 PHY Management Read Timing 9/00 DESCRIPTION MIN 420 420 840 Reference Only / Allayer Communications TYP MAX UNIT 425 430 ns 425 430 ns 850 860 ...

Page 55

... SYMBOL t MDC high time ch t MDC low time cl t MDC period mc t MDIO output delay d MDC MDIO Figure 12 PHY Management Write Timing 9/00 DESCRIPTION MIN 420 420 840 Reference Only / Allayer Communications TYP MAX UNIT 425 430 ns 425 430 ns 850 860 ...

Page 56

... Precharge command period RP t Auto refresh to auto refresh period RC PBCLK CKH CKS CKE Precharge NOP Command BANK t Address RP Don't Care Figure 13 SGRAM Refresh Timing 9/00 Table 46: SGRAM Refresh Timing DESCRIPTION t CHI Auto NOP Refresh t RC Reference Only / Allayer Communications MIN TYP MAX 3 3 ...

Page 57

... Data out hold time OH t Active to precharge command RAS period t Active to read delay RCD Note: This timing requirement is for a SGRAM running at CAS Latency 2. Typically a -8 speed grade SGRAM needs to be used. 9/00 Table 47: SGRAM Read Timing DESCRIPTION Reference Only / Allayer Communications MIN TYP MAX - - 2 ...

Page 58

... PBD t (Bank 0) RCD t RAS Figure 14 SGRAM Read Timing 9/ CHI NOP READ NOP NOP BANK Dout Dout m m CAS Latency 256 location within the same row (Bank 0) Reference Only / Allayer Communications BURST NOP NOP NOP TERM. Dout Dout Dout Dout m m+1 m+2 m ...

Page 59

... Data in setup time DS t Active to precharge command RAS period t Active to read delay RCD Note: This timing requirement is for a SGRAM running at CAS Latency 2. Typically a -8 speed grade SGRAM needs to be used. 9/00 Table 48: SGRAM Write Timing DESCRIPTION Reference Only / Allayer Communications MIN TYP MAX 2 ...

Page 60

... RCD t RAS Figure 15 SGRAM Write Timing 9/ NOP write NOP NOP BANK Din Din Din Din m m+1 m+2 m+3 256 location within the same row (Bank 0) Reference Only / Allayer Communications BURST NOP NOP NOP TERM. Din Din m m-1 Don't Care Undefined 60 ...

Page 61

... Input high voltage Vil Input low voltage Icc Supply current 9/00 Table 49: Maximum Ratings Table 50: Recommended Operation Conditions Table 51: DC Electrical Characteristics DESCRIPTION Reference Only / Allayer Communications -0. 3.6V -0. 6.0V -0.3 ~ Vcc + 0.3V -0.3 ~ Vcc + 0.3V -0.6V to 6.0V -0.6 to VccM + 0.3V -0.6 to VccM + 0. ...

Page 62

... AL104 Mechanical Data 208-Pin PQFP Package 3.23 ± 0.12 0.10 min. Figure 16 AL104 Mechanical Dimensions 9/00 25.5 28.00 ± 0.13 30.6 ± 0.3 Reference Only / Allayer Communications 0.20 ± 0.05 0.50 ± 0.1 3.68 max. 0.10 0.50 ± 0.20 1.30 ± 0.20 ...

Page 63

... Appendix I (VLAN Mapping Work Sheet) PORT BIT 9/ Reference Only / Allayer Communications 63 ...

Page 64

... Appendix II (Port to Trunk Port Assignment Work Sheet) TRUNK / PORT TRUNK 1 BITS 3, 2 TRUNK 0 BITS 1, 0 9/00 BIT/ VALUE Reference Only / Allayer Communications 64 ...

Page 65

... Note: This is only a partial list of memory components that can be used in Allayer devices. The AL104 uses Frame Buffer SGRAM chips that require 32-bit wide SGRAM or SDRAM, that is 80 MHz or faster with CAS latency 2. The AL104 uses MAC Table Memory SSRAM chips that require Sync Burst pipelined SSRAM, 80 MHz or faster ...

Page 66

... Added new PHY management timing diagrams. 4. Added new RMII and MII timing diagrams. Rev. History Prelim. 1.3a to Prelim. 1.4 1. Cleaned up SGRAM write and read tables. 2. Corrected queue management information. Rev. History (Prelim. 1.4 to Rev. 1.0) 1. Fully released document. 9/00 Reference Only / Allayer Communications 66 ...

Page 67

... A Address Learning 18 AL104 EEPROM Mapping 34 AL104 Interface Block Diagram 15 AL104 Mechanical Data 62 AL104 Overview 5 AL104 Pin Diagram 6 Appendix I (VLAN Mapping Work Sheet) 63 Appendix II (Port to Trunk Port Assignment Work Sheet) 64 Appendix III (Suggested Memory Components Broadcast Storm Control 17 C Check Sum (Register 47) 51 ...

Page 68

... U Uplink Port 27 V Vendor Specific PHY register (Register 05) 43 VLAN Mapping for MAC Based Loading Trunk 25 VLAN Mapping for Port Based Load Balancing Trunk 23 VLAN Support 19 W Write Cycle Timing 32 9/00 Reference Only / Allayer Communications 68 ...

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