PPC8548EVTAUJA Freescale Semiconductor, Inc, PPC8548EVTAUJA Datasheet

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... For specific PVR and SVR numbers, refer to the MPC8548E PowerQUICC™ III Integrated Processor Family Reference Manual. © Freescale Semiconductor, Inc., 2009. All rights reserved. Document Number: MPC8548EEC Rev. 6, 12/2009 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 ...

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Overview DDR/DDR2/ DDR SDRAM Memory Controller Flash Local Bus Controller SDRAM GPIO Programmable Interrupt IRQs Controller (PIC) Serial DUART Controller Controller MII, GMII, TBI, eTSEC RTBI, RGMII, 10/100/1Gb ...

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Performance monitor facility that is similar to, but separate from, the MPC8548E performance monitor The e500 defines features that are not implemented on this device. It also generally defines some features that this device implements more specifically. An understanding ...

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Overview – simultaneous open pages for DDR2 — Contiguous or discontiguous memory mapping — Read-modify-write support for RapidIO atomic increment, decrement, set, and clear transactions — Sleep mode support for self-refresh SDRAM — On-die termination support when ...

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AESU—Advanced Encryption Standard unit – Implements the Rijndael symmetric key cipher – ECB, CBC, CTR, and CCM modes – 128-, 192-, and 256-bit key lengths — AFEU—ARC four execution unit – Implements a stream cipher compatible with the RC4 ...

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Overview – Dedicated single data rate SDRAM controller — Parity support — Default boot ROM chip select with configurable bus width (8, 16 bits) • Four enhanced three-speed Ethernet controllers (eTSECs) — Three-speed support (10/100/1000 Mbps) — Four ...

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VRRP and HSRP support for seamless router fail-over – exact-match MAC addresses supported – Broadcast address (accept/reject) – Hash table match 512 multicast addresses – Promiscuous mode — Buffer descriptors backward compatible with ...

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Overview — Memory prefetching of PCI read accesses — Supports posting of processor-to-PCI and PCI-to-memory writes — PCI 3.3-V compatible — Selectable hardware-enforced coherency • Serial RapidIO™ interface unit — Supports RapidIO™ Interconnect Specification, Revision 1.2 — Both 1× and ...

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Single inbound doorbell message structure — Facility to accept port-write messages • PCI Express interface — PCI Express 1.0a compatible — Supports ×8, ×4, ×2, and ×1 link widths — Auto-detection of number of connected lanes — Selectable operation ...

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Electrical Characteristics 2 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8548E. This device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are ...

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Table 1. Absolute Maximum Ratings Characteristic Storage temperature range Notes: 1. Functional and tested operating conditions are given in functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to ...

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Electrical Characteristics Table 2. Recommended Operating Conditions (continued) Characteristic Junction temperature range Notes: 1. This voltage is the input to the filter discussed in at the AV pin, which may be reduced from Caution: MV must not ...

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Output Driver Characteristics Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Driver Type Local bus interface utilities signals PCI signals DDR signal DDR2 signal TSEC/10/100 signals DUART, system control, JTAG ...

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Power Characteristics In order to guarantee MCKE low during power-up, the above sequencing for GV is required. If there is no concern about any of the DDR signals being indeterminate state during power-up, then the sequencing for ...

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Input Clocks This section discusses the timing for the input clocks. 4.1 System Clock Timing Table 5 provides the system clock (SYSCLK) AC timing specifications for the MPC8548E. At recommended operating conditions (see Parameter/Condition SYSCLK frequency SYSCLK cycle time ...

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Input Clocks 4.3 eTSEC Gigabit Reference Clock Timing Table 6 provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for the MPC8548E. Table 6. EC_GTX_CLK125 AC Timing Specifications Parameter/Condition EC_GTX_CLK125 frequency EC_GTX_CLK125 cycle time EC_GTX_CLK125 rise and fall time ...

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Platform to FIFO Restrictions Please note the following FIFO maximum speed restrictions based on platform speed. For FIFO GMII mode: FIFO TX/RX clock frequency ≤ platform clock frequency/4.2 For example, if the platform frequency is 533 MHz, the FIFO ...

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RESET Initialization 5 RESET Initialization This section describes the AC electrical specifications for the RESET initialization timing requirements of the MPC8548E. Table 8 provides the RESET initialization AC timing specifications for the DDR SDRAM component(s). Table 8. RESET Initialization Timing ...

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DDR and DDR2 SDRAM This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8548E. Note that GV (typ) = 2.5 V for DDR SDRAM, and GV DD SDRAM. 6.1 DDR SDRAM DC ...

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DDR and DDR2 SDRAM Table 13 provides the recommended operating conditions for the DDR SDRAM controller when GV (typ Table 13. DDR SDRAM DC Electrical Characteristics for GV Parameter/Condition I/O supply voltage I/O reference voltage ...

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DDR SDRAM AC Electrical Characteristics This section provides the AC electrical characteristics for the DDR SDRAM interface. The DDR controller supports both DDR1 and DDR2 memories. DDR1 is supported with the following AC timings at data rates of 333 ...

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DDR and DDR2 SDRAM 6.2.2 DDR SDRAM Output AC Timing Specifications Table 19. DDR SDRAM Output AC Timing Specifications At recommended operating conditions. Parameter MCK[n] cycle time, MCK[ n ]/MCK crossing ADDR/CMD output setup with respect to MCK ...

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Table 19. DDR SDRAM Output AC Timing Specifications (continued) At recommended operating conditions. Parameter MDQS epilogue end Notes: 1. The symbols used for timing specifications follow the pattern of t inputs and t (first two letters of functional block)(reference)(state)(signal)(state) (DD) ...

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DDR and DDR2 SDRAM Figure 4 shows the DDR SDRAM output timing diagram.+ MCK MCK ADDR/CMD Write A0 MDQS MDQ[x] Figure 4. DDR SDRAM Output Timing Diagram Figure 5 provides the AC test load ...

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DUART This section describes the DC and AC electrical specifications for the DUART interface of the MPC8548E. 7.1 DUART DC Electrical Characteristics Table 20 provides the DC electrical characteristics for the DUART interface. Table 20. DUART DC Electrical Characteristics ...

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Enhanced Three-Speed Ethernet (eTSEC) 8 Enhanced Three-Speed Ethernet (eTSEC) This section provides the AC and DC electrical characteristics for the enhanced three-speed Ethernet controller. The electrical characteristics for MDIO and MDC are specified in Management Interface Electrical Characteristics.” 8.1 Enhanced ...

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Table 23. GMII, MII, RMII, TBI, RGMII, RTBI, and FIFO DC Electrical Characteristics Parameters Supply voltage 2.5 V Output high voltage (LV /TV = Min –1.0 mA) OH Output low voltage (LV /TV = Min, DD ...

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Enhanced Three-Speed Ethernet (eTSEC) A summary of the FIFO AC specifications appears in Table 24. FIFO Mode Transmit AC Timing Specification Parameter/Condition TX_CLK, GTX_CLK clock period TX_CLK, GTX_CLK duty cycle TX_CLK, GTX_CLK peak-to-peak jitter Rise time TX_CLK (20%–80%) Fall time ...

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RX_CLK t FIRH RXD[7:0] RX_DV RX_ER 8.2.2 GMII AC Timing Specifications This section describes the GMII transmit and receive AC timing specifications. 8.2.2.1 GMII Transmit AC Timing Specifications Table 26 provides the GMII transmit AC timing specifications. Table 26. GMII ...

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Enhanced Three-Speed Ethernet (eTSEC) Figure 8 shows the GMII transmit AC timing diagram. GTX_CLK TXD[7:0] TX_EN TX_ER 8.2.2.2 GMII Receive AC Timing Specifications Table 27 provides the GMII receive AC timing specifications. Table 27. GMII Receive AC Timing Specifications Parameter/Condition ...

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Figure 10 shows the GMII receive AC timing diagram. RX_CLK RXD[7:0] RX_DV RX_ER 8.2.3 MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. 8.2.3.1 MII Transmit AC Timing Specifications Table 28 provides the MII ...

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Enhanced Three-Speed Ethernet (eTSEC) Figure 11 shows the MII transmit AC timing diagram. TX_CLK TXD[3:0] TX_EN TX_ER 8.2.3.2 MII Receive AC Timing Specifications Table 29 provides the MII receive AC timing specifications. Table 29. MII Receive AC Timing Specifications Parameter/Condition ...

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Figure 13 shows the MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER 8.2.4 TBI AC Timing Specifications This section describes the TBI transmit and receive AC timing specifications. 8.2.4.1 TBI Transmit AC Timing Specifications Table 30 provides the TBI ...

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Enhanced Three-Speed Ethernet (eTSEC) Figure 14 shows the TBI transmit AC timing diagram. GTX_CLK TCG[9:0] 8.2.4.2 TBI Receive AC Timing Specifications Table 31 provides the TBI receive AC timing specifications. Table 31. TBI Receive AC Timing Specifications Parameter/Condition TSEC n ...

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Figure 15 shows the TBI receive AC timing diagram. TSEC n _RX_CLK1 RCG[9:0] TSEC n _RX_CLK0 8.2.5 TBI Single-Clock Mode AC Specifications When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant ...

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Enhanced Three-Speed Ethernet (eTSEC) A timing diagram for TBI receive appears in . RX_CLK t TRRH RCG[9:0] Figure 16. TBI Single-Clock Mode Receive AC Timing Diagram 8.2.6 RGMII and RTBI AC Timing Table 33 presents the RGMII and RTBI AC ...

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Figure 17 shows the RGMII and RTBI AC timing and multiplexing diagrams. GTX_CLK (At Transmitter) TXD[8:5][3:0] TXD[7:4][3:0] TX_CTL TX_CLK (At PHY) RXD[8:5][3:0] RXD[7:4][3:0] RX_CTL RX_CLK (At PHY) Figure 17. RGMII and RTBI AC Timing and Multiplexing Diagrams 8.2.7 RMII AC ...

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Enhanced Three-Speed Ethernet (eTSEC) Table 34. RMII Transmit AC Timing Specifications (continued) Parameter/Condition TSEC n _TX_CLK to RMII data TXD[1:0], TX_EN delay Note: 1. The symbols used for timing specifications follow the pattern of t inputs and t (first two ...

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Figure 19 provides the AC test load for eTSEC. Output Figure 20 shows the RMII receive AC timing diagram. TSEC n _TX_CLK RXD[1:0] CRS_DV RX_ER 9 Ethernet Management Interface Electrical Characteristics The electrical characteristics specified here apply to MII management ...

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Ethernet Management Interface Electrical Characteristics Table 36. MII Management DC Electrical Characteristics (continued) Parameter 1 Input high current (OV = Max Input low current (OV = Max 0 Note: 1. Note that ...

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Figure 21 shows the MII management AC timing diagram. MDC MDIO (Input) MDIO (Output) Figure 21. MII Management Interface Timing Diagram 10 Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the ...

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Local Bus Table 39 provides the DC electrical characteristics for the local bus interface operating 2.5 V DC. DD Table 39. Local Bus DC Electrical Characteristics (2.5 V DC) Parameter High-level input voltage Low-level input voltage 1 ...

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Table 40. Local Bus Timing Parameters (BV Parameter Local bus clock to output high impedance for LAD/LDP Notes: 1. The symbols used for timing specifications follow the pattern of t inputs and t (first two letters of functional block)(reference)(state)(signal)(state) timing ...

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Local Bus Table 41. Local Bus Timing Parameters (BV Parameter Local bus clock to output high Impedance (except LAD/LDP and LALE) Local bus clock to output high impedance for LAD/LDP Notes: 1. The symbols used for timing specifications follow the ...

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Figure 23 through Figure 28 show the local bus signals. LSYNC_IN Input Signals: LAD[0:31]/LDP[0:3] Input Signal: LGTA LUPWAIT Output Signals: LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Table 42 describes the timing parameters of the ...

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Local Bus Table 42. Local Bus Timing Parameters—PLL Bypassed (continued) Parameter Local bus clock to address valid for LAD Local bus clock to LALE assertion Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus ...

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Internal Launch/Capture Clock LCLK Input Signals: LAD[0:31]/LDP[0:3] Input Signal: LGTA LUPWAIT Output Signals: LA[27:31]/LBCTL/LBCKE/LOE/ LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Figure 24. Local Bus Signals (PLL Bypass Mode) In PLL bypass mode, LCLK[n] ...

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Local Bus LSYNC_IN T1 T3 GPCM Mode Output Signals: LCS[0:7]/LWE GPCM Mode Input Signal: LGTA UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 25. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL ...

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Internal Launch/Capture Clock T1 T3 LCLK GPCM Mode Output Signals: LCS[0:7]/LWE GPCM Mode Input Signal: LGTA UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV ...

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Local Bus LSYNC_IN GPCM Mode Output Signals: LCS[0:7]/LWE GPCM Mode Input Signal: LGTA UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 27. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = ...

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Internal Launch/Capture Clock LCLK GPCM Mode Output Signals: LCS[0:7]/LWE GPCM Mode Input Signal: LGTA UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 28. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] ...

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JTAG 12.1 JTAG DC Electrical Characteristics Table 43 provides the DC electrical characteristics for the JTAG interface. Table 43. JTAG DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage 1 Input current ( ...

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Table 44. JTAG AC Timing Specifications (Independent of SYSCLK) Parameter JTAG external clock to output high impedance: Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of t The output timings are measured at the ...

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I C Figure 32 provides the boundary-scan timing diagram. JTAG External Clock Boundary Data Inputs t JTKLDX Boundary Data Outputs Boundary Output Data Valid Data Outputs This section describes the DC and AC electrical characteristics ...

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Electrical Specifications Table 46 provides the AC timing parameters for the I Parameter SCL clock frequency Low period of the SCL clock High period of the SCL clock Setup time for a repeated START condition ...

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PCI/PCI-X Figure 29 provides the AC test load for the I Output Figure 34 shows the AC timing diagram for the I SDA t I2CF t I2CL SCL t I2SXKL S 14 PCI/PCI-X This section describes the DC and AC ...

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PCI/PCI-X AC Electrical Specifications This section describes the general AC timing parameters of the PCI/PCI-X bus. Note that the clock reference CLK is represented by SYSCLK when the PCI controller is configured for asynchronous mode and by PCIn_CLK when ...

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PCI/PCI-X Figure 36 shows the PCI/PCI-X input AC timing conditions. CLK Input Figure 36. PCI/PCI-X Input AC Timing Measurement Conditions Figure 37 shows the PCI/PCI-X output AC timing conditions. Output Delay High-Impedance Figure 37. PCI/PCI-X Output AC Timing Measurement Condition ...

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Table 49. PCI-X AC Timing Specifications at 66 MHz (continued) Parameter HRESET to PCI-X initialization pattern hold time Notes: 1. See the timing measurement conditions in the PCI-X 1.0a Specification . 2. Minimum times are measured at the package pin ...

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High-Speed Serial Interfaces (HSSI) Table 50. PCI-X AC Timing Specifications at 133 MHz (continued) Parameter HRESET to PCI-X initialization pattern hold time Notes: 1. See the timing measurement conditions in the PCI-X 1.0a Specification . 2. Minimum times are measured ...

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Using this waveform, the definitions are as follows. To simplify the illustration, the following definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment. 1. Single-ended swing The transmitter output signals and the receiver ...

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High-Speed Serial Interfaces (HSSI) SD_TX or SD_RX A Volts SD_TX or SD_RX B Volts Figure 38. Differential Voltage Definitions for Transmitter or Receiver To illustrate these definitions using real values, consider the case of a CML (current mode logic) transmitter ...

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The maximum average current requirement that also determines the common mode voltage range: — When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin ...

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High-Speed Serial Interfaces (HSSI) average voltage (common mode voltage between 100 and 400 mV. SerDes reference clock input requirement for DC-coupled connection scheme. — For external AC-coupled connection, there is no common mode voltage requirement for the clock ...

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SD_REF_CLK Input Amplitude < 800 mV SD_REF_CLK SD_REF_CLK Figure 42. Single-Ended Reference Clock Input DC Requirements 15.2.3 Interfacing With Other Differential Signaling Levels • With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are HCSL ...

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High-Speed Serial Interfaces (HSSI) Figure 43 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC levels of the clock driver chip is compatible with MPC8548E SerDes reference clock input’s DC requirement. ...

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AC-coupling. Its value could be ranged from 140 to 240 Ω depending on the clock driver vendor’s requirement used together with the SerDes reference clock receiver’s 50-Ω termination resistor to attenuate the LVPECL output’s differential ...

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PCI Express 15.2.4 AC Requirements for SerDes Reference Clocks The clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and ...

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DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK For more information, see Section 15.2, “SerDes Reference Clocks.” 16.2 AC Requirements for PCI Express SerDes Clocks Table 51 lists the AC requirements for the PCI Express SerDes clocks. Table 51. ...

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PCI Express Table 52. Differential Transmitter (TX) Output Specifications (continued) Symbol Parameter V De- emphasized TX-DE-RATIO differential output voltage (ratio) T Minimum TX eye TX-EYE width T Maximum time TX-EYE-MEDIAN-to- between the MAX-JITTER jitter median and maximum deviation from the ...

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Table 52. Differential Transmitter (TX) Output Specifications (continued) Symbol Parameter T Minimum time TX-IDLE-MIN spent in electrical idle T Maximum time TX-IDLE-SET-TO-IDLE to transition to a valid electrical idle after sending an electrical idle ordered set T Maximum time TX-IDLE-TO-DIFF-DATA ...

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PCI Express Table 52. Differential Transmitter (TX) Output Specifications (continued) Symbol Parameter T Crosslink crosslink random timeout Notes test load is necessarily associated with this value. 2. Specified at the measurement point into a timing and voltage compliance ...

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RX-DIFF (D+ D– Crossing Point) Figure 48. Minimum Transmitter Timing and Voltage Output Compliance Specifications 16.4.3 Differential Receiver (RX) Input Specifications Table 53 defines the specifications for the differential input at all receivers (RXs). The parameters ...

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PCI Express Table 53. Differential Receiver (RX) Input Specifications (continued) Symbol Parameter V AC peak RX-CM-ACp common mode input voltage RL Differential RX-DIFF return loss RL Common mode RX-CM return loss Z DC differential RX-DIFF-DC input impedance Z DC input ...

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Table 53. Differential Receiver (RX) Input Specifications (continued) Symbol Parameter L Total Skew TX-SKEW Notes test load is necessarily associated with this value. 2. Specified at the measurement point and measured over any 250 consecutive UIs. The test ...

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PCI Express The eye diagram must be valid for any 250 consecutive UIs. A recovered calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive UI ...

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Serial RapidIO This section describes the DC and AC electrical specifications for the RapidIO interface of the MPC8548E, for the LP-Serial physical layer. The electrical specifications cover both single- and multiple-lane links. Two transmitters (short and long run) and ...

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Serial RapidIO 17.3 Signal Definitions LP-serial links use differential signaling. This section defines terms used in the description and specification of differential signals. waveforms for either a transmitter output (TD and TD receiver input (RD and RD). Each ...

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Explanatory Note on Transmitter and Receiver Specifications AC electrical specifications are given for transmitter and receiver. Long- and short-run interfaces at three baud rates (a total of six cases) are described. The parameters for the AC electrical specifications are ...

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Serial RapidIO Table 56. Short Run Transmitter AC Timing Specifications—2.5 GBaud Characteristic Symbol Output voltage V O Differential output voltage V DIFFPP Deterministic jitter J D Total jitter J T Multiple output skew S MO Unit interval UI Table 57. ...

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Table 59. Long Run Transmitter AC Timing Specifications—2.5 GBaud Characteristic Symbol Output voltage V O Differential output voltage V DIFFPP Deterministic jitter J D Total jitter J T Multiple output skew S MO Unit interval UI Table 60. Long Run ...

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Serial RapidIO transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol interference) need only comply with the transmitter output compliance mask when pre-emphasis is disabled or minimized. V max DIFF V min DIFF 0 –V min DIFF –V ...

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The reference impedance for return loss measurements is 100-Ω resistive for differential return loss and 25-Ω resistive for common mode. Table 62. Receiver AC Timing Specifications—1.25 GBaud Characteristic Differential input voltage Deterministic jitter tolerance ...

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Serial RapidIO Table 64. Receiver AC Timing Specifications—3.125 GBaud Characteristic Differential input voltage Deterministic jitter tolerance Combined deterministic and random jitter tolerance 1 Total jitter tolerance Multiple input skew Bit error rate Unit interval Note: 1. Total jitter is composed ...

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Receiver Eye Diagrams For each baud rate at which an LP-serial receiver is specified to operate, the receiver shall meet the corresponding bit error rate specification receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion ...

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Serial RapidIO is specified as the test pattern for use in eye pattern and jitter measurements. Annex 48B of IEEE Std. 802.3ae-2002 is recommended as a reference for additional information on jitter test methods. 17.9.1 Eye Template Measurements For the ...

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Package Description This section details package parameters, pin assignments, and dimensions. 18.1 Package Parameters The package parameters for both the HiCTE FC-CBGA and FC-PBGA are as provided in Parameter Package outline Interconnects Ball pitch Ball diameter (typical) Solder ball ...

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Package Description 18.2 Mechanical Dimensions of the HiCTE FC-CBGA and FC-PBGA with Full Lid Figure 55 shows the mechanical dimensions and bottom surface nomenclature for both the MPC8548E HiCTE FC-CBGA and FC-PBGA package with full lid. Notes: imensions are in ...

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Pinout Listings The DMA_DACK[0:1] and TEST_SEL/TEST_SEL pins must be set to a proper state during POR configuration. Please refer to the pinlist table of the individual device for more details. For MPC8548/47/45, GPIOs are still available on PCI1_AD[63:32]/PC2_AD[31:0] pins ...

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Package Description Table 67. MPC8548E Pinout Listing (continued) Signal PCI1_REQ[4:1] PCI1_REQ0 PCI1_CLK PCI1_DEVSEL PCI1_FRAME PCI1_IDSEL PCI1_REQ64/PCI2_FRAME PCI1_ACK64/PCI2_DEVSEL PCI2_CLK PCI2_IRDY PCI2_PERR PCI2_GNT[4:1] PCI2_GNT0 PCI2_SERR PCI2_STOP PCI2_TRDY PCI2_REQ[4:1] PCI2_REQ0 MDQ[0:63] MECC[0:7] MDM[0:8] MDQS[0:8] MDQS[0:8] MA[0:15] MBA[0:2] MPC8548E PowerQUICC™ III Integrated Processor Hardware ...

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Table 67. MPC8548E Pinout Listing (continued) Signal MWE MCAS MRAS MCKE[0:3] MCS[0:3] MCK[0:5] MCK[0:5] MODT[0:3] MDIC[0:1] LAD[0:31] LDP[0:3] LA[27] LA[28:31] LCS[0:4] LCS5/DMA_DREQ2 LCS6/DMA_DACK2 LCS7/DMA_DDONE2 LWE0/LBS0/LSDDQM[0] LWE1/LBS1/LSDDQM[1] LWE2/LBS2/LSDDQM[2] LWE3/LBS3/LSDDQM[3] LALE LBCTL LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LOE/LSDRAS LGPL3/LSDCAS LGPL4/LGTA/LUPWAIT/LPBSE LGPL5 LCKE LCLK[0:2] MPC8548E PowerQUICC™ ...

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Package Description Table 67. MPC8548E Pinout Listing (continued) Signal LSYNC_IN LSYNC_OUT DMA_DACK[0:1] DMA_DREQ[0:1] DMA_DDONE[0:1] UDE MCP IRQ[0:7] IRQ[8] IRQ[9]/DMA_DREQ3 IRQ[10]/DMA_DACK3 IRQ[11]/DMA_DDONE3 IRQ_OUT EC_MDC EC_MDIO EC_GTX_CLK125 Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_RXD[7:0] TSEC1_TXD[7:0] TSEC1_COL TSEC1_CRS TSEC1_GTX_CLK TSEC1_RX_CLK TSEC1_RX_DV TSEC1_RX_ER TSEC1_TX_CLK ...

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Table 67. MPC8548E Pinout Listing (continued) Signal Three-Speed Ethernet Controller (Gigabit Ethernet 2) TSEC2_RXD[7:0] TSEC2_TXD[7:0] TSEC2_COL TSEC2_CRS TSEC2_GTX_CLK TSEC2_RX_CLK TSEC2_RX_DV TSEC2_RX_ER TSEC2_TX_CLK TSEC2_TX_EN TSEC2_TX_ER Three-Speed Ethernet Controller (Gigabit Ethernet 3) TSEC3_TXD[3:0] TSEC3_RXD[3:0] TSEC3_GTX_CLK TSEC3_RX_CLK TSEC3_RX_DV TSEC3_RX_ER TSEC3_TX_CLK TSEC3_TX_EN Three-Speed Ethernet ...

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Package Description Table 67. MPC8548E Pinout Listing (continued) Signal IIC1_SCL IIC1_SDA IIC2_SCL IIC2_SDA SD_RX[0:7] SD_RX[0:7] SD_TX[0:7] SD_TX[0:7] SD_PLL_TPD SD_REF_CLK SD_REF_CLK Reserved Reserved Reserved Reserved GPOUT[24:31] HRESET HRESET_REQ SRESET CKSTP_IN CKSTP_OUT TRIG_IN TRIG_OUT/READY/QUIESCE MSRCID[0:1] MSRCID[2:4] MDVAL CLK_OUT MPC8548E PowerQUICC™ III Integrated ...

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Table 67. MPC8548E Pinout Listing (continued) Signal RTC SYSCLK TCK TDI TDO TMS TRST L1_TSTCLK L2_TSTCLK LSSD_MODE TEST_SEL THERM0 THERM1 ASLEEP GND OV DD MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6 Freescale Semiconductor Package Pin Number Clock AF16 ...

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Package Description Table 67. MPC8548E Pinout Listing (continued) Signal AVDD_LBIU AVDD_PCI1 AVDD_PCI2 AVDD_CORE AVDD_PLAT AVDD_SRDS SENSEVDD SENSEVSS MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6 ...

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Table 67. MPC8548E Pinout Listing (continued) Signal MVREF SD_IMP_CAL_RX SD_IMP_CAL_TX SD_PLL_TPA Notes: 1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the local bus controller section, and is not ...

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Package Description Table 67. MPC8548E Pinout Listing (continued) Signal 25.These are test signals for factory use only and must be pulled up (100 Ω–1 kΩ 26.Independent supplies derived from board V 27.Recommend a pull-up resistor (~1 kΩ) be ...

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Table 68 provides the pin-out listing for the MPC8547E 783 FC-PBGA package. All note references in the following table use the same numbers as those for Table 67. The reader should refer to notes. Signal PCI1_AD[63:32] PCI1_AD[31:0] PCI1_C_BE[7:4] PCI1_C_BE[3:0] PCI1_PAR64 ...

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Package Description Table 68. MPC8547E Pinout Listing (continued) Signal Reserved Reserved cfg_pci1_clk Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MDQ[0:63] MECC[0:7] MDM[0:8] MDQS[0:8] MDQS[0:8] MA[0:15] MBA[0:2] MWE MCAS MRAS MCKE[0:3] MCS[0:3] MCK[0:5] MCK[0:5] MODT[0:3] MDIC[0:1] MPC8548E PowerQUICC™ III Integrated ...

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Table 68. MPC8547E Pinout Listing (continued) Signal LAD[0:31] LDP[0:3] LA[27] LA[28:31] LCS[0:4] LCS5/DMA_DREQ2 LCS6/DMA_DACK2 LCS7/DMA_DDONE2 LWE0/LBS0/LSDDQM[0] LWE1/LBS1/LSDDQM[1] LWE2/LBS2/LSDDQM[2] LWE3/LBS3/LSDDQM[3] LALE LBCTL LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LOE/LSDRAS LGPL3/LSDCAS LGPL4/LGTA/LUPWAIT/LPBSE LGPL5 LCKE LCLK[0:2] LSYNC_IN LSYNC_OUT DMA_DACK[0:1] DMA_DREQ[0:1] DMA_DDONE[0:1] UDE MCP MPC8548E PowerQUICC™ III Integrated ...

Page 102

Package Description Table 68. MPC8547E Pinout Listing (continued) Signal IRQ[0:7] IRQ[8] IRQ[9]/DMA_DREQ3 IRQ[10]/DMA_DACK3 IRQ[11]/DMA_DDONE3 IRQ_OUT EC_MDC EC_MDIO EC_GTX_CLK125 Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_RXD[7:0] TSEC1_TXD[7:0] TSEC1_COL TSEC1_CRS TSEC1_GTX_CLK TSEC1_RX_CLK TSEC1_RX_DV TSEC1_RX_ER TSEC1_TX_CLK TSEC1_TX_EN TSEC1_TX_ER Three-Speed Ethernet Controller (Gigabit Ethernet ...

Page 103

Table 68. MPC8547E Pinout Listing (continued) Signal TSEC2_TX_ER Three-Speed Ethernet Controller (Gigabit Ethernet 3) TSEC3_TXD[3:0] TSEC3_RXD[3:0] TSEC3_GTX_CLK TSEC3_RX_CLK TSEC3_RX_DV TSEC3_RX_ER TSEC3_TX_CLK TSEC3_TX_EN Three-Speed Ethernet Controller (Gigabit Ethernet 4) TSEC4_TXD[3:0]/TSEC3_TXD[7:4] TSEC4_RXD[3:0]/TSEC3_RXD[7:4] TSEC4_GTX_CLK TSEC4_RX_CLK/TSEC3_COL TSEC4_RX_DV/TSEC3_CRS TSEC4_TX_EN/TSEC3_TX_ER UART_CTS[0:1] UART_RTS[0:1] UART_SIN[0:1] UART_SOUT[0:1] IIC1_SCL IIC1_SDA ...

Page 104

Package Description Table 68. MPC8547E Pinout Listing (continued) Signal Reserved Reserved SD_PLL_TPD SD_REF_CLK SD_REF_CLK Reserved Reserved Reserved Reserved GPOUT[24:31] HRESET HRESET_REQ SRESET CKSTP_IN CKSTP_OUT TRIG_IN TRIG_OUT/READY/QUIESCE MSRCID[0:1] MSRCID[2:4] MDVAL CLK_OUT RTC SYSCLK TCK TDI TDO TMS TRST MPC8548E PowerQUICC™ III ...

Page 105

Table 68. MPC8547E Pinout Listing (continued) Signal L1_TSTCLK L2_TSTCLK LSSD_MODE TEST_SEL THERM0 THERM1 ASLEEP GND MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6 Freescale Semiconductor Package Pin Number DFT AC25 AE22 ...

Page 106

Package Description Table 68. MPC8547E Pinout Listing (continued) Signal AVDD_LBIU AVDD_PCI1 AVDD_PCI2 AVDD_CORE AVDD_PLAT AVDD_SRDS SENSEVDD SENSEVSS MVREF SD_IMP_CAL_RX SD_IMP_CAL_TX SD_PLL_TPA Note: All note references in this table use the same numbers ...

Page 107

Table 69 provides the pin-out listing for the MPC8545E 783 FC-PBGA package. All note references in the following table use the same numbers as those for Table 67. The reader should refer to notes. Signal PCI1_AD[63:32]/PCI2_AD[31:0] PCI1_AD[31:0] PCI1_C_BE[7:4]/PCI2_C_BE[3:0] PCI1_C_BE[3:0] PCI1_PAR64/PCI2_PAR ...

Page 108

Package Description Table 69. MPC8545E Pinout Listing (continued) Signal PCI2_PERR PCI2_GNT[4:1] PCI2_GNT0 PCI2_SERR PCI2_STOP PCI2_TRDY PCI2_REQ[4:1] PCI2_REQ0 MDQ[0:63] MECC[0:7] MDM[0:8] MDQS[0:8] MDQS[0:8] MA[0:15] MBA[0:2] MWE MCAS MRAS MCKE[0:3] MCS[0:3] MCK[0:5] MCK[0:5] MODT[0:3] MDIC[0:1] LAD[0:31] LDP[0:3] MPC8548E PowerQUICC™ III Integrated Processor ...

Page 109

Table 69. MPC8545E Pinout Listing (continued) Signal LA[27] LA[28:31] LCS[0:4] LCS5/DMA_DREQ2 LCS6/DMA_DACK2 LCS7/DMA_DDONE2 LWE0/LBS0/LSDDQM[0] LWE1/LBS1/LSDDQM[1] LWE2/LBS2/LSDDQM[2] LWE3/LBS3/LSDDQM[3] LALE LBCTL LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LOE/LSDRAS LGPL3/LSDCAS LGPL4/LGTA/LUPWAIT/LPBSE LGPL5 LCKE LCLK[0:2] LSYNC_IN LSYNC_OUT DMA_DACK[0:1] DMA_DREQ[0:1] DMA_DDONE[0:1] UDE MCP IRQ[0:7] IRQ[8] IRQ[9]/DMA_DREQ3 IRQ[10]/DMA_DACK3 MPC8548E PowerQUICC™ ...

Page 110

Package Description Table 69. MPC8545E Pinout Listing (continued) Signal IRQ[11]/DMA_DDONE3 IRQ_OUT EC_MDC EC_MDIO EC_GTX_CLK125 Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_RXD[7:0] TSEC1_TXD[7:0] TSEC1_COL TSEC1_CRS TSEC1_GTX_CLK TSEC1_RX_CLK TSEC1_RX_DV TSEC1_RX_ER TSEC1_TX_CLK TSEC1_TX_EN TSEC1_TX_ER GPIN[0:7] GPOUT[0:5] cfg_dram_type0/GPOUT6 GPOUT7 Reserved Reserved Reserved Reserved FIFO1_RXC2 ...

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Table 69. MPC8545E Pinout Listing (continued) Signal TSEC3_RXD[3:0] TSEC3_GTX_CLK TSEC3_RX_CLK TSEC3_RX_DV TSEC3_RX_ER TSEC3_TX_CLK TSEC3_TX_EN TSEC3_TXD[7:4] TSEC3_RXD[7:4] Reserved TSEC3_COL TSEC3_CRS TSEC3_TX_ER UART_CTS[0:1] UART_RTS[0:1] UART_SIN[0:1] UART_SOUT[0:1] IIC1_SCL IIC1_SDA IIC2_SCL IIC2_SDA SD_RX[0:3] SD_RX[0:3] SD_TX[0:3] SD_TX[0:3] Reserved Reserved Reserved Reserved SD_PLL_TPD SD_REF_CLK MPC8548E PowerQUICC™ ...

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Package Description Table 69. MPC8545E Pinout Listing (continued) Signal SD_REF_CLK Reserved Reserved Reserved Reserved GPOUT[24:31] HRESET HRESET_REQ SRESET CKSTP_IN CKSTP_OUT TRIG_IN TRIG_OUT/READY/QUIESCE MSRCID[0:1] MSRCID[2:4] MDVAL CLK_OUT RTC SYSCLK TCK TDI TDO TMS TRST L1_TSTCLK L2_TSTCLK LSSD_MODE MPC8548E PowerQUICC™ III Integrated ...

Page 113

Table 69. MPC8545E Pinout Listing (continued) Signal TEST_SEL THERM0 THERM1 ASLEEP GND MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6 Freescale Semiconductor Package Pin Number AH14 Thermal Management AG1 ...

Page 114

Package Description Table 69. MPC8545E Pinout Listing (continued) Signal AVDD_LBIU AVDD_PCI1 AVDD_PCI2 AVDD_CORE AVDD_PLAT AVDD_SRDS SENSEVDD SENSEVSS MVREF SD_IMP_CAL_RX SD_IMP_CAL_TX SD_PLL_TPA Note: All note references in this table use the same numbers as those ...

Page 115

Table 70 provides the pin-out listing for the MPC8543E 783 FC-PBGA package. All note references in the following table use the same numbers as those for Table 67. The reader should refer to notes. Signal Reserved GPOUT[8:15] AB18, AA19, AB19, ...

Page 116

Package Description Table 70. MPC8543E Pinout Listing (continued) Signal Reserved Reserved Reserved Reserved cfg_pci1_clk Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MDQ[0:63] B17, A13, B12, C18, B18, B13, A12, H18, F18, D7, B5, B4, A2, B1, D1, E4, A3, ...

Page 117

Table 70. MPC8543E Pinout Listing (continued) Signal LAD[0:31] K22, B28, D27, D19, J22, K20, D28, D25, B25, LDP[0:3] LA[27] LA[28:31] LCS[0:4] LCS5/DMA_DREQ2 LCS6/DMA_DACK2 LCS7/DMA_DDONE2 LWE0/LBS0/LSDDQM[0] LWE1/LBS1/LSDDQM[1] LWE2/LBS2/LSDDQM[2] LWE3/LBS3/LSDDQM[3] LALE LBCTL LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LOE/LSDRAS LGPL3/LSDCAS LGPL4/LGTA/LUPWAIT/LPBSE LGPL5 LCKE LCLK[0:2] LSYNC_IN LSYNC_OUT ...

Page 118

Package Description Table 70. MPC8543E Pinout Listing (continued) Signal IRQ[0:7] AG23, AF18, AE18, AF20, AG18, AF17, AH24, IRQ[8] IRQ[9]/DMA_DREQ3 IRQ[10]/DMA_DACK3 IRQ[11]/DMA_DDONE3 IRQ_OUT EC_MDC EC_MDIO EC_GTX_CLK125 Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_RXD[7:0] TSEC1_TXD[7:0] TSEC1_COL TSEC1_CRS TSEC1_GTX_CLK TSEC1_RX_CLK TSEC1_RX_DV TSEC1_RX_ER TSEC1_TX_CLK ...

Page 119

Table 70. MPC8543E Pinout Listing (continued) Signal Reserved FIFO1_TXC2 cfg_dram_type1 Three-Speed Ethernet Controller (Gigabit Ethernet 3) TSEC3_TXD[3:0] TSEC3_RXD[3:0] TSEC3_GTX_CLK TSEC3_RX_CLK TSEC3_RX_DV TSEC3_RX_ER TSEC3_TX_CLK TSEC3_TX_EN TSEC3_TXD[7:4] TSEC3_RXD[7:4] Reserved TSEC3_COL TSEC3_CRS TSEC3_TX_ER UART_CTS[0:1] UART_RTS[0:1] UART_SIN[0:1] UART_SOUT[0:1] IIC1_SCL IIC1_SDA IIC2_SCL IIC2_SDA SD_RX[0:7] SD_RX[0:7] ...

Page 120

Package Description Table 70. MPC8543E Pinout Listing (continued) Signal SD_REF_CLK SD_REF_CLK Reserved Reserved Reserved Reserved GPOUT[24:31] HRESET HRESET_REQ SRESET CKSTP_IN CKSTP_OUT TRIG_IN TRIG_OUT/READY/QUIESCE MSRCID[0:1] MSRCID[2:4] MDVAL CLK_OUT RTC SYSCLK TCK TDI TDO TMS TRST L1_TSTCLK L2_TSTCLK MPC8548E PowerQUICC™ III Integrated ...

Page 121

Table 70. MPC8543E Pinout Listing (continued) Signal LSSD_MODE TEST_SEL THERM0 THERM1 ASLEEP GND W6, W19, Y4, Y9, Y11, Y19, AA6, AA14, AA17, P25, R28, T24, T26, U24, V25, W28, Y24, Y26, AA24, AA27, AB25, AC28, L21, L23, N22, P20, OV ...

Page 122

Package Description Table 70. MPC8543E Pinout Listing (continued) Signal BV C21, C24, C27, E20, E25, G19, G23, H26, J20 DD V M19, N12, N14, N16, N18, P11, P13, P15, P17, DD P19, R12, R14, R16, R18, T11, T13, T15, T17, ...

Page 123

Table 70. MPC8543E Pinout Listing (continued) Signal SD_IMP_CAL_TX SD_PLL_TPA Note: All note references in this table use the same numbers as those for meanings of these notes. 19 Clocking This section describes the PLL configuration of the MPC8548E. Note that ...

Page 124

Clocking Table 73. Processor Core Clocking Specifications (MPC8543E) Characteristic e500 core processor frequency Notes: 1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, ...

Page 125

Table 76. Memory Bus Clocking Specifications (MPC8543E) Characteristic Memory bus clock speed Notes: 1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) ...

Page 126

Clocking 19.3 e500 Core PLL Ratio Table 78 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This ratio is determined by the binary value of LBCTL, LALE, and LGPL2 at power up, ...

Page 127

Thermal This section describes the thermal specifications of the MPC8548. 20.1 Thermal for Version 2.0 Silicon HiCTE FC-CBGA with Full Lid This section describes the thermal specifications for the HiCTE FC-CBGA package for revision 2.0 silicon. Table 80 shows ...

Page 128

System Design Information Table 81. Package Thermal Characteristics for FC-PBGA (continued) Characteristic Die junction-to-case Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of ...

Page 129

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide independent filter circuits per PLL power supply as illustrated in AV pins. By providing independent filters to each PLL the ...

Page 130

System Design Information 1.0 Ω Note 0805 sized capacitor is recommended for system initial bring-up. Note the following: • AV _SRDS should be a filtered version • Signals on the SerDes interface are ...

Page 131

Where the board does not have blind vias, these capacitors should be placed in a ring around the device as close to the supply and ground connections as possible. • Second, there ...

Page 132

System Design Information Table 82 summarizes the signal impedance targets. The driver impedances are targeted at minimum V nominal OV , 105°C. DD Local Bus, Ethernet, DUART, Control, Impedance Configuration, Power Management Note: Nominal supply voltages. ...

Page 133

The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up devices. 21.9 JTAG Configuration Signals Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in ...

Page 134

System Design Information as shown in Figure 62. If this is not possible, the isolation resistor will allow future access to TRST in case a JTAG interface may need to be wired onto the system in future debug situations. • ...

Page 135

SRESET From Target Board Sources (if any) HRESET KEY 13 No pin COP Connector 1 ...

Page 136

System Design Information 21.10 Guidelines for High-Speed Interface Termination This section provides the guidelines for high-speed interface termination when the SerDes interface is entirely unused and when it is partly unused. 21.10.1 SerDes Interface Entirely Unused If the high-speed SerDes ...

Page 137

SD_REF_CLK It is recommended to power down the unused lane through SRDSCR1[0:7] register (offset = 0xE_0F08) (this prevents the oscillations and holds the receiver output in a fixed state) that maps to SERDES lane 0 to lane 7 accordingly. ...

Page 138

Ordering Information includes an application modifier which may specify special application conditions. Each part number also contains a revision code which refers to the die mask revision number. MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6 138 Freescale Semiconductor ...

Page 139

MPC nnnnn t Product Part Temperature Code Identifier MPC 8548E Blank = 0 to 105° –40° to 105°C 8548 8547E 8547 8545E 8545 8543E 8543 Notes: 1. See Section 18, “Package Description,” 2. The HiCTE FC-CBGA package is ...

Page 140

Ordering Information 22.2 Part Marking Parts are marked as the example shown in Notes : TWLYYWW is final test traceability code. MMMMM is 5 digit mask number. CCCCC is the country of assembly. This space is left blank if parts ...

Page 141

Document Revision History Table 84 provides a revision history for the MPC8548E hardware specification. Revision Date 6 12/2009 • In Section 5.1, “Power-On Ramp avoid falsely triggering ESD circuitry. • In Table 10 changed required ramp rate from 545 ...

Page 142

Document Revision History Table 84. Document Revision History (continued) Revision Date 3 01/2009 • [Section 4.6, “Platform Frequency Requirements for PCI-Express and Serial RapidIO.” minimum frequency equation to be 527 MHz for PCI x8. • In Table 5, added note ...

Page 143

Table 84. Document Revision History (continued) Revision Date 1 10/2007 • Adjusted maximum SYSCLK frequency down in device erratum GEN-13. • Clarified notes to • Added Section 4.4, “PCI/PCI-X Reference Clock • Clarified descriptions and added PCI/PCI-X to • Removed ...

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... Power.org. IEEE 802.3, 802.2, 802.1, and 1149.1 are registered trademarks of the Institute of Electrical and Electronics Engineers, Inc. (IEEE). This product is not endorsed or approved by the IEEE. © Freescale Semiconductor, Inc., 2009. All rights reserved. ...