MBM29F016-90PFTR Fujitsu, MBM29F016-90PFTR Datasheet

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MBM29F016-90PFTR

Manufacturer Part Number
MBM29F016-90PFTR
Description
N/A
Manufacturer
Fujitsu
Datasheet

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MBM29F016-90PFTR
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FUJI
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FUJITSU SEMICONDUCTOR
FLASH MEMORY
CMOS
16 M ( 2 M 8 ) BIT
MBM29F016
Embedded Erase
• Single 5.0 V read, write, and erase
• Compatible with JEDEC-standard commands
• 48-pin TSOP
• Minimum 100,000 write/erase cycles
• High performance
• Sector erase architecture
• Embedded Erase
• Embedded Program
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/BUSY output (RY/BY)
• Low power consumption
• Enhanced power management for standby mode
• Low V
• Hardware RESET pin
• Erase Suspend/Resume
• Sector group protection
DISTINCTIVE CHARACTERISTICS
Minimizes system level power requirements
Pinout and software compatible with single-power supply Flash
Superior inadvertent write protection
90 ns maximum access time
Uniform sectors of 64K bytes each
Any combination of sectors can be erased. Also supports full chip erase.
Automatically pre-programs and erases the chip or any sector
Automatically programs and verifies data at specified address
Hardware method for detection of program or erase cycle completion
40 mA maximum active read current
60 mA maximum program/erase current
<1 A typical standby current
Standard access time from standby mode
Resets internal state machine to the read mode
Supports reading or programming data to a sector not being erased
Hardware method that disables any combination of sector groups from write or erase operation (a sector group
consists of 4 adjacent sectors of 64K bytes each)
DATA SHEET
CC
write inhibit
and Embedded Program
Algorithms
Algorithms
3.2 V
are trademarks of Advanced Micro Devices, Inc.
- 90/-12
DS05–20807–3E

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MBM29F016-90PFTR Summary of contents

Page 1

... FUJITSU SEMICONDUCTOR DATA SHEET FLASH MEMORY CMOS BIT MBM29F016 DISTINCTIVE CHARACTERISTICS • Single 5.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Pinout and software compatible with single-power supply Flash Superior inadvertent write protection • ...

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... MBM29F016 -90/-12 PACKAGE Marking side FPT-48P-M19 2 Marking side FPT-48P-M20 ...

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... GENERAL DESCRIPTION The MBM29F016 is a 16M-bit, 5.0 V-Only Flash memory organized as 2M bytes of 8 bits each. The 2M bytes of data is divided into 32 sectors of 64K bytes for flexible erase capability. The 8 bit of data will appear on DQ0 to DQ7. The MBM29F016 is offered in a 48-pin TSOP package. This device is designed to be programmed in-system with the standard system 5 ...

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... MBM29F016 -90/-12 FLEXIBLE SECTOR-ERASE ARCHI- TECTURE • Thirty two 64K byte sectors • 8 sector groups each of which consists of 4 ad- jacent sectors in the following pattern; sectors 0- 3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28- 31 • Individual-sector or multiple-sector erase capa- bility • Sector group protection is user-definable 4 1FFFFFh SA 31 64K byte ...

Page 5

... Detector –90 10% — Erase Voltage Generator Program Voltage Chip Enable Generator Output Enable Logic Y-Decoder STB Address Timer Latch X-Decoder MBM29F016 -90/-12 MBM29F016 — –12 120 120 Input/Output Buffers STB Data Latch Y-Gating Cell Matrix 5 ...

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... MBM29F016 37 Standard Pinout FPT-48P-M19 (Marking side MBM29F016 36 Reverse Pinout FPT-48P-M20 N. RY/ ...

Page 7

... RESET RY/BY Table 2 MBM29F016 User Bus Operations Operation Auto-Select Manufacturer Code (1) Auto-Select Device Code (1) Read (3) Standby Output Disable Write Enable Sector Group Protection (2) Verify Sector Group Protection (2) Temporary Sector Group Unprotection Reset (Hardware) Legend ...

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... ORDERING INFORMATION Standard Products Fujitsu standard products are available in several packages. The order number is formed by a combination of: MBM29F016 –90 PFTN DEVICE NUMBER/DESCRIPTION MBM29F016 16 Mega-bit (2M 5.0 V-only Read, Write, and Erase 64 K bytes (32 Sectors) 8 PACKAGE TYPE PFTN = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout ...

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... Read Mode The MBM29F016 has two control functions which must be satisfied in order to obtain data at the outputs the power control and should be used for a device selection the output control and should be used to gate data to the output pins if a device is selected. ...

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... MBM29F016 -90/-12 Table 3 MBM29F016 Sector Protection Verify Autoselect Codes Type Manufacturer’ Code X Device Code Sector Group Sector Group V Protection Addresses * Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses SA0 0 0 SA1 ...

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... Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Sector Group Protection The MBM29F016 features hardware sector group protection. This feature will disable both program and erase opera- tions in any combination of eight sector groups of memory. Each sector group consists of four adjacent sectors grouped in the following pattern: sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31 (see Table 5) ...

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... MBM29F016 -90/-12 Table 6 MBM29F016 Command Definitions Bus First Bus Command Write Write Cycle Sequence Cycles Req'd Addr Read/Reset* 1 XXXH Reset/Read* 3 555H Autoselect 3 555H Byte Program 4 555H Chip Erase 6 555H Sector Erase 6 555H Erase can be suspended during sector erase with Addr (H or L), Data (B0H) ...

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... while ( ( will produce a logical “1” at device Algorithm command sequence, the system is not required to is equivalent to data written to this bit at 7 Algorithm using typical command strings and bus operations. MBM29F016 -90/-12 13 ...

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... MBM29F016 -90/-12 address (any address location within the desired sector) is latched on the falling edge while the command (Data = 30H) is latched on the rising edge After time-out from the rising edge of the last sector erase command, the sector erase operation will begin. ...

Page 15

... DQ 7 Data Polling The MBM29F016 device features Data Polling as a method to indicate to the host that the embedded algorithms are in progress or completed. During the Embedded Program complement of the data last written to DQ read the device will produce the true data last written to DQ read the device will produce a “ ...

Page 16

... DQ 6 Toggle Bit I The MBM29F016 also features the “Toggle Bit I” method to indicate to the host system that the embedded algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read ( OE toggling) data from the device at any address will result in DQ Algorithm cycle is completed, DQ will stop toggling and valid data will be read on the next successive attempts ...

Page 17

... Embedded Erase 2 bit toggles 7 0 toggles 1 DQ (2) toggles 7 toggles only when the standard program or Erase, or Erase Suspend Pro- 6 MBM29F016 -90/-12 will 3 may low (“0”), the device will 3 were high on the 3 Algorithm Algorithm. If the toggles 1 ...

Page 18

... RY/BY Ready/Busy The MBM29F016 provides a RY/ BYopen-drain output pin as a way to indicate to the host system that the Embed- ded Algorithms are either in progress or has been completed. If the output is low, the device is busy with either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase operation. ...

Page 19

... Power-up of the device with = WE CE internal state machine is automatically reset to the read mode on power-up will not initiate a write cycle initiate a write cycle and will not accept commands on the rising edge MBM29F016 -90/-12 and must The WE 19 ...

Page 20

... A V Supply Voltages CC V for MBM29F016-90 ................................................................................+4. +5. for MBM29F016-12 ................................................................................+4. +5. Operating ranges define those limits between which the functionality of the device is guaranteed RESET (Note 1) .....–2 +7 +2.0 V for periods ns RESET pins are –0.5 V. During voltage transitions – ...

Page 21

... MAXIMUM OVERSHOOT +0.8 V –0.5 V –2.0 V Figure 1 Maximum Negative Overshoot Waveform 2.0 V Figure 2 Maximum Positive Overshoot Waveform MBM29F016 -90/-12 21 ...

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... MBM29F016 -90/-12 DC CHARACTERISTICS TTL/NMOS Compatible Parameter Parameter Description Symbol I LI Input Leakage Current I Outputs Leakage Current OE, RESET Inputs Leakage 9 I LIT Current I V Active Current (Note 1) CC1 CC I CC2 V Active Current (Note CC3 V Current (Standby Current (Standby, Reset) CC4 ...

Page 23

... CC Notes: 1. The I current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). CC The frequency component typically is 2 mA/MHz, with active while Embedded Algorithm (program or erase progress. CC MBM29F016 Test Conditions Max ...

Page 24

... MBM29F016 -90/-12 AC CHARACTERISTICS Read only Operations Characteristics Parameter Symbols Description JEDEC Standard t t Read Cycle Time AVAV RC t Address to Output Delay t AVQV ACC t t Chip Enable to Output Delay ELQV CE t Output Enable to Output Delay t GLQV OE t Chip Enable to Output High-Z t EHQZ DF Output Enable to Output High-Z ...

Page 25

... Min. Min. Min. Min. Polling Min. Data Min. Min. Min. Min. Min. Typ. Typ. Max. Min. Min. Active (Note 2) Min. WE Active (Note 2) Min. WE Min. BY Delay Min. MBM29F016 -90/-12 –90 –12 Unit 90 120 ...

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... MBM29F016 -90/-12 AC/CHARACTERISTICS • Write/Erase/Program Operations Alternate CE Controlled Writes Parameter Symbols JEDEC Standard t t Write Cycle Time AVAV Address Setup Time AVEL Address Hold Time ELAX Data Setup Time DVEH Data Hold Time EHDX DH t Output Enable Setup Time ...

Page 27

... May Will Be Change Changing from from Changing, Any Change State Permitted Unknown Does Not Center Line is Apply High- Impedance “Off” State t RC Addresses Stable t ACC OEH t CE Output Valid MBM29F016 -90/- High-Z 27 ...

Page 28

... MBM29F016 -90/-12 3rd Bus Cycle Addresses 555H GHWL A0H Data t DS 5.0V Notes address of the memory location to be programmed data to be programmed at byte address the output of the complement of the data written to the device the output of the data written to the device. ...

Page 29

... D is the output of the data written to the device. OUT 5. Figure indicates last two bus cycles of four bus cycle sequence. Figure 6 Alternate CE Controlled Program Operation Timings MBM29F016 Data Polling WHWH1 ...

Page 30

... MBM29F016 -90/-12 555H Addresses CE t GHWL WPH t DH Data AAH VCS CC Note the sector address for Sector Erase. Addresses = 555H for Chip Erase. Figure 7 AC Waveforms Chip/Sector Erase Operations 2AAH 555H 555H 2AAH t AS 55H ...

Page 31

... CE t OEH WE t OES OE Data DQ = Toggle 6 ( *DQ stops toggling (The device has completed the Embedded operation). 6 Figure 9 AC Waveforms for Toggle Bit I During Embedded Algorithm Operations MBM29F016 High Valid Data High =Invalid 6 Valid Data ...

Page 32

... MBM29F016 -90/- RY/BY Figure 10 RY/BY Timing Diagram During Program/Erase Operations RESET 32 The rising edge of the last WE signal t BUSY READY Figure 11 RESET Timing Diagram Entire programming or erase operations ...

Page 33

... 12V VLHT 12V VLHT WE t CSP CE Data SGAX: Sector Group Address for initial sector SGAY: Sector Group Address for next sector Figure 12 AC Waveforms for Sector Group Protection SGAX t VLHT t WPP t OESP MBM29F016 -90/-12 SGAY 01H ...

Page 34

... MBM29F016 -90/- RESET RY/BY Figure 13 Temporary Sector Group Unprotection Enter Erase Embedded Suspend Erasing WE Erase Erase Suspend Read Toggle DQ2 and DQ6 with OE Note read from the erase-suspended sector Program or Erase Command Sequence VLHT Enter Erase ...

Page 35

... EMBEDDED ALGORITHMS Increment Address Program Command Sequence (Address/Command): Figure 15 Embedded Programming Algorithm MBM29F016 Start Write Program Command Sequence (See below) Data Polling Device No Last Address ? Yes Programming Completed 555H/AAH 2AAH/55H 555H/A0H Program Address/Program Data -90/-12 35 ...

Page 36

... MBM29F016 -90/-12 EMBEDDED ALGORITHMS Chip Erase Command Sequence (Address/Command): 555H/AAH 2AAH/55H 555H/80H 555H/AAH 2AAH/55H 555H/10H Note: To insure the command has been accepted, the system software should check the status of DQ and following each subsequent sector erase command command may not have been accepted. ...

Page 37

... No DQ Read Byte (DQ Addr = VA DQ Note rechecked even Figure 17 Data Polling Algorithm MBM29F016 Start VA = Byte address for programming Any of the sector addresses within the sector being erased during sector erase operation Yes = Any of the sector group address ...

Page 38

... MBM29F016 -90/-12 Note rechecked even changing to “1” Start Read Byte ( Addr = Toggle? 6 Yes Yes Read Byte ( Addr = Toggle? 6 Yes Fail Pass = “1” because DQ may stop toggling at the same time as DQ ...

Page 39

... Data = 01H? PLSCNT = 25? Yes Remove V from Protect Another Sector Write Reset Command Group? Remove V Device Failed Write Reset Command Sector Protection Completed Figure 19 Sector Group Protection Algorithm MBM29F016 , Yes ...

Page 40

... MBM29F016 -90/-12 Notes: 1. All protected sector groups unprotected. 2. All previously protected sector groups are protected once again. Figure 20 Temporary Sector Group Unprotection Algorithm 40 Start RESET = V ID (Note 1) Perform Erase or Program Operations RESET = V IH Temporary Sector Group Unprotection Completed (Note 2) ...

Page 41

... Unit Typ. Max. — sec — 8 2000 sec — — 1,000,000 Cycles Test Setup OUT MBM29F016 -90/-12 Comments Excludes 00H programming prior to erasure Excludes system-level over- s head Excludes system-level over- head Typ. Max. Unit 6 7 ...

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... MBM29F016 -90/-12 PACKAGE DIMENSIONS 48-Pin Standard Thin Small Outline Package LEAD No. 1 INDEX 24 20.00±0.20 (.787±.008) * 18.40±0.20 (.724±.008) 0.10(.004) 19.00±0.20 (.748±.008) 1994 FUJITSU LIMITED F48029S-1C-1 C 48-Pin Reversed Thin Small Outline Package LEAD No. 1 INDEX 24 19.00±0.20 (.748±.008) ...

Page 43

... Singapore 189554 Tel: 336-1600 Fax: 336-1609 P9603 FUJITSU LIMITED Printed in Japan MBM29F016 All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Com- plete Information sufficient for construction purposes is not nec- essarily given. The information contained in this document has been carefully checked and is believed to be reliable ...

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