AT32UC3A3256 Atmel Corporation, AT32UC3A3256 Datasheet - Page 206
AT32UC3A3256
Manufacturer Part Number
AT32UC3A3256
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 206 of 1012
- Download datasheet (16Mb)
15.6.8
15.6.8.1
Figure 15-30. Read and Write Cycles in Slow Clock Mode
32072G–11/2011
NBS0, NBS1,
A[AD_MSB:2]
A0, A1
CLK_SMC
NWE
NCS
Slow Clock Mode
Slow clock mode waveforms
SLOW CLOCK MODE WRITE
1
NWECYCLES = 3
The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when
an internal signal driven by the SMC’s Power Management Controller is asserted because
CLK_SMC has been turned to a very slow clock rate (typically 32 kHz clock rate). In this mode,
the user-programmed waveforms are ignored and the slow clock mode waveforms are applied.
This mode is provided so as to avoid reprogramming the User Interface with appropriate wave-
forms at very slow clock rate. When activated, the slow mode is active on all chip selects.
Figure 15-30 on page 206
valid on all chip selects.
ters in slow clock mode.
Table 15-5.
Read Parameters
NRDSETUP
NRDPULSE
NCSRDSETUP
NCSRDPULSE
NRDCYCLE
1
Read and Write Timing Parameters in Slow Clock Mode
1
Duration (cycles)
Table 15-5 on page 206
illustrates the read and write operations in slow clock mode. They are
1
1
0
2
2
Write Parameters
NWESETUP
NWEPULSE
NCSWRSETUP
NCSWRPULSE
NWECYCLE
NBS0, NBS1,
A[AD_MSB:2]
indicates the value of read and write parame-
A0, A1
CLK_SMC
NRD
NCS
SLOW CLOCK MODE READ
NRDCYCLES = 2
1
Duration (cycles)
1
1
0
3
3
1
206
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